Computer Aided Design 2008 Computer Aided Design Course (Spring 2008) I Jivet (B112 - A207) and A Avram (B126 ) Syllabus A. Lectures
1.lecture objective presentation. Device and Circuits models. - SPICE models, Swich level models for CMOS 2. Entry Level Tools. OrCAD and Mentor Graphics - Schematic Entry, State Diagrames and ecuations - Libraries, Instantiations and Editing, Hierachic schemes - EDIF 3. HDL Representations of Circuits (VERILOG) - Functional/structural descriptions, block general form - Simulation control ( #, @ ) 4. PCB Design - Partitioning using chain/tree - Auto route startegies - Quality assesment 5. FEM Field Modeling. MathLab simulation Tools - FEM method outline. Segmentation. Boundary conditions. - MathLab general introduction. Simulink B. Lab 1 Models, libraries and technology files. IRSIM example 2. OrCA Scematic entry , flat, hierarchy designs (diagrams) 3. Mentro Graphics simulation 3. Verilog descriptions examples. Active-VHDL simulation. 4. PCB design project. 5. Qfield FEM case study. 6. MathLab Simlink explorartion D. BIBLIOGRAFY 1. A Campeanu, I Jivet OrCAD III 2. OrCAD Manuals 3. Mentor Graphics Users Manual. Tutorials 4. MathLab Teora 1993 OrCAD Mentor Graphics 1 lab 2 lab (2 h) 3 lab (4 h) 3 lab 2 lab 2 lab 1 lab 1 lecture 5 lectures (2 h) (10 h)

3 lectures 2 lectures

(6 h) (4 h)

3 lectures

(6 h)

(6 h) (6 h) (4 h) (4 h) (2 h)

General Definition: Computer-aided design (CAD) is the use of computer technology to aid in the design of a product. Fields of Use Architecture......

Electronic Engineering

............ Office and Arts

Electronic Design Dutomation (EDA)

Designing and producing electronic systems ranging from schematic, printed circuit boards (PCBs) to integrated circuits. Electronic Design Tools - Schematic Capture


Simulate a circuit's operation so as to verify correctness and performance. •Transistor Simulation – low-level simulation of a schematic/layout's behavior device-level. • – digital-simulation of an RTL or gate-netlist's digital (boolean 0/1) behavior, •Behavioral Simulation – high-level simulation of a design's architecture, cycle-level or interface • – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called in-circuit emulation. EDIF stands for Electronic Design Interchange Format, and has been predominantly used as a neutral format in which to sth Electronic net-lists and schematics. ViewTypes •SCHEMATIC to describe the schematic representation and connectivity of a cell •NETLIST to describe a netlist •BEHAVIOR to describe the behavior of a cell •LOGICMODEL to describe the logic-simulation model of the cell •MASKLAYOUT to describe an integrated circuit layout •PCBLAYOUT to describe a printed circuit board •SYMBOLIC to describe a symbolic layout PCB Layout

Levels of representation.

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High Level Languages Circuit Description Verilog (VHDL) – a simple yet very use full Hardware Description Language.

Although Higher Levels are possible: (RTL) The circuit is modeled at a - low level of abstraction.

A LOGIC VERIFICATION and a immediate Simulation for validation are possible with minimum of effort.


Test Signals are entered using a Graphical UI.

Electric Fields FEM Modeling Given a conducting or dielectric medium the electric field in the medium produces by a series of sources is modeled numerically (solutions of Laplace Eq.) by Finite Element Method. User specifies: - 1.Geometry of Space – 2.Boundary Data - (V, I sources) - 3.Space Finite Element Density

The results of U, I, E, D, Q,…..In Color Plots or …Tables of Values …

MathLab Computational and Simulation Environment Computations, Simulations and Graphics…..

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