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Limitations and Parallel-Port Interface Documentation of the HungChang DSO-2100 PC-Based Oscilloscope

A while ago I needed to do some automated data acquisition and happened to be in
possession of the DSO-2100 PC-based digital storage oscilloscope made by Hung Chang
(Seoul, Korea) and sold under brand names like Protek or Voltcraft. Unfortunately, Hung
Chang went bankrupt in 2001, and driver software that could be linked to user programs,
though advertised in the instrument brochure, had never been made available. At least
that's what I was told. I therefore had to analyze the Visual-Basic program that comes
with the instrument.
Along the way I found that the DSO 2100 differs in important respects from the
specifications stated in the instrument brochure and (until 2004) on the Hung-Chang
website, and also (until 2005) by Conrad Electronic, a German electronics chain store
where the instrument was on sale. Thus, you cannot acquire data from both inputs
simultaneously, and only 5000 data points per trigger event are made available for
uploading to the host! I felt quite annoyed when I realized this.
I also learned that, prior to the bankruptcy, a new Korean company called MITech, Inc.
had taken over the Test & Measurement Department of Hung Chang, but their engineers
preferred not to answer my technical questions. Since 2005, Hung Chang continues as
GSI Co., Inc. in Incheon, Korea, and the DSO 2100 (or Protek 2100) still receives
support on the website of their chinese subsidiary, HCQ Electronics Co., Ltd. in Qingdao.
I am herewith placing the results of my analysis on the Web. A simple test driver written
in Turbo Pascal that implements DSO-2100 control via the parallel port can be obtained
from the author and may serve as a starting point for programs of your own. Please direct
requests, as well as comments and notifications of mistakes to Clicliclic.
A friendly correspondent, Anton Zechner, from Austria has contributed an upgrade utility
(http://www.mikrocontroller.net/topic/56876) to make your DSO2100.EXE run under
Windows NT or 2K or XP. Be sure to have a German dictionary around. And don't ask
me for support on this!
© Copyright 2002, 2004, 2006 by Clicliclic. All rights reserved.

0. Remarks on DSO-2100 Limitations
- the DSO 2100 must be operated on a bi-directional parallel port (with the host BIOS
configured accordingly!): only the eight data lines (pins 2-9) and the STROBE (pin 1),

and 107th are skipped and the 128th is omitted! (Here. such as electromagnetic pulses generated by switching on the room lighting.data reloaded from previously stored *. Briefly unplug the power supply of the DSO unit to recover from this.) You can easily uncover the frequency holes by means of a tunable oscillator. however. Ch B: 100 MSa/s. Old unidirectional ports won't do! AUTO-FEED . and there are no data windowing options. Most unbelievably. although the digitization channel is equipped with 32+32 kB RAM.digital data from the DSO unit always include 6 or 7 data points preceding the trigger event .the Fourier transform for the spectrum display is based on 2^8 = 256 samples (and thus generates only 2^7+1 = 129 data points in frequency). .a pleasant surprise for a change! The trigger. The sparkle is easily seen when a suitable signal is heavily "undersampled".even though the DSO unit prepares only 5000 samples for uploading. 64th. In either case. the ADC (actually two alternating HI5714s) begins to show glitches: the lower five bits gradually fail (folding section of the converter) while the upper three bits continue to function (subranging section of the converter). Consequently. the effect is dependent on the vertical offset setting! . as also stated in the instrument brochure! .for each data acquisition completed. INIT (pin 16). the DSO unit has only one digitization channel which is switched between the two analog input channels: capture of both inputs requires two successive trigger events even for single-shot acquisition. the 21st. This falls far short of a memory depth of 32 kB/Ch. the on-board intelligence (an ADSP-2105 processor with 8 kB OTP EPROM and a QL2003 FPGA) makes only 5000 samples available to the host. Dual: 100 MSa/s").dso files are vertically expanded relative to the measured signal as originally displayed.(pin 14). causing a time jitter of two sampling intervals! . the spectral points are numbered from zero.at slew rates of about 3Div / 10ns. data displayed during Scroll Mode measurements are vertically contracted relative to signals measured otherwise. resulting in non-corresponding signals! .signal attenuation is comparatively unimportant here!). The inefficiency should be attributed to a bug in the DSO firmware. may cause the communication between PC and DSO to hang up. . of the 129 spectral points only 125 are actually displayed. .electromagnetic interference. On the other hand. .in contrast to what the accompanying brochure suggests ("Ch A: 100 MSa/s. their acquisition takes twice as long as needed for 5000 consecutive data points. the maximum repetition rate of the DSO 2100 at low scan speeds is only half of what one would expect. but remains invisible in ordinary work. The behavior is in agreement with the "analog input bandwidth" specification of the HI5714 (provided the Harris/Intersil datasheet is read correctly . and SELECT-IN (pin 17) control lines are wired. is accepted only before every other sample.

you may have to break and restart the process repeatedly.even for shorted inputs.. The contamination is influenced by the various amplifier and trigger settings. i.. . Control Sequences Employed by DSO2100.6 Div) followed by a train of weaker equidistant (640 ns) peaks.{R01} S04R0f. .e. I have prepared a description of what can be done about some of the hardware problems (mainly trigger instability and calibration drift) of the DSO 2100. whence calibration drift results in a progressive (and ultimately prohibitive) signal distortion for measurements from 50 ms/Div (10 kSa/s) to 0.. with acquisition times exceeding 0. suggesting bad routing on the PCB.the auto-calibration procedure quite frequently fails to terminate within reasonable time. 1. and triggering to be bistable without exception. . in striking contrast with negative-slope triggering: for rapid transitions the trigger comparator (LM361) seems to suffer from some kind of ringing.3 Div p-p that may at first sight be taken for analog noise.{R01} S02{R00}{R21} {S99{R21}} S99{R00}{R03} {L} AUTO-trigger acquisition: S04R0f..{R01} S04R0f.and finally.positive-slope triggering on fast signals (such as the 1 kHz calibration signal measured with a 10÷1 probe) is unreliable (frequent false release on negative slopes).EXE NORM-trigger acquisition without signal: S04R0f. .5 V/Div and 50 mV/Div.5 s/Div (1 kSa/s). obvious features are stronger isolated spikes (occasionally up to ?0.the DSO amplifiers stop drifting and recalibration becomes unnecessary only after roughly one hour of warming-up and thermal equilibration! .. the distinction of slopes seems to be lost as well. For slow signals like a 50 Hz sine wave.for open inputs there is a significant capacitive coupling from the EXT trigger signal onto CH2 at 0. this is sometimes (at 50 MSa/s) accompanied by a constant signal at half the sampling frequency.{R01} S04R0f.5 s. for daring fellow owners.the on-board analog calibration settings (stored in 1 µF capacitors gated by an HC4051) are not refreshed during acquisition.{R01} S02{R00}{R21} {S99{R21}} NORM-trigger acquisition with signal: S04R0f...{R01} S02{R00}{R21} S02{R00}{R21} S02{R00}{R21} S02{R00}{R21} S99{R00}{R03} {L} S99{R21} S99{R00}{R03} {L} S99{R21} S99{R21} S99{R00}{R03} {L} S99{R21} S99{R21} S99{R21} Sfe{R21} . at acquisition rates above 5 MSa/s (especially at 50 and 100 MSa/s) the data from my unit show a digital contamination of up to 0. .

03. DSO-2100 Setup-Parameter Transfer R0f S01 R0f S01 R05 S02 R05 S02 R08 S02 R08 S02 ready for transfer select Acq CH1 (01. 3.. Sfe. MSa/s) repeat readout2 step + 1 (02.C. R14 indicates Scroll Acquisition Active (scroll acquisition timing is determined by the host data requests!). {L} Sff{R0f}.Rxx.{R01} S03{R00}{R03} {L} scroll acquisition: S04R0f.S02 starts a 5000-sample acquisition with selection of 500+500 readout points. it stays on after a reselection.the LED indicator on top of the DSO unit lights up for any status but hex 03 (Acquisition Complete / Data Ready) after an acquisition. and L stand for Receive Status Byte.S99{R00}{R03} {L} and so on repeating {S99..0b) repeat ...25.E. respectively. Sxx. and Load Data Byte.10 . Sfe supplies AUTO trigger. R03 indicates Acquisition Complete / Data Ready.. S99 leaves acquisition if complete...02 = CH1. .. . ....03 ... respectively.. {R21} Sff{R00}{R03} {L} reselect readout: S04R0f. 2.{R01} .05 . The corresponding parallel-port operations are detailed in sections 3. S99.50.R00 indicates On-board Processor Busy / Illegal Command. .the sequence R0f. S99. Sff breaks acquisition.02.20.CH2) repeat set 50 MSa/s (01. = 100. . S03 starts a reselection of 500+500 readout points from the previous data. Notes: .to my knowledge.D.{R01} S04 {{R14}{L}} scroll-acquisition break: ... the commands listed here exhaust those accepted by the DSO unit. Send Command Byte. S99.} acquisition break: . and 3.04. R21 indicates Waiting for Trigger / Acquiring.R01 transfers setup parameters to the DSO. {} indicates repetition. S04 starts a scroll acquisition / a new setup-parameter transfer. it is explicated in section 2. where xx represents the transferred byte in hex.

readout2 step.15.20..31.03 .80 = Trig AC. = 0.02. 5 V/Div.20 .04.2.02 = neg.AC) (01.CH2) repeat set CH2 AC.5..20m.pos) repeat Cal CH1 V-Offset + 1 repeat Cal CH2 V-Offset + 1 repeat Trig Level + 1 repeat Cal CH1 Offset + 1 repeat Cal CH1 Gain + 1 repeat Cal CH2 Offset + 1 repeat Cal CH2 Gain + 1 repeat transfer done Notes: .TV-H) repeat readout2 shift (01.30.1.02. 5 V/Div.22.33 = 10m. Trig CH1 (00.10.the purpose of the readout1 step.80 = Trig CH1.TV-V.0.0..03.08 = DC.R09 S0b R09 S0b R06 S3b V/Div) R06 S3b R07 S3b R07 S3b R0a S01 R0a S01 R0b S02 R0b S02 R0c S66 R0c S66 R0d S5d R0d S5d R0e S80 R0e S80 R10 Saa R10 Saa R11 S7c R11 S7c R12 S89 R12 S89 R13 Sba R13 Sba R01 readout1 step + 1 (02. and readout2 shift parameters is .50m.EXT.32.0.1.2.5.05 .0b) repeat set CH1 AC.) repeat set Trig Slope pos (01.21.40.GND.40.5 (00. Trig AC (00..04.

SLCTIN+ . DX EAX. Receive DSO status: . 000000FF ESI. . port . AL DX. 00000002 EAX. read status byte . set ECP hardware to emulate a B. AL DX. DWORD PTR [ESI] DWORD PTR [ESI]. 00000402 EAX.AUTO+ INIT.SLCTIN+ .the V-Offset. and Gain calibration constants are stored in the file DSO2100.SLCTIN+ Note: . STROBE+ AUTO+ INIT. DSO-2100 Parallel-Port Code from VKVXD. DWORD PTR [EBP+08] EDX. DWORD PTR [ESI] EDX. 00000020 DX. AL .E. AL DX. 00000020 DX.explained in section 3.5 V/Div settings. 3. DWORD PTR [EBP+08] EDX. (+ 402 !) . AL ESI.the new parameter settings become effective only with the subsequent command (S02. 00000002 EAX. STROBE. the PCB is apparently not equipped for a variable trigger level! . AL DX. or S04). STROBE+ AUTO+ INIT. C. . AL EAX. . Verify DSO connection: LEA MOV ADD MOV OUT OUT OUT OUT OUT OUT MOV OUT LEA MOV IN AND LEA MOV MOV ADD MOV OUT ESI.VXD A. DWORD PTR [ESI] EDX. Offset. port .INI. DWORD PTR [ESI] AL.a status of hex 55 is returned if the DSO is present. 00000020 DX. DWORD PTR [EBP+0C] ESI. EAX EDX. . 00000021 DX. S03. DWORD PTR [EBP+08] EDX. . . AL DX.EXE seems to keep the trigger level fixed at 50% (hex 7f). Change DSO2100. their advantage is a reduced noise level.DSO2100.EXE at hex file offset 29782 from hex 20 to hex 03 and at hex file offset 297c6 from hex 10 to hex 03 to see this. Initialize DSO port: LEA MOV ADD MOV OUT BPP ESI. .hex 03 and hex 23 are alternative codes for the 50 mV/Div and 0. AL . .

SLCTIN- . DX EAX. 0000002A DX. Send DSO command: LEA MOV ADD MOV OUT LEA MOV LEA MOV OUT OUT OUT ADD MOV OUT MOV OUT MOV OUT OUT MOV OUT MOV OUT ESI.SLCTIN+ . . 00000002 EAX. .INIT+ SLCTIN+ . port . DWORD PTR EDX.INIT. 00000002 EAX.INIT. AL DX. . write command byte .AUTO. AL EAX. DWORD PTR ESI. STROBE+ AUTO. DWORD PTR [EBP+0C] ESI. 00000024 DX. 00000006 DX. AL DX. AL DX. . DWORD PTR [ESI] DWORD PTR [ESI]. read status byte .INIT+ SLCTIN+ . port . DWORD PTR DX. 000000FF ESI. STROBE+ AUTO. DWORD PTR [EBP+08] EDX. STROBE. AL E. 00000022 DX. DWORD PTR EAX. STROBE+ AUTO. AL EDX. 00000006 DX. AL . . DWORD PTR EDX. AL ESI. port . (28 = AUTO+ for CH2) . AL EAX. AL EAX. AL EAX. EAX EDX. AL EAX. DWORD PTR [EBP+08] EDX. AL DX. 00000007 DX.INIT+ SLCTIN+ [EBP+08] [ESI] [EBP+0C] [ESI] ESI. 00000002 EAX. DWORD PTR [ESI] EDX. AL DX.AUTO.SLCTIN+ .SLCTIN+ . STROBE. AL D. STROBE+ AUTO. . 00000006 DX. DWORD PTR [ESI] EDX. STROBE+ AUTO.INIT+ SLCTIN+ . AL ESI. 00000022 DX. STROBE+ AUTO+ INIT+ SLCTIN+ . 00000023 DX.INIT. Load DSO data (CH1): LEA MOV ADD MOV OUT [EBP+08] [ESI] . AL EAX. 00000022 DX. 00000026 DX. .INIT. DWORD PTR [EBP+08] EDX. 00000002 EAX. 00000024 DX.LEA MOV ADD MOV OUT OUT MOV OUT OUT LEA MOV IN AND LEA MOV MOV ADD MOV OUT MOV OUT MOV OUT ESI. 00000002 EAX. DWORD PTR EDX. DWORD PTR [ESI] AL. STROBE+ AUTO. STROBE+ AUTO+ INIT+ SLCTIN+ . AL EAX.

followed by 500 points selected according to the readout2 step and shift parameters. 00000002 EAX. EBX . DWORD PTR [EBP+0C] ESI.data after a 5000-sample acquisition for one input channel consist of 500 points selected according to the readout1 step parameter. . 0000002B DX. 2004. .AUTO. (28 = AUTO+ for CH2) . EAX EDX. DWORD PTR [ESI] AL. readout2 starts at the original data point selected as the (n+1)th point of readout1 and proceeds in steps of readout2 step. AL ESI.SLCTIN.during scroll acquisition.MOV OUT LEA MOV IN AND MOV ADD MOV OUT LEA MOV MOV EAX. hex fe. 000000FF EBX. .to load CH2 data substitute hex 28/29 for hex 2a/2b. Hung-Chang DSO-2100 Hardware Faults and Remedies . DWORD PTR [EBP+08] EDX.the original 5000 samples are available after hex 2000 bytes (8 kB). followed by the bytes hex 01. DWORD PTR [ESI] DWORD PTR [ESI]. and hex 80. Load Data delivers the previous data. STROBE. the intervening and subsequent bytes are mostly set to a pattern of hex 00 and ff (presumably the power-on state). 0000002A DX. AL ESI. © Copyright 2002. after an acquisition break. 2006 by Clicliclic. followed by a repeat of points 301 through 400 from readout2.readout1 starts at the 1st point of the original data and proceeds in steps of readout1 step. read data byte . where n is the value coded by the readout2 shift parameter. . STROBE+ AUTO. it delivers part new and part old data. (29 = AUTO+ for CH2) .SLCTIN- Notes: . data points are loaded one at a time (scroll acquisition timing is determined by the host data requests!).INIT.INIT. the whole data repeat after hex 4000 bytes (16 kB). data in the acquisition RAM are not affected. DX EAX.data are retained in the acquisition RAM until overwritten: when acquisition / reselection is on hold. All rights reserved. .

All rights reserved. the "WARNING" sticker covering the fifth (the center) screw must be punched or removed. with some massaging of the frequency response) followed by a PNP level shifter (2N3906) and another HFA1130 gain block (unfortunately.) The description refers to the particulars of my board (labelled REV 2100 . The linearity of the DSO amplifiers is good. but the gain of the differential stage depends on the voltage level at its inverting input. for center setting the data are expanded about 2. (Conrad were selling the DSO 2100 across Europe. Needless to say.) Some resistors and capacitors in the amplifiers are (?regularly) adjusted by hand soldering at the factory in order to trim the offset (R110. Rise Time.In this description. The gain correction is taken into account . 2006 by Clicliclic. and Thermal Drift The DSO amplifiers have the usual high-impedance FET input stage (a cascode of two 2SK161s. but relevant deviations are mentioned insofar as they were brought to my attention. as well as the frequency response (C34. Comments and notifications of mistakes should be directed to Clicliclic. (The hardware would need to be modified if you want to acquire the two channels in parallel. Amplifier Linearity. The amplifiers drive two parallel HI5714/6 (=TDA8714/6) ADCs supplied with ping-pong clocking of up to 50MHz to achieve acquisition rates of up to 100MSa/s. © Copyright 2004. In order to open the DSO-2100 unit.just ask them to mail you one. and for the uppermost position the data are expanded twice as much (displayed range 0 to 243). where the top FET operates as a source follower and the bottom FET as a constant-current active load) followed by a HFA1130 (current-feedback amplifier) gain block followed by a discrete differential stage where the screen offset is added (three 2N3904 jelly beans.4% (displayed range 0 to 249). other boards may differ. electronic components of the DSO 2100 are referred to by their designations on the oscilloscope schematic and board. The expansion appears to be uniform. It's a shame the unit was marketed at this immature stage. 0.02) and the components on it (or left out!). You may obtain the schematic from Conrad Electronic. the responsibility for any action regarding your DSO 2100 is yours! Once you have studied the description you will probably concur that the DSO-2100 hardware was insufficiently debugged. C88). R40) calibration ranges. which is controlled by the corresponding vertical offset knob. This gain variation is corrected for in software: for the lowermost knob position the full ADC data are displayed (range 0 to 255). the built-in clipping function of the HFA1130s is not used). and the transformation therefore linear. and they still provide copies of the schematic for free . and not ready for sale. R131) and gain (R12.

on my board some components necessary for this option are left out. In fact. Scroll Mode signals are therefore contracted relative to the screen markings! On the other hand. The thermal drift is caused in part by the FET cascodes (their contribution varies with the Volts/Div setting and may also differ between channels) and in part by the 2N3906 level shifters (whose effect doesn't vary and should dominate at the 5V/Div setting). one may use the drift of the PNP level shifter to estimate the temperature inside the unit.g. it is often too sensitive to high-frequency interference spikes. this kind of noise is strongest when the signal fluctuates across major digital transitions. from about 4ns to about 5ns (these values assume on-resistances around 40 Ohm for the selector switches). There is no simple remedy for this design weakness. Without R-C damping of this order the digital noise seen at high sampling rates (up to about 0. it looks like the trigger . the 1/e decay time of the associated exponential tails varies noticeably.) More disturbingly. at the 5V/Div setting.during auto-calibration. It is also visibly influenced by the combined capacitance (5+25)pF + (5+12)pF + (2*14)pF of a HC4051 trigger source selector plus a HC4052 acquisition channel selector plus the double HI5714 inputs. (Although one of the DAC channels used for calibration is reserved for a variable trigger level. the correction is applied to data reloaded from disk even though saved data are already transformed. 1.) My unit reaches about 20°C above ambient temperature. and the Hung-Chang operating software makes no provision for setting this channel. You will have noticed that the heat generated by the unit (of the order of 10W) makes the amplifier offsets drift for an hour or so after switching on. the unit would have to be equipped with drift-compensated amplifiers. reloaded data are therefore expanded relative to the markings! The DSO signal rise-time of the order of 10ns (10% to 90%) is primarily determined by the discrete differential stage. or the heat kept away from them. once every minute) would be a practical way to deal with the thermal drift. (The signal level at the shifter stage is about 40mV per screen division. but it is omitted in Scroll Mode display. for the typical environment with the SMPS of a PC and a CRT monitor running nearby.3 Div p-p at 100 MSa/s) would most likely be worse. the distinction between positive and negative signal slopes is unsatisfactory even for the simple 1kHz calibration signal. such as from binary 01111111 to 10000000 and back. Trigger Comparator Instability Almost every user must have noticed the shortcomings of the DSO trigger circuitry: in the first place. On-the-fly automatic recalibration of the offset by the DSO software (e. which are all driven by the final HFA1130s via current-limiting resistors of 47 Ohm. assuming a typical -2mV/K for the B-E junction at Ic = -2mA. As the effective capacitance depends on the trigger source setting.

. +----------------------||-----> U36(2) | ''C87 | . C95) feeding 27kOhm (R202. with 47nF (C94. Fault: The trigger stage is AC coupled.. Make absolutely sure your signal is free of highfrequency hidden spikes when looking into trigger stability! . where 200mV at the trigger stage correspond to 1 division on the screen. R202. | +-----||-----+ | | ''C81 | | . the schematic says 75kOhm).8mA typ). (I have also replaced C96 by a 22(?47)-Ohm resistor .. Rapid negative signal transitions (as exhibited by the calibration signal measured with a 10÷1 probe) are therefore regularly (after about 200ns delay) followed by false positive ones whence triggering on positive slopes becomes bistable. as the unit often triggers on negative edges when set for positive ones.5mA clamping current in my case. This is intolerable as you cannot switch to a DC-coupled trigger mode. Fault: C22 = 1. its hysteresis) is about 80mV.comparator U26 (LM361) suffers from internal ringing. Remedy: Upgrade C94 and C95 to 1µF 16V X7R capacitors. I have moved the free 1.the external trigger path doesn't need two 47nF capacitors in series). the datasheet by National says 0. B. Remedy: Replace C22 by a 0-Ohm connection.2 kOhm (!) introduces a kickback from the LM1881 video sync separator U36 (about 0. This high-pass with a corner frequency of 125Hz lowers the trigger sensitivity at low frequencies (expected around 37% for a 50Hz sine wave. | ____ | U43(3) >---|-----||-----+---|____|---+---< U26(11) | ''C22 | R159 | ____ | +---|____|---+---> U26(3) | R30 |¯| | | |_|R202 | === AGND A. C87 is not properly represented on the schematic (compare the sketch below)! The sensitivity of the trigger comparator (i. R30. Watch out: the connection topology around C22.e. and vice versa. Murata makes them in 0805 size.2kOhm resistor to the R30 . measured near 25%) and introduces huge phase shifts (expected almost 70° at 50Hz).

position . Fault: There is no value of R158 that guarantees stable triggering on both positive and negative signal slopes at all board temperatures. but I am informed that the diode stabilization works even with C22 shorted . R159 = 680k supplies the input bias current (about 5µA) during the comparator-high state. for a 50Hz sine wave). Moral: don't place a trigger comparator within 1cm of a supply regulator heat sink.regardless of board temperature! 2.e.5s.5 s/Div). Remedy: Put in R226 = 39k. i. and no static hysteresis. don't forget to adjust C78 too (keeping C78 / 220pF = R226 / 1kOhm)! D. comparator oscillation may trigger data acquisition on a wrong signal slope. As with the LM1881 kickback (see under 1. increase R158 (my board has 39 Ohm dropping 460mV DC. Fault: R226 = 39k was missing on my board. this resistor in the positive supply line of the trigger comparator utilizes the switching current spike boosted by C127 and C78 at output pin 9 to suppress spurious oscillations (about 25MHz) during the negative transitions at output pin 11: sufficiently large resistor values stabilize the negative transitions.maybe the designer had thought about protecting the LM1881 input in this way (note: the copper bridge between the R30 pads has to be cut for this!). in the form of two antiseries connected diodes tacked on by hand soldering and looking much like 1SS133 by Rohm. This would make the removal of C22 = 1. C. By the way. thereby making the trigger level independent of the low-high ratio (5µA * 27kOhm = 135mV !).B). As I see it. Remedy: You have to live with unstable triggering on negative signal slopes while the unit warms up! If the triggering on negative slopes doesn't stabilize at elevated board temperatures. the DSO exhibits an increasingly severe downward . If triggering on positive signal slopes becomes unstable at elevated board temperatures. The trigger comparator then has only dynamic hysteresis with tau = R201*C78 = 10µs. and the trigger stage stabilized instead by adding C81. which prevents stable triggering for slow signal transitions (e. I have also changed C87 = 10n to 47n (the LM1881 datasheet recommends 100nF). If you think about tinkering with the trigger hysteresis. It appears that only a small R158 = 10 Ohm was used on earlier boards labelled REV 2100 . subjecting it to a temperature variation of about 40°C.2 kOhm seem unwise. Sloping Background at Low Scan Speeds At low acquisition rates from 10 kSa/s (50 ms/Div) down to 1 kSa/s (0. decrease R158. which is barely large enough). as shown on the schematic.01.g. but may also destabilize positive ones. for acquisition times exceeding 0.

and this one is in the VRB/VRT reference circuitry of the DSO. The National datasheet specifies an absolute maximum rating of only 15mA! The HI5714 datasheet has this statement: "VRT must be kept within the range of 3. In addition. Out-of-Tolerance Reference Voltage VRT There is yet another blunder. X7R with a much smaller dC/dT should be preferred for this purpose in order to minimize voltage fluctuations resulting from fluctuations in capacitor temperature. VRT = 3.6V.9V is derived from VRB by 2k / 1k multiplication (R178 and R124) in another OpAmp and buffering by a third.16V as the unit warmed up. the input folding amplifiers may saturate giving erroneous digital data. The ADCs combined draw a substantial current of 20mA between VRT and VRB.5V to 3.3V is derived from a LM336-2.my board has a Harris chip. and R178 to 1.5 is fed from the 5V supply via a 100-Ohm resistor (R122). however) with CMOS types (I've used TLC27M4.slope of the background without signal. According to the HI5714 datasheet. the schematic says MC3403. nor does its input common-mode range suffice! Indeed. If the reference voltages go outside their respective ranges. These voltages are used by the two HI5714 ADCs (VRB is also used by the HI1171 DAC). the slope is caused by the input bias current of the KA324 (40nA typ) gradually increasing the charge of the 1µF sample-andhold capacitors C99 to C106! (I had earlier suspected the HC4051 CMOS gate U23. The OpAmps used (U34) are a KA324 (=LM324) quad model. VRB must lie between 1.9V and VRB within 1. which simply isn't capable of delivering 20mA at 3.3k division (R123 and R31) and OpAmp buffering.2V to 1. and VRT between 3.it's just a tradeoff between power consumption and speed. So." Although this doesn't really tell what the consequences of a (slightly drifting) VRT of 3. 3.6V.5 bandgap reference (D7) by 1.2V are. which is here clearly pushed beyond the specified leakage limit of ±100nA at 25°C. The TL064 (BiFET).3V and 3.21V after switching on.2k / 1. VRB = 1. and speed is of no importance here. the specs of which closely resemble the LM324 specs). I measured a VRT around 3. which decreased to about 3.5V and 3. Moreover. R122 should be changed to 1k (2.) I think the ceramic chips used for the 1µF capacitors are 16V types made of Y5V material.2V and 1. the LM336-2.9V from a 5V supply. I would suggest to substitute MC33204 (bipolar rail-to-rail by ON) for U34. and many more may be considered as well.9V.5mA bias current). the TS914 (CMOS rail-to-rail). recommended values are 1.6V. ±1µA at 85°C . respectively.8k in order . I succeeded in getting rid of the slope by replacing the quad sample-and-hold OpAmps U17 and U18 (KA324=LM324. The TLC274 or the TLC27L4 should also have done for U17 and U18 . implying a bias current of 25mA.

All rights reserved.64V (else there might be problems with the HFA1130 output upper limit). its benefit is somewhat uncertain anyway. I suspect the unreasonably high current through the LM336. . © Copyright 2004.16V to 3. it should therefore be bypassed and VRT be taken directly from C25. The TS924 OpAmp (BiCMOS rail-to-rail by SGS-Thomson) might be an alternative substitute for U34. 2006 by Clicliclic. the choice of a resistance ratio corresponding to a rather high target voltage. Such ramifications make this upgrade less than straightforward. and the extra OpAmp buffer are all the result of an abortive attempt to raise VRT to an acceptable level. The gain calibration probably cannot absorb a change of VRT from 3.to bring VRT down 3. so R12 and R40 (330 Ohm on my board) may need to be increased. Because the buffer OpAmp U34C is not isolated from the capacitive load C175 plus C176 (100n+100n) it is likely to oscillate when the output is no longer glued to the positive rail.64V.