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Design and verification of highly complex, trustworthy hardware and software systems have always been a
challenge. The verification of instrumentation and control (I&C) designs still relies heavily on subjective
evaluation. Formal methods have been studied, but often they are only used for certain tasks as indicators of
potential problems. Model checking is a promising approach that theoretically enables complete verification of
the system requirements using exhausting analysis. Due to exhaustive analysis, design errors can be found in
control systems that have already been evaluated using more traditional methods such as testing or simulation.
I have extensively been involved in simulation of functional blocks of I&C systems since my M.Sc degree in
Physics. I completed my M.Sc. at Department of Physics, Government College University, Lahore, Pakistan
with distinction as I stood second in my university with CGPA 3.88/4.0. After my M.Sc. being an active
member of a team for the development of full scope training simulation for Chashma Power Plant, my
responsibility was to simulate the I&C systems. The project gave me insight of large scale systems where safety
and reliability are of prime importance. These large scale systems are usually divided into smaller functional
blocks that perform a specialized operation making it more comprehendible and easier to simulate. Functional
blocks are, these days, being used for verification of I&C systems using model checking during designing stage.
Delays and other time-related operations, which are crucial in many automation system logic designs are very
challenging to design and verify.
During my MS Computational Science and Engineering, I opted for formal verification as my major and studied
graph theory, advanced model checking and Petri nets. I got hands on experience of many model checkers like
HyTech, SMV, Prism, Charlie. Later on I modeled a biological signaling pathway using Petri net theory in my
MS research project. I used Pathway Logic to identify cross talk within insulin signaling pathway and Petri net
tools to determine the structural and dynamic properties of this pathway. I presented a part of this study as
research paper entitled Identification of cross talk in insulin signaling pathway using Pathway Logic in IEEE
ICET-2013 conference. This paper is available online on IEEE explore.
The advanced knowledge of mathematics, practical experience of simulation of functional blocks and MS
degree in computer science (focus on model checking) provides the requisite skill set for pursuing doctoral
research. Post graduate research in model checking will be a great learning experience. The field is in infancy in
Pakistan, therefore, I want to promote its usage in all fields of engineering and sciences. I want to focus my
research on challenge of avoiding state explosion.
A designer models a hardware design as a finite state machine, states the properties the design implements, and
invokes a model checker to verify that the properties are indeed true in every reachable state of the design. As
explicit state model checkers utilize a breadth first search of a very large state space with large states, these
model checkers are slow; sometimes extremely slow. An explicit state model checker enumerates the reachable
states of the model being verified, so the runtime can increase exponentially with the size of the model.
The main challenge in model checking is to deal with the state explosion problem. The number of model states
grows exponentially with the number of model inputs and interacting components. The model is usually based
on a finite state machine (FSM) representation, and a variant of temporal logic is typically used to formulate the
properties. This method often requires a trained tester to express the properties in temporal logic, and is
extremely prone to human error. A lot of manual work and some expertise are still needed.
FPGAs (Field Programmable Gate Arrays) hold the potential for performance improvement when the
application can be reconstructed to take advantage of concurrency, which is the case in explicit-state model
checking. The model checking algorithm implemented on FPGA may avoid the problem of state explosion and
may also accelerate the model checking. The idea is to distribute the whole process of model checking on
computer and FPGA. The model generation, properties formulation, generation of resource matrices etc. and
output handling to be performed on computer while algorithm to be implemented on FPGA. A FPGA
implementation has two advantages. Firstly the ability to pipeline steps such as next state generation and
secondly, the fast, high-bandwidth access to local memory. Fast access to memory is particularly important,
since access to data structures such as the hash table is one of the main bottlenecks.