IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

1281

A 110-nm CMOS 0.7-V Input Transient-Enhanced

Digital Low-Dropout Regulator With 99.98%
Current Efficiency at 80-mA Load
Tak-Jun Oh and In-Chul Hwang, Member, IEEE
Abstract This paper presents a digital low-dropout regulator
(D-LDO) with a proposed transient-response boost technique,
which enables the reduction of transient response time, as well as
overshoot/undershoot, when the load current is abruptly drawn.
The proposed D-LDO detects the deviation of the output voltage
by overshoot/undershoot, and increases its loop gain, for the
time that the deviation is beyond a limit. Once the output
voltage is settled again, the loop gain is returned. With the
D-LDO fabricated on an 110-nm CMOS technology, we measured
its settling time and peak of undershoot, which were reduced
by 60% and 72%, respectively, compared with and without
the transient-response boost mode. Using the digital logic gates,
the chip occupies a small area of 0.04 mm2 , and it achieves
a maximum current efficiency of 99.98%, by consuming the
quiescent current of 15 A at 0.7-V input voltage.
Index Terms Current efficiency, cyclic TDC, digital
low-dropout regulator (D-LDO), fast transient response,
transient-response boost mode (TRBM), voltage-to-time
converter (VTC).

I. I NTRODUCTION

S PORTABLE and battery-powered devices are required

to include more various applications than ever, SOCs
for this purpose are competing with each other to integrate
more features at less power consumption, even aided by energy
harvesting, because the total energy available from a battery
is limited in capacity [1], [2]. This trend imposes a greater
design burden on the power management unit (PMU), because
it should drive superthreshold to subthreshold logic gates
according to various power-saving techniques with its available
peak power efficiency.
The on-chip LDO regulators are gaining more attention as
a dedicated PMU for the near-threshold/subthreshold logic
circuits [3], since they can supply more stable and precise
voltage despite lower power efficiency, compared with the
switching regulators [4], [5].

Manuscript received January 16, 2014; revised May 12, 2014; accepted
June 23, 2014. Date of publication July 16, 2014; date of current version
June 23, 2015. This work was supported by the Basic Science Research
Program through the Ministry of Education, National Research Foundation
of Korea, under Grant 2014R1A1A4A01008906.
T.-J. Oh was with the Department of Electrical Engineering, Kangwon
National University, Chuncheon 200-701, Korea. He is now with
Magnachip Semiconductor Corporation, Seoul 100-712, Korea (e-mail:
tjoh@kangwon.ac.kr).
I.-C. Hwang is with the Integrated Circuits and Systems Laboratory,
Department of Electrical Engineering, Kangwon National University,
Chuncheon 200-701, Korea (e-mail: ihwang@kangwon.ac.kr).
Digital Object Identifier 10.1109/TVLSI.2014.2333755

The power efficiency of an LDO regulator is decided by the

drop-out voltage and its current efficiency, given by the ratio
between quiescent current and load current. Conventional
analog LDO regulators (A-LDO) exhibit difficulties in
maintaining the low drop-out voltage when driving the
near-threshold and subthreshold logic circuits, because the
stacked transistors are needed for high precision. To make
matters worse, the quiescent current should be increased in
proportion to the load current, because more bias current is
consumed to drive bigger power transistors [6].
The D-LDO regulators offer better opportunity in terms of
these issues due to the use of digital logic gates, continuously
enhanced by process scaling [4][11].
Also, the digital segmentation of a big power transistor enables for D-LDO to avoid the consumption of static
quiescent current for static load current, because the minimized
number of bits are toggled to keep the output voltage once the
D-LDO is settled to a target value, so it makes the quiescent
current independent of load current.
For the power-efficient D-LDO, a simple structure
composed of binary comparator and shift register is widely
used, due to the low-level quiescent current [4][7]. But, this
successive approximation register (SAR)-like operation causes
slow loop-tracking speed, because the loop value is updated
by a small fixed step at every clock. Therefore, the only
solution to speed up transient response, is to increase the
clock frequency [10]. The work in [7] solves this problem,
using the asynchronous shift register, instead of the typical
synchronous shift registers. But, it still has a problem, in
that circuit operation is too sensitive to PVT variation, to get
constant performance between chips.
A multibit ADC can provide faster loop operation through
direct measurement of the voltage difference. Also, it allows
for designers to implement the algorithms of more complex
loop compensation and loop acceleration [8][10].
The work in [8] is designed with a direct conversion of
A-LDO into D-LDO using a SAR-type ADC and a separate
DAC driving a single power transistor. But, this design is
not power-efficient because its complex design consumes
additional quiescent current. Another work in [9] employs
a TDC-based 4-b ADC and a PID controller for stability
compensation. In this design, the performance of fast transient
response is achieved through dynamic clock scaling from
normally 250 MHz to 1 GHz.
Thus, it consumes big quiescent current of 2.5 mA. In [10],
the three-level ADC designed with TDC provides the control

1063-8210 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

1282

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 2.

Fig. 1. (a) Block diagram of the proposed D-LDO. (b) Operational waveform.

of charging, discharging, and holding the gate of the power

MOS, respectively, without a PID controller. But, higher
voltage ripple is caused by the insufficient resolution of power
MOS.
Therefore, the D-LDOs focused on low-level quiescent
current have a limit to improve the driving capability and
transient response, on the contrary, the schemes having highlevel driving capability consume more quiescent current than
needed.
In this paper, we propose a new scheme of power-efficient
digital linear LDO regulator based on a multibit cyclic
TDC for high-level current efficiency, while targeting on
driving super-to-near-threshold logic gates. To compensate for
the degraded transient performance, we propose a transientresponse boost circuit, which detects undershoot/overshoot
during transient response, and creates additional asynchronous
clocks only during that time.
The overall structure and operation principle are presented
in Section II. Section III presents the implementation of
major circuits. The measurement results and conclusions are
described in Sections IV and V, respectively.
II. P ROPOSED D-LDO R EGULATOR W ITH
T RANSIENT - R ESPONSE B OOST M ODE
A. Structure and Principle of Operation
Fig. 1(a) shows a block diagram of the proposed
D-LDO, which consists of a voltage-to-time converter (VTC),
phase and polarity detector (PPD), a cyclic TDC, an
UP/DN counter, and a 9-b binary-weighted pMOS array.
With the time resolution of logic gates enhanced more in
deep-submicrometer CMOS processes, a time-domain ADC
can provide higher resolution at low power and small area,
than a voltage-mode or a current-mode ADC.

Tradeoff issue between transient response and voltage ripple.

For power-efficient design, we employ a multibit cyclic

TDC, since it provides fine resolution with less quiescent
current and smaller area, than a flash-type TDC.
First, in this diagram, Vref and Vout are converted to a
pair of pulse streams, ref and out , through the proposed
VTC, where the duty of each pulse is linearly modulated,
according to the magnitude of the input voltage. Fig. 1(b)
shows a set of the operational waveforms, starting from the
output of the VTC. The time difference between ref and out ,
implying the voltage difference between Vref and Vout , is
measured by the phase detector as err , and then digitized by
the cyclic TDC. In operation detail, the cyclic TDC repeatedly
shrinks the pulsewidth of err once a cycle of reference
clock, until the pulsewidth fully disappears. The entire number
of cycles operated in this way is stored in the following
UP/DN counter, and controls the binary-weighted 9-b switch
transistors. In our design, the UP/DN counter is not reset to
zero, but keeps the previous counted value at the end of the
reference cycle in our design, and thus, it works as a low-pass
filter, as well as a part of the cyclic TDC.
B. Transient-Response Boost Mode (TRBM) Operation
Fig. 2 illustrates a typical response of digital regulators to
a step change of the load current. When the load current
(I L ) jumps up from a steady-state condition, as shown in
Fig. 2, Vout is instantly dropped, since the current is drawn
from C L , which is much faster than adjusting the gate of the
power transistor, through the loop response operating at clock
frequency.
The D-LDO takes over the loop control, to correct Vout
after the delay of f , inversely proportional to the closedloop bandwidth. With this property, we need to increase the
bandwidth to reduce f , and to reduce the peak undershoot
at the same time. This goal can be achieved by increasing
the overall size of the pMOS transistors, assuming that all the
other loop conditions are kept unchanged. However, it causes
the voltage ripple to increase, which is unavoidable in such
D-LDO regulators.
To solve this tradeoff issue, we employed a gain-boosting
technique activated only for the transient period, which
is named the transient-response boost mode (TRBM). The
TRBM detector [Fig. 1(a)] monitors the magnitude of the
undershoot/overshoot, then it controls our D-LDO to increase

OH AND HWANG: 110-nm CMOS 0.7-V INPUT TRANSIENT-ENHANCED D-LDO REGULATOR

Fig. 5.
Fig. 3.

Fig. 4.

1283

Block diagram of cyclic TDC and the TRBM detector.

Circuit diagram of the proposed VTC.

Circuit diagram of PPD.

the loop gain as needed, if Vout goes beyond a predetermined

boundary condition. Once Vout is reduced to within the boundary values, the loop gain returns to smaller normal value.
III. C IRCUIT D ESIGN
A. Voltage-to-Time Converter
Fig. 3 shows a simplified circuit diagram of the proposed
VTC, which consists of a half-period sawtooth generator, and a
voltage comparator. While ck is low, C1 and C2 are charged by
I M2 and I M3 , until Va and Vb reach VDD , and then Va and Vb
are reset to zero as ck goes high.
Using the half-period sawtooth clocks generated in this
block, the comparators create the clocks of ref and out , with
their duty ratio modulated by Vref and Vout , respectively.
With this circuit, Vout is settled to the following value, since
the rising edges of ref and out are forced to be aligned in
phase by the following PPD:
I M3 C1
Vref .
(1)
Vout =
I M2 C2
As given above, the ratio between I M2 and I M3 determines
the output voltage, assuming the use of the same capacitors.
This design offers a good solution to trimming Vout with fine
resolution, as it is enabled in the current-mode DACs.
B. Phase and Polarity Detector
Fig. 4 shows a three-state phase-frequency detector (PFD)
with polarity detector. The PFD is composed of two D flipflops with asynchronous reset, AND, and OR gates. If ref goes

to HIGH, while all the D flip-flops keep LOW, Q of DFF0 is

raised to HIGH. If this event is followed by a rising transition
on out , Q of DFF1 goes to HIGH as well, then the AND gate
resets both the flip-flops (DFF0 and DFF1) to LOW after the
buffer delay of d , an intentionally made delay, to remove the
dead-zone problem in the cyclic TDC. The polarity detector
is implemented with a single D flip-flop (DFF2). This circuit
discerns the first-coming clock between ref and out , which
represents that the corresponding voltage is lower than the
other. As an example, if ref is faster than out , i.e., Vref is
lower than Vout , the output of up/down is set to LOW, so that
the counter is decremented.
C. Cyclic TDC and TRBM Detector
Fig. 5 shows a circuit detail of the cyclic TDC and the
TRBM detector.
The TRBM detector triggers the output (boost) HIGH, when
the time difference between ref and out is increased beyond
D or more, which means that Vout deviates from a preset
boundary, because of the overshoot/undershoot during the
transient response. If we assume that C1 , C2 have a common
value of CC , and I M2 , I M3 have a common value of IC ,
respectively, D can be converted back to voltage difference,
as V D
V D =

IC
D.
CC

(2)

Therefore, Vref V D is the upper and lower boundary

voltage to trigger TRBM. The cyclic TDC consists of the
eight-stage delay cells (D 0D7, among which one cell has
the delay skew by Tres , between its rising and falling delays.
Therefore, the pulsewidth of err is shrunk by Tres per rotation.
In normal mode, the cyclic TDC produces a single pulse per
turn of the delay loop, and thus the number of clock pulses
represents the cycles for which err are rotated through the
delay chain, until the pulse on 7 disappears [11].
Sharing the delay cells for resolution of each bit in this way
results in good linearity, as well as the basic advantage of the
power and area efficient design, since the mismatch between
delay cells is repeated equally for each bit. Also, it provides
a wide dynamic range, because the dynamic range is limited

1284

Fig. 6.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Small-signal model for the proposed D-LDO.

by the number of bits in the UP/DN counter, not by the total

delay range of TDC.
Once TRBM is entered, the number of pulses in cnt is
multiplied four times, by tapping the nonoverlapped clocks
(D1, D3, D5, and D7) from the intermediate nodes of the
delay chain. This leads to effectively increasing the loop gain
by four times, and thus accelerating the loop operation.
With this scheme, we can reduce the overshoot/undershoot
on Vout , without any detrimental effect on the ripple after the
loop settles down. It should be noted that this performance
is achieved by just an UP/DN counter, not by more complex
adders and multipliers.

Fig. 7. Bode plots for two cases according to p1 and z 1 . (a) H0 < p1 , z 1 .
(b) H0 > p1 , z 1 .

D. Small-Signal Analysis
Fig. 6 shows the small-signal model for the proposed
D-LDO, where Cc and Ic are the common values in VTC
as assumed above, and Tres represents the resolution of the
TDC. Using this model, we can get the steady-state open-loop
transfer function O(s) in s-domain, as follows:
O(s) = H0

es/ f ref 1 + s/z 1

s
1 + s/ p1

Fig. 8.

Cc f ck gm
K bst
Ic Tres gds

(4)

p1 = 1/C0 (RESR + 1/gds)

(5)

z 1 = 1/(RESR Co )

(6)

H0 =

Chip microphotograph.

(3)

where RESR represents ESR of Co , gm is the transconductance of an LSB switch transistor, and gds is the sum of
the output conductance of the switch transistors at steady
state. The term of K bst represents the incremental gain at
the boost mode, which is set to 4 at the boost mode and
returns to 1 at the normal mode. A conventional cyclic TDC
produces its value in every reference clock cycle. For this
purpose, the counter should be reset to zero, before it enters
next cycle.
However, our design reuses the counter, to implement an
accumulator as a low-pass filter without reset operation, and
thus it results in an integrator in the transfer function. Also,
the conventional pole made in the gate of pMOS is moved to
a frequency that is high enough to be ignored, because of the
low output resistance of the digital inverters driving it.
With this understanding, Fig. 7 shows the effect of the
accumulator that adds one more pole ( p0 ) at dc on the loop
gain. Fig. 7(a) shows the loop gain for a case that C0 is small

enough to be excluded in the stability analysis. In this case,

the unity gain frequency (UGF) is determined as H0 , which
corresponds to the dc gain of the transfer function without the
effect of the accumulator. The loop stability can be always
secured if UGF is placed apart below p1 , because O(s) can be
approximated as a first-order system in that region


Cc f ck gm
(7)
K bst .
UGF = H0 =
Ic Tres gds
This equation indicates that for higher UGF, we need to use
a higher frequency clock, or to improve the time resolution of
the path of VTC to TDC, which is made possible by reducing
Tres , or increasing the rate by Cc /Ic .
Fig. 7(b) shows the plot for another case that C0 is much
larger and ESR cannot be ignored, while H0 is maintained
constant. In this case, UGF is reduced from H0 by p1/z 1 and
its stability need to be compensated by ESR.
IV. E XPERIMENTAL R ESULTS
The proposed D-LDO regulator, targeting on 80 mA at
0.5-V output for the maximum load current, has been implemented on an 110-nm CMOS process. Fig. 8 shows a die

OH AND HWANG: 110-nm CMOS 0.7-V INPUT TRANSIENT-ENHANCED D-LDO REGULATOR

Fig. 9. Measurement of Vout and I Q versus Vin , at various sets of clock

frequency.

Fig. 10.

Fig. 11.

1285

Measured load regulation of Vout .

Vout versus the current ratio between I M2 and I M3 .

photograph of the designed chip, which occupies the active

area of 0.04 mm2 .
The proposed D-LDO offers loop stability over a wide range
of clock frequency, once pole, and zero exist far enough outside the frequency. This property is useful for the functionality
of scalable quiescent current, which is enabled by scaling f ck ,
depending on the requirement of load current.
Fig. 9 shows Vout and I Q in a single plot for 0.5-V target
voltage, while VIN and f ck are swept from 1 V down to 0.6 V,
and from 1 MHz down to 14 kHz, respectively. As a result,
our D-LDO consumes the quiescent current of 15 A, when
f ck is normally at 1 MHz with VIN of 0.7 V. Also, a sleep
mode with fck scaled down to 50 kHz can be assigned so that
it can drive the always-on circuits, such as power on reset,
brownout detector, memory data retention, and sleep timer,
just with the low quiescent current of 1.5 A. When f ck is
scaled down more to 14 kHz, the quiescent current tends to
be increased again. Under 14 kHz, it fails to provide the target
voltage, because it loses stability.
Fig. 10 shows the plot of Vout versus the current ratio of
I M2 /I M3 inside the VTC, which indicates that Vout can be
adjusted linearly enough with the current ratio, replacing the
resistors.
Fig. 11 shows the performance of the load regulation
measured when the load current alternates between 0 and
80 mA, and f ck is set to 1 MHz. This plot indicates that the

Fig. 12. Measured load transient response for a different mode. (a) 80-mA
step-top load. (b) 80-mA step-bottom load.

load regulation is 24 mV at 80-mA load current, including the

resistance of the package and the PCB line, and the voltage
ripple is <4 mV, when a 1-nF load capacitor is used.
Fig. 12 compares transient responses with and without TRBM, to clarify the effect of the TRBM on undershoot/overshoot at a transient response. Under the condition
that the load current rises to 80 mA, as shown in Fig. 12(a),
it is observed that the settling time and the peak of the
undershoot are reduced by 60% and 72%, respectively. Also,
the settling time and the peak of overshoot are commonly
reduced by 60%, for the load current falling to zero, as shown
in Fig. 12(b).
Table I compares the basic performance metrics between
our design, and other recent works. For fair comparison,

1286

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE I
P ERFORMANCE C OMPARISON OF LDO S

we employed the widely used FOM, as follows [12]:

IQ
COUT VOUT

(8)
IMAX
IMAX
where COUT is the output capacitor, VOUT is the maximum
transient output-voltage variation, IOUT is the maximum load
current, and I Q is the quiescent current. As listed in Table I,
the digital regulator achieves the smallest FOM.

[4] Y. Okuma et al., 0.5-V input digital LDO with 98.7% current efficiency
and 2.7-A quiescent current in 65 nm CMOS, in Proc. IEEE Custom
Integr. Circuits Conf. (CICC), Sep. 2010, pp. 14.
[5] M. Lders et al., A fully-integrated system power aware LDO for
energy harvesting applications, in Proc. IEEE Symp. VLSI Circuits,
2011, pp. 244245.
[6] A. Raychowdhury, D. Somasekhar, J. Tschanz, and V. De, A fullydigital phase-locked low dropout regulator in 32 nm CMOS, in Proc.
IEEE Symp. VLSI Circuits, Jun. 2012, pp. 148149.
[7] Y.-H. Lee et al., A low quiescent current asynchronous digital-LDO
with PLL-modulated fast-DVS power management in 40 nm SoC for
MIPS performance improvement, IEEE J. Solid-State Circuits, vol. 48,
no. 4, pp. 10181033, Apr. 2013.
[8] Y.-C. Chu and L.-R. Chang-Chien, Digitally controlled low-dropout
regulator with fast-transient and autotuning algorithms, IEEE Trans.
Power Electron., vol. 28, no. 9, pp. 43084317, Sep. 2013.
[9] K. Otsuga et al., An on-chip 250 mA 40 nm CMOS digital LDO
using dynamic sampling clock frequency scaling with offset-free TDCbased voltage sensor, in Proc. IEEE Int. SOC Conf. (SOCC), Sep. 2012,
pp. 1114.
[10] W.-C. Hsieh and W. Hwang, All digital linear voltage regulator for
super-to near-threshold operation, IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 20, no. 6, pp. 9891001, Jun. 2012.
[11] P. Chen, C.-C. Chen, W.-F. Lu, and C.-C. Tsai, A time-to-digitalconverter-based CMOS smart temperature sensor, IEEE J. Solid-State
Circuits, vol. 40, no. 8, pp. 16421648, Aug. 2005.
[12] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and
S. Borkar, Area-efficient linear regulator with ultra-fast load regulation,
IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933940, Apr. 2005.

FOM =

V. C ONCLUSION
The proposed transient-boost technique solves the tradeoff
issue between transient response and ripple at steady state,
one of the structural problems in D-LDO regulators, and
thus it enables a reduction of the transient response time by
60%, without affecting the ripple. Also, the designed regulator
achieved the maximum current efficiency of 99.98%, and it
produced a wide range of output voltage from 0.50.9 V, due
to the low-voltage operation at 0.7 V, which is caused by the
use of logic gates.
R EFERENCES
[1] M. Hammes, C. Kranz, D. Seippel, J. Kissing, and A. Leyk, Evolution
on SoC integration: GSM baseband-radio in 0.13 m CMOS extended
by fully integrated power management unit, IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 236245, Jan. 2008.
[2] J.-W. Lai et al., A world-band triple-mode 802.11a/b/g SOC in 130-nm
CMOS, IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 29112921,
Nov. 2009.
[3] E. Alon and M. Horowitz, Integrated regulation for energy-efficient
digital circuits, IEEE J. Solid-State Circuits, vol. 43, no. 8,
pp. 17951805, Aug. 2008.

Tak-Jun Oh received the B.S. and M.S. degrees

from Kangwon National University, Chuncheon,
Korea, in 2011 and 2013, respectively.
He has been a Research Staff Engineer with
MagnaChip Company, Ltd., Seoul, Korea, since
2013. His current research interests include highprecision CMOS temperature sensors and dcdc
converters.

In-Chul Hwang (S93M95) received the B.S.,

M.S., and Ph.D. degrees from Korea University,
Seoul, Korea, in 1993, 1995, and 2000, respectively.
He was a Research Staff with the Coordinated
Science Laboratory, University of Illinois at UrbanaChampaign, Champaign, IL, USA, from 2000 to
2001. From 2001 to 2007, he was a Senior Engineer
with Samsung Electronics, Kiheung, Korea, where
he was involved with CMOS RFIC development
targeting for GSM/EDGE/WCDMA RF transceivers.
In 2007, he joined the faculty of the Department
of Electrical and Electronics Engineering, Kangwon National University,
Chuncheon, Korea, where he is currently an Associate Professor. His current
research interests include CMOS RFIC, LED driver ICs, and power- and
frequency-management ICs.