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This introduction is valid for OrCad PSpice ver 9.2 lite edition. The lite edition or student edition of
the software is limited to designs with max 64 nodes and max 10 transistors. After the program is
installed start the schematic capture program Capture.
Select File / New Project
be sure to choose Analog or Mixed A/D. Browse to the location where
you want to save your project and give the project a name
In the schematic window choose Place / Part. The first time you have to add PSpice libraries. Select
Add / Library and select all libraries in the PSpice library directory.
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MbreakN
MbreakP
Library BREAKOUT
Place / Ground
Library Source, you have to add this library to find the ground
symbol with name 0, in SPICE there has to be one node with
the name 0
Place / Part
VDC
IDC
VSIN
Library Source
Place / Wire
add name to nets in your design so it is easier to find signals or connecting nets
without actually drawing wires (VDD and VSS)
After drawing design and setting voltage and current sources the drawing would look like this.
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Next we need a SPICE model for the transistor and get the model connected to the actual transistor.
MOS_models should be in a plain text file and look something like this
* PSpice Model Editor - Version 9.2
*$
.model MOS_p PMOS Level=1
+ VTO=-0.8 KP=6.474E-5 LAMBDA=
+ GAMMA=2.675E-1 PHI=0.6 CGSO=0.35E-9 CGDO=0.35E-9
+ CJ=0.4E-3 CJSW=2.4E-9 MJ=0.4 MJSW=0.3 PB=0.7
+ TOX=80E-10 NSUB=4E16 NSS=1E11 XJ=0.18E-6 LD=0.09E-6
*$
.model MOS_n NMOS Level=1
+ VTO=0.6 KP=1.942E-4 LAMBDA=
+ GAMMA=9.457E-2 PHI=0.6 CGSO=0.35E-9 CGDO=0.35E-9
+ CJ=0.2E-3 CJSW=1.2E-9 MJ=0.5 MJSW=0.4 PB=0.7
+ TOX=80E-10 NSUB=5E15 NSS=1E11 XJ=0.15E-6 LD=0.09E-6
*$
Copy the model file (in this case MOS_models.lib) to the directory where your design is located (or
any other directory you prefer).
Create a simulation profile PSpice / New Simulation Profile, give it a name free of choice (in this
case I have chosen Transient). In Libraries, browse to the model file and add it to design.
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The transistors area, W and L, is not specified in the model. This could be different for each transistor
so we will specify it in schematics. Select the transistor, right click and select Edit Properties... If you
right click in the property editor and choose Pivot it will look like this
Select attribute L and click on Display... and change the Display Properties to Name and Value. Do
the same with W. L and W should now be visible in your drawing.
Now the values of W and L could be changed. It could be convenient to use a constant for the length
because several transistors usually have the same length. This could be done with PARAM from
library Special. After placing PARAM edit its properties, select New line, give it the name L and
value 1u. Dont forget to make name and value visible. For the transistors, give L the value {L}. Give
also width W a value for the transistors.
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2.0V
0V
-2.0V
0s
V(OUT)
2ms
4ms
6ms
8ms
10ms
Time
It seems to be very high gain in this amplifier. Try to always be critical when you study simulation
results. Is this what should be expected? In this case there is no LAMBDA specified in the model and
the output conductance is zero for all transistors (infinite output resistance). If you go back to Capture
and change the simulation profile and in Out File Options... specify to Include detailed bias point
information... and rerun the simulation
If you from Capture open output file with PSpice / View Out File you could find bias point
information and all small signal parameters for all transistors.
**** MOSFETS
NAME
MODEL
ID
VGS
VDS
VBS
VTH
VDSAT
Lin0/Sat1
if
ir
TAU
GM
GDS
GMB
CBD
CBS
CGSOV
CGDOV
CGBOV
CGS
CGD
CGB
M_M1
MOS_n
1.00E-05
6.41E-01
3.07E+00
0.00E+00
6.00E-01
4.11E-02
-1.00E+00
-1.00E+00
-1.00E+00
-1.00E+00
4.87E-04
0.00E+00
2.97E-05
0.00E+00
0.00E+00
1.75E-14
1.75E-14
0.00E+00
1.18E-13
0.00E+00
0.00E+00
M_M2
MOS_n
1.00E-05
6.41E-01
3.07E+00
0.00E+00
6.00E-01
4.11E-02
-1.00E+00
-1.00E+00
-1.00E+00
-1.00E+00
4.87E-04
0.00E+00
2.97E-05
0.00E+00
0.00E+00
1.75E-14
1.75E-14
0.00E+00
1.18E-13
0.00E+00
0.00E+00
M_M3
MOS_p
-1.00E-05
-8.71E-01
-8.71E-01
0.00E+00
-8.00E-01
-7.12E-02
-1.00E+00
-1.00E+00
-1.00E+00
-1.00E+00
2.81E-04
0.00E+00
4.85E-05
0.00E+00
0.00E+00
1.75E-14
1.75E-14
0.00E+00
1.18E-13
0.00E+00
0.00E+00
M_M4
MOS_p
-1.00E-05
-8.71E-01
-8.71E-01
0.00E+00
-8.00E-01
-7.12E-02
-1.00E+00
-1.00E+00
-1.00E+00
-1.00E+00
2.81E-04
0.00E+00
4.85E-05
0.00E+00
0.00E+00
1.75E-14
1.75E-14
0.00E+00
1.18E-13
0.00E+00
0.00E+00
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Go back to Capture, select one of the transistors, right click and select Edit PSpice model. Change
LAMBDA to 0.13 for both transistors. (Note that Lambda depends on channel length and voltage bias
so this value might not be valid in this case, this is just to illustrate how to change the model). The
change in the model will be valid for all transistors using the same model.
2.8V
2.4V
2.0V
0s
V(OUT)
2ms
4ms
6ms
8ms
10ms
Time
The amplitude of the output voltage could be read to 271 mV, so the gain is 271 (1 mV input voltage
amplitude). From output file
GDS
9.29E-07
9.29E-07
1.17E-06
1.17E-06
In transient analysis a large signal model is used for the transistors. If we do a small signal analysis,
AC sweep analysis.
Before you start the simulation you have to specify input voltage source for small signal analysis. This
could be done by changing input voltage source VSIN to VAC, but in this case I recommend to add
AC voltage to the source VSIN that you already have in design, so you could use same source symbol
to specify both transient analysis and AC analysis. Select input source, edit properties and make
attribute AC visible with name and value. Give it the value 1mV.
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274
272
270
10Hz
V(OUT)/V(IN)
100Hz
1.0KHz
10KHz
100KHz
1.0MHz
Frequency
(6.2643M,45.785)
45
40
10Hz
100Hz
DB(V(OUT)/V(IN))
1.0KHz
10KHz
100KHz
1.0MHz
10MHz
Frequency
If we simulate higher in frequency and plot gain in dB, a -3dB-cutoff-frequency of 6.3 MHz could be
estimated with the help of cursors in display. Voltage gain in dB is 48.75 dB.
Some hints:
SPICE do not distinguish between m and M, use MEG for meg, M means milli.
Values and prefix should be typed without spaces. For example: 10u
not 10 u
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