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It contains question bank of EC6403-electronic circuits I

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YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Syllabus

Sub.Code

Sub.Name

Staff Name

: EC6304

: ELECTRONIC CIRCUITS I

: Mrs.A.SUJITHA

Batch : 2013-2017

Academic Year: 2015-2016 (Odd Sem)

LTPC

3104

UNIT I

9

Design and construct amplifiers

Construct amplifiers with active loads

Study high frequency response of all amplifiers

compensation,Thermal stability, Design of biasing for JFET, Design of biasing for MOSFET

UNIT II

9

BJT AMPLIFIERS

UNIT III

9

UNIT IV

9

UNIT V

9

IC MOSFET AMPLIFIERS

Common

collector and common base amplifiers Differential amplifiers- CMRR- Darlington

Amplifier,Bootstrap technique - Cascaded stages - Cascode Amplifier

Small signal analysis of JFT amplifiers- Small signal Analysis of MOSFET and JFET,

Common source amplifier, Voltage swing limitations, Small signal analysis of MOSFET and

JFET Source follower and Common Gate amplifiers, - BiMOS Cascode amplifier

Low frequency and Miller effect, High frequency analysis of CE and MOSFET CS

amplifier, Short

circuit current gain, cut off frequency f and f unity gain and Determination of

bandwidth of single

stage and multistage amplifiers

sources- PMOS

and NMOS current sources. Amplifier with active loads - enhancement load, Depletion load

and

PMOS and NMOS current sources load- CMOS common source and source follower- CMOS

differential amplifier- CMRR.

TOTAL (L : 45 + T : 15) :

60 PERIODS

A.SUJITHA,AP/ECE

KSKCET

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

TEXT BOOK:

1. Donald .A. Neamen, Electronic Circuit Analysis and Design 2 ndEdition,Tata Mc

GrawHill, 2009.

REFERENCES:

1.

Adel .S. Sedra, Kenneth C. Smith, Micro Electronic Circuits, 6thEdition, Oxford

University

Press, 2010.41

2. David A., Bell Electronic Devices and Circuits, Oxford Higher Education Press,

5thEditon, 2010

3. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata Mc Graw Hill,

2007.

4. Paul Gray, Hurst, Lewis, Meyer Analysis and Design of Analog Integrated

Circuits,

4thEdition ,John Willey & Sons 2005

5. Millman.J. and Halkias C.C, Integrated Electronics, Mc Graw Hill, 2001.

6. D.Schilling and C.Belove, Electronic Circuits, 3rdEdition, Mc Graw Hill, 1989

UNITI

BIASING OF DISCRETE BJT AND MOSFET

PART A

1. Define - Stability Factor. [May/June 2012], [Nov/Dec 2009], [Apr/May 2010], [May/June 2012]

2. Compare bias stabilization and compensation techniques.

[Nov/Dec 2011]

[Nov/Dec 2007]

[May/June 2012]

[Nov/Dec 2011]

6. Draw the single stage self biased circuit using pnp transistor.

[Apr/May 2011]

[ Nov/Dec 2012]

9.

[Apr/May 2011]

[May/June 2012]

11. Calculate the value of feedback resistor (Rs) required to self bias an N-channel JFET with

IDSS=40mA, VP = -10V and VGSQ = -5V.

[ Apr/May 2010]

12. What is DC load line? How is Q point plotted on the DC load line?

13. What

is

the

function

of

[Nov/Dec 2012]

the

point?

[nov/dec 2013]

14. What

[nov/dec 2013]

A.SUJITHA,AP/ECE

KSKCET

is

thermal

stability?

YEAR /SEM:II/III

15. Define

EC6304-ELECTRONIC CIRCUITS I

the

term

biasing.

[May-2013]

16. How can collector current be stabilized with respect to Ico variations?

[Nov-2010]

17. Derive stability factor for fixed bias circuit.

[Nov- 2010].

18. What are the operating regions of N channel MOSFET and how do you identify the operating

region?

[Nov- 2014]

19. Find the collector and base current of circuit given in fig hfe=100,V BE=0.7V

[nov-14]

20. List out the importance of selecting the proper operating point.

[may-15]

[may-15]

PART B

1. Explain fixed biasing in BJT and FET. Explain the procedure for locating operating point on the

characteristic curves and derive an expression for the stability factor.

2. Draw a voltage divider bias BJT network. Derive expressions for

ICQ

and

VCEQ

method of drawing the dc load line on the output characteristics of transistor derive an

expression for the stability factor.

A.SUJITHA,AP/ECE

KSKCET

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

3. A silicon transistor with = 49 is used in self bias arrangement with VCC = 5V, RE = 1Kohms and

IE = 1mA. Find the values of R1 and R2 such that the stability factor does not exceed 5. (10)

[ Nov/Dec 2012]

4. In an N-channel JFET, biased by potential divider method, the operating point has to be at I DSS =

12mA. If VDD = 12V, R1 = 20K and R2 = 10K , RD =1.2K and VP= -4V. Find the values of

ID, VGS, VG, VDS and VS.

V c c = 1 5 V

2 0 0

o h m

k o h m

1 0 0

=5

o h m

0

6. For the following circuit calculate VCE and IC, where = 100 for the silicon transistor.

.

[ May/June 2012]

8. Explain the circuit that uses a diode to compensate the changes in VBE and ICO. (12) [May 2010]

9. Explain the operation of thermistor compensation.

10. Explain the various techniques of stabilization of Q-point in a transistor.

11. Explain the factors on which an amplifier needs to be stabilized.

(16) [May/June 2012]

(6) [ Nov/Dec 2012]

12. With the help of neat diagram, explain the methods used in biasing the FET and MOSFET.

(16)

[Nov/Dec 2011]

13. (i) Define - Stability Factor

(2)

(ii) The pnp transistor in the following circuit has = 50. Find the values of RC to obtain

Vc = 5V. What happens if the transistor is replaced with another transistor = 100?

A.SUJITHA,AP/ECE

KSKCET

(14)

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

[ Apr/May 2011]

14. (i) Draw the circuit of a voltage divider bias circuit. Explain its operation and

discuss

how it stabilizes against VBE changes.

(8)

(ii) Derive the stability factor of the voltage divider bias circuit.Compare

the stability factor

of fixed bias and voltage divider bias circuits with hFE =100, Re = 1K,

R1 = 33K and R2 = 12 K.

(8)

[nov/dec 2013]

15. (i) Explain the circuit of gate bias for providing stabilization of JFET.

(8)

(ii) Sketch the bias circuit for enhancement MOSFETs and explain its

operation. (8)[Nov-2013]

16. For the Circuit in the Figure-1 , draw the AC load line and determine the

maximum output swing without distortion.

(8)[may/june-13]

(8)[may/june 2013]

18. Locate the operating point for the below figure ,Vcc=15v,hf=200

(8) [nov/dec 2010]

A.SUJITHA,AP/ECE

KSKCET

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

19. Design a self bias circuit for JFET to be biased in pinch off region . Given Vdd=20,Vgb=4v,Idss=8mA.Draw the designed circuit.

(8) (Nov-2010]

20. i)Design Emitter bias for BJT with Ic=2mA,Vcc=18V,VCE=10V and =150.

ii)Derive the stability factor of self bias circuit of BJT.

(8)

(8) [Nov-2014]

21. Design voltage divider bias circuit for NMOS, such that

IDQ=400A,VDD=14V,VDS=2.3V,kn=nCox(W/L)=1mA/V2,Vt=1V. Assume a current of 1A

through R1 and R2 and Vs=1.2V.

(16)[Nov-2014]

22. The parameters for each transistor in the circuit given are hfe=100 and VBE(on)=0.7V. Determine

the Q point values of base, collector and emitter currents in Q1 and Q2.

(8)

[may-15]

23. Determine the change in collector current produced in each bias referred in figure, when the

circuit temperature raised from 25C to 105C and ICBO=15nA @25C.

A.SUJITHA,AP/ECE

KSKCET

(8)

[may-15]

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

24. Determine the quiescent current and voltage values in a p channel JFET circuit

(6)

[may-15]

25. The circuit given let hfe=100.(1)Find Vth and Rth for the base circuit (2)Determine I CQ andVCEQ

(3)Draw the DC load line.

(10)[may-15]

UNITII

BJT AMPLIFIERS

PART A

1. Define h-parameters

[May/June 2007]

2. Write the voltage gain equation for CE configuration including source resistance. [M/June 2012]

3. What is AC load line? How is Q point plotted on the AC load line?

A.SUJITHA,AP/ECE

KSKCET

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

[ Nov/Dec 2011]

[ Apr/May 2008]

6. Two identical amplifiers having 10 dB gain each are cascaded. Calculate the output, if the input

is of 1mV (p-p).

[Apr/May 2011]

[ Apr/May 2010]

9. Determine the output voltage of a differential amplifier for the input voltages of 300 V and

240V. The differential gain of the amplifier is 5000 and the value of CMRR is 100.

[N/D-12]

10. If CMRR of an amplifier is 100 dB and differential gain is 1000, calculate the common mode

gain.

[Apr/May 2011]

[May/June 2012]

[ Nov/Dec 2012]

15. What

is

the

advantage

of

Darlington

amplifier?

[nov/dec 2013]

16. Mention

two

important

characteristics

of

CC

circuit.

[nov/dec 2013]

17. Draw

the

circuit

diagram

of

Darlington

type

amplifier.

[may/june2013]

18. Give

the

reason

for

the

improvement

of

CMMR

in

the

amplifier.

[may/june2013]

19. Draw

darlington

amplifier

with

bootstrap

arrangement.

[nov/dec 2010]

20. Why CB amplifier is preferred for high frequency signal when compared to CE

amplifier?

[nov/dec 2010]

21. Draw

the

AC

equivalent

circuit

for

given

figure.

[Nov-2014]

22. Find CMRR of differential amplifier with differential gain of 300 and common

mode gain of 0.2. [Nov-2014]

23. Define CMRR of BJT differential amplifier.How to improve it?

[nov-15]

24. A small signal source Vi(t)=20cos20t + 30 sin10 6t is applied to a transistor

amplifier as shown in fig. The transistor has hfe=150,ro=infinite and r=3k.

Determine Vo(t)

[nov-15]

A.SUJITHA,AP/ECE

KSKCET

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

PART B

1. Derive the expression for

a) Current gain,

b) Voltage gain,

c) Input impedance and

d) Output admittance.

of a small signal transistor amplifier in terms of h parameters.

2. Explain the voltage swing limitations for a common emitter amplifier configuration.

3. A CC amplifier is fed with the voltage source Vs of internal resistance R s = 800. The load

resistance RL = 1600. The CE hybrid parameters are hie = 1000; hre = 2.2 x 10-4;

hfe = 55;

hoe = 23 A/V. Compute voltage gain, current gain, input resistance, output resistance using

approximate analysis.

4. Draw the small signal hybrid model of CE amplifier and derive the expression for its A I, AV, RI,

RO.

(8) [ Nov/Dec 2011],[May/June 2012], [Nov/Dec 2009] [ Apr/May 2010]

6. Consider a single stage CE amplifier with RS = 1K and RL = 1.2K. Calculate Ai, Ri, AV,

power gain and Ro if hie = 1.1K, hre = 2.5x10-4, hfe = 50 and hoe = 25 A/V.

7. For the following circuit, find the voltage gain when the capacitance is connected across R E and

when capacitance is not connected across RE.

RB

RC

C

.

RL

RE

.

A.SUJITHA,AP/ECE

KSKCET

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

8. For the CC transistor amplifier circuit, find the expressions for input impedance and voltage

gain. Assume suitable model for the transistor.

9.

(i) Describe the method to increase the input resistance using Darlington connection.

(8)

(4)

10. Explain the operation of a Darlington emitter follower and also derive an expression for its

performance measures.

11. Explain the boot strapped Darlington emitter follower with circuit diagram. (8) [ May/June 2012]

12. Explain the operation of emitter coupled differential amplifier.

14. Draw the circuit of a CE amplifier with coupling and bypass capacitors. With

the help

of its equivalent circuit, obtain the equation of the voltage gain, input and

output impedance. (16)[nov/dec2013]

15. Draw the circuit of a emitter coupled BJT differential amplifier and explain the

operation of the circuit. Explain how the differential amplifier with a

constant current stage

improves the CMRR.

(16)[nov/dec2013]

16. Compute the parameters of the circuit shown in Figure 2 with

= 100.

(10)[MAY/JUNE-13]

17. Draw a differential amplifier and its AC equivalent circuit. Derive for Ac and

Ad.

18. Derive

CMRR

(16)[Nov-14]

A.SUJITHA,AP/ECE

KSKCET

of

differential

amplifier

with

its

equivalent

circuit.

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

19. Explain the operation of cascade amplifier and derive gain, input and output

impedance. (16)[Nov-14]

20. Consider the circuit shown with parameters are hfe=120 and V A=infinite.

(1)Determine the current gain, voltage gain, input impedance and output

impedance. (2)Find the maximum undistorted output voltage swing.

(12)[may-15]

21. Draw the circuit diagram of bootstrapped emitter follower with its equivalent

circuit, derive for its input and output impedance.

(6)[may-15]

UNITIII

JFET AND MOSFET AMPLIFIERS

PART A

1. What is an amplifier?

2. Write the expression for basic current equation in MOSFET.

3. Why FET is called as a voltage controlled device?

4. Draw the equivalent circuit of MOSFET.

5. State atleast two reasons why a hybrid parameter model is used in small signal analysis.

6. Sketch the simple common source amplifier circuit of MOSFET.

7. What are the basic circuit configurations used in MOSFET?

8. Sketch the simple common gate amplifier circuit of MOSFET.

9. Compare the characteristics of small signal and large signal amplifiers.

10. Compare the AC circuit characteristics of the CS, CG and CD.

11. State the general advantages of using JFET rather than BJT.

12. Draw the small signal equivalent circuit of JFET.

13. How does the body effect change the small signal equivalent circuit of MOSFET?

14. Write the applications of MOSFET.

15. Write the expression of small signal voltage gain and output resistance of the common gate

circuit.

16. What is the difference between MOSFET and PN junction FET?

A.SUJITHA,AP/ECE

KSKCET

YEAR /SEM:II/III

17. Define amplifier rise time.

EC6304-ELECTRONIC CIRCUITS I

[nov/dec 2013]

[nov/dec 2013]

19. Draw small signal model of JFET.

[Nov-14]

20. What are the features of BiMOS cascade amplifier?

[Nov-14]

[may-15]

PART-B

1. Draw the small signal hybrid model of common drain MOSFET amplifier and derive the

expression for Ai,Av,Ri,Rv.

2. Briefly explain about the small signal analysis of CS amplifier MOSFET?

3. With the neat sketch explain the principle of operation of cascode amplifier and also derive an

expression for its performance measures?

4. Write short notes on voltage swing limitations.

5. Briefly explain about the small signal analysis of JFET?

6. Derive gain, input and output impedance of common source JFET amplifier with neat

circuit diagram and equivalent circuit.

(16)[Nov-14]

7. Derive gain, input and output impedance of MOSFET source follower with neat circuit

diagram and equivalent circuit.

(16)[Nov-14]

8. Draw a discrete common gate JFET amplifier and derive voltage gain, input impedance and output

impedance with small signal equivalent circuit.

9. Determine the current gain of JFET source follower amplifier.

(6)[may-15]

(4) [may-15]

UNITIV

FREQUENCY ANALYSIS OF BJT AND MOSFET AMPLIFIERS

PART A

1. Why are h parameters not used at high frequencies?

[May/June 2012]

2. Write the expressions for gain bandwidth product for voltage and current.

[ Apr/May 2010]

[May/June 2012]

A.SUJITHA,AP/ECE

KSKCET

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

[Nov/Dec 2011]

f = 200KHz, calculate fT and hfe.

[ Nov/Dec 2011]

8. What are the effects of emitter bypass capacitor on high frequency response?

9. What is meant by gain-bandwidth product?

[Nov/Dec 2012]

[ Apr/May 2011]

[ May/June 2012]

12. Two amplifiers having gain 20 dB and 40 dB are cascaded. Find the overall gain in dB.

13. Write the equation of overall upper and lower cut off frequencies of multistage amplifiers.

14. What is the bandwidth that can be obtained using BJT, if the rise time of a BJT is 40 ns?

.

16. What is the effect of Millers capacitance on the frequency response of an amplifier?

[Nov-14]

17. Relate gain and bandwidth of single and multi stage amplifier.

[Nov-14]

18. Find the unity gain bandwidth of MOSFET whose gm=6mA/V, Cgs=8pF, Cgd=4pF

and Cds=1pF.[m-15]

PART B

1. Define alpha cutoff frequency.

2. Explain the significance of cut off frequencies and gain bandwidth product of amplifier.

(6)

3. Explain the low frequency response and the high frequency response of an amplifier. (16)[M-10]

4. Draw the high frequency hybrid model for a transistor in the CE configuration and explain the

significance of each component.

5. Explain in detail with neat diagram frequency response of BJT amplifier. Discuss the

significance of cut off frequencies and band width of the amplifier.

6. Using hybrid model of a CE amplifier derive the expression for its short circuit gain.

(16)

[ May/June 2012]

7. The following circuit has R = 100K, Rin = 420K, Cgs = Cgd = 1PF, gm = 4mA/V,

Rt = 3.33K. Find the mid band gain and upper 3 dB frequency, fH . (16) [ Apr/May 2011]

A.SUJITHA,AP/ECE

KSKCET

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

R

Vin

Cgs

Rin

RL

gmVgs

.

8. Explain the operation of high frequency common source MOSFET amplifier with neat diagram.

Derive the expression for

(a) voltage gain

(b) input admittance

(c) input impedance

(d) output admittance

9. Draw the high frequency equivalent circuit of MOSFET amplifier and derive all the parameters

related to its frequency response.

10. Explain the high frequency equivalent circuit of MOSFET and hence derive gain bandwidth

product for any one configuration.

12. Explain the frequency response of multistage amplifiers. Calculate the overall upper and lower

cut off frequencies.

13. How does Rise and Sag time related to cut-off frequencies? Justify.

14. i)Derive f,f anf f.

ii)For the circuit shown find cut off frequencies due to C1 and C2.

A.SUJITHA,AP/ECE

KSKCET

(8)

(8)[NOV-14]

YEAR /SEM:II/III

EC6304-ELECTRONIC CIRCUITS I

15. Explain the high frequency operation of common source amplifier with its equivalent circuit.

(16)[Nov-14]

16. Determine the voltage gain, input impedance, output impedance of CMOS source follower

amplifier.

(8)[may-15]

UNITV

IC MOSFET AMPLIFIERS

PART A

2. Describe the characteristics of CMOS CS amplifier.

3. How current sources are used to bias IC amplifiers.

4. What is IC biasing Current steering circuit using MOSFET?

5. What is the small signal behavior of an enhancement load?

6. Give the advantages of CMOS IC.

7. How does this enhancement load resemble a resistor?

8. What is the small signal behavior of an enhancement load?

9. Draw a circuit of current source using MOSFET.

[Nov-14]

10. Draw a CMOS amplifier with NMOS driver and PMOS as active load.

[Nov-14]

11. Compare NMOS amplifier with enhancement , depletion and resistive load.

[m-15]

12. List out the advantages of CMOS differential amplifier over MOS differential amplifier

[m-15]

PART B

1. Explain the working principle of a simple MOSFET differential amplifier with an active load.

2. Derive the expression of the differential-mode voltage gain, common mode voltage gain and

CMRR for a MOSFET differential amplifier.

3. Explain the working principle of a CMOS differential amplifier.

4. Explain the design of a PMOS and NMOS current sources to provide a specified bias current and

output resistance.

5. Explain in detail the MOSFET amplifiers with enhancement load and depletion load.

6. Draw a MOS current steering circuit with two sink and two source terminals. Write the

expression for the terminal currents in terms of reference current.

(16)[Nov-14]

7. Derive gain, input and output impedance of common source amplifier with NMOS

diode connected active load.

A.SUJITHA,AP/ECE

KSKCET

(16)[Nov-14]

YEAR /SEM:II/III

A.SUJITHA,AP/ECE

KSKCET

EC6304-ELECTRONIC CIRCUITS I