Mr. Jiteshwar Anand

Surendra Roll No. – RD380 REGD. ID - 10806601

DECLARATION: I declare this assignment is my individual work. I have not copied from student’s work or from any source except where due acknowledgment is made explicitly in the text, nor as any part been for me by another person.


Q1 The access time of cache memory is 100 ns and that of main memory is 1000 ns. If cache hit ratio is 0.9, determine the effective access time of the system.

We can calculate the effective access time of the system.of the following method such as (Hit ratio*cache mem.access time + miss ratio * (cache mem. access time + main mem. access time).

Access time of Cache Memory = 100 ns Access time of Main Memory = 1000 ns Cache Memory Hit Ratio = 0.9 Hits missed by the Cache Memory= 0.1

Effective Access time of the System is = 0.9 * 100 + 0.1 *1100 = 90 + 110 = 200 ns.

Q2. A digital computer has memory unit of 64K x 16 and cache memory of 1K words. If direct mapping policy is used, determine the number of bits in: (a) Main Memory address (b)Cache Memory address (c) Tag and Index fields ANSWER: Memory unit of 64K*16 capacity means 64 K = 26 * 2 10 = 216. i.e. 16 bit address and 16 bit data lines are needed.

(b)Cache Memory Address:

28 =256 blocks of four words each cache accommodate.

(C)Tag and Index fields:

Q3 Determine the number of page faults and number of page replacements for the reference string: 1, 7, 3, 3, 2, 1, 7, 1, 2, 1, 3, 4 using FIFO, LRU and Optimal algorithms. ANSWER: According to this string the page fault and page replacement will be-

FIFO algoritheme-

Page Faults: 8 Page replacements: 5


Page Faults: 8 Page replacements:5


Page Faults: 6 Page replacements:3


Q4 Show Memory connections to CPU with four 128X8 RAM and one 512X8 ROM chip


Q5 the content of Key register is 0001 1000. Determine which of the following words of CAM match the Argument 1100 1011: (a) 1100 1011 0011 0101 ANSWER: b) 0010 1011 c) 1101 0101 d)

Let the Argument Register as ‘A’ and Key Register as ‘K’.

Now, matching them with given four words to get the result.

A K Word (a) Word (b) Word (c) Word (d)

1100 1011 0001 1000 1100 1011 0010 1011 1101 0101 0011 0101 Match found Match found No match found No match found

So, only 2 Match has been found in the above comparisons.

Q6. Design the architecture of DMA mode of operation and illustrate how various components namely, CPU, RAM, DMA Controller and I/O Peripheral interface each other. ANSWER:

The CPU can wait to fetch instructions and data from memory without any damage occurring except loss of time. DMA usually transfers data from a device that cannot be stopped since information continues to flow so loss of data may occur. During DMA transfer , the CPU is idle and has no control of the memory buses. A DMA controller takes over the buses to maintain the transfer directly between the input output device .The DMA controller needs the usual circuits of an interface to communicate with the CPU and input – output device .