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Digital Electrical

Digital Electrical

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- EE46digital Logic Circuits
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You are on page 1of 102

Basics

B

i

Combinational Circuits

Sequential Circuits

Pu-Jen Cheng

Adapted from the slides prepared by S. Dandamudi for the book,

Fundamentals of Computer Organization and Design.

AND, OR, NOT,

NAND, NOR, XOR,

L i gates

Logic

t are b

built

ilt using

i ttransistors

i t

AND gate requires 3 transistors

Compaq Alpha consists of 9 million transistors

Now we can build chips with more than 100 million

transistors

Basic Concepts

Simple gates

Functionality can be

expressed by a truth table

AND

OR

NOT

each possible input

combination

Precedence

F=AB+AB

= (A (B)) + ((A) B)

NAND

NOR

XOR

NOR = OR + NOT

XOR implements

exclusive-OR function

NAND and NOR gates

require only 2 transistors

transistors!

Number of functions

N

22 functions

Some of them are useful

AND,

AND NAND,

NAND NOR,

NOR XOR,

XOR

Some are not useful:

Output is always 1

Output is always 0

Number of functions definition is useful in proving

completeness property

Complete sets

If we can implement any logical function using only

the type of gates in the set

{AND, OR, NOT}

Not a minimal complete set

{AND, NOT}

{OR, NOT}

{NAND}

{NOR}

Minimal complete set

NAND gate is called universal gate

NOR gate is called universal gate

Logic Chips

Integration levels

Introduced in late 1960s

1-10 gates (previous examples)

MSI (medium scale integration)

Introduced in late 1960s

10-100 gates

LSI (large scale integration)

Introduced in early 1970s

100-10,000 gates

VLSI (very large scale integration)

Introduced in late 1970s

More than 10,000 gates

Logic Functions

ways:

Truth table

Logical expressions

Graphical form

Example:

Majority function

Output is 1 whenever majority of inputs is 1

We use 3-input majority function

3-input majority function

A

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

0

1

0

1

1

1

F=AB+BC+AC

Logical Equivalence

circuit

Show that these two expressions are equivalent

Two ways:

For every combination of inputs, if both expressions

yield the same output, they are equivalent

Good for logical expressions with small number of

variables

You can also use algebraic manipulation

Need Boolean identities

Write down intermediate logical expressions along the path

A

0

0

1

1

B

0

1

0

1

F1 = A B

0

0

0

1

F3 = (A + B) (A + B) (A + B)

0

0

0

1

Boolean Algebra

method

equivalent

Start with one function and apply Boolean laws to

derive the other function

Needs intuition as to which laws should be applied

and when

Practice helps

functions to the same expression

Example: F1= A B and F3 are equivalent

A B = (A + B) (A + B) (A + B)

Problem specification

Truth table derivation

Derivation of logical expression

Simplification of logical expression

I l

Implementation

t ti

SOP form

product-of-sums (POS) form

Write

W

i an AND term ffor each

h iinput combination

bi i that

h

produces a 1 output

Write the variable if its value is 1; complement

otherwise

OR the AND terms to get the final expression

POS form

B

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

0

1

0

1

1

1

Four product terms

with a 1 output

F=ABC+ABC+

ABC+ABC

B

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

0

1

0

1

1

1

Four sum terms

with a 0 output

F = (A + B + C) (A + B + C)

(A + B + C) (A + B + C)

Algebraic manipulation

Use Boolean laws to simplify the expression

Difficult to use

Dont know if you have the simplified form

Graphical method

Easy to use

variables

Algebraic Manipulation

Added extra

ABC+ABC+ABC+ABC =

ABC+ABC+ABC+ABC+ABC+ABC

BC+AC+AB

Note the order

Simplification examples

First and last columns/rows are adjacent

Minimal expression depends on groupings

No redundant groupings

Example

Seven-segment display

Need to select the right LEDs to display a digit

Dont cares simplify the expression a lot

AB+CD=AB+CD

Using

U

g de

d Morgans

o ga

law

a

AB+CD=AB.CD

Can be generalized

Majority function

A B + B C + AC = A B . BC . AC

Idea: NAND Gates: Sum-of-Products, NOR Gates: Product-of-Sums

Majority function

Combinational circuits

abstraction

Help

H

l in

i reducing

d i design

d i complexity

l it

Reduce chip count

Multiplexers

Multiplexer

2n data inputs

n selection inputs

a single output

Selection input

determines the

input that should

be connected to

the output

Multiplexers (cont.)

4-data input MUX implementation

Multiplexers (cont.)

MUX implementations

Multiplexers (cont.)

Example chip: 8-to-1 MUX

Multiplexers (cont.)

Efficient implementation: Majority function

Demultiplexers (DeMUX)

Demultiplexer

a single input

n selection inputs

2n outputs

Decoders

Decoders (cont.)

Logic function implementation

Comparator

Comparator (cont.)

Comparator (cont.)

Serial construction of an 8-bit comparator

1-bit Comparator

x>y

CMP

x=y

x<y

x

x

y

x>y x=y x<y

8-bit comparator

xn>yn

xn=yn

x>y

CMP

xn<yn

x=y

x<y

Adders

Half-adder

Produces a sum and carry

Problem: Cannot use it to build larger inputs

F ll dd

Full-adder

Like half-adder, produces a sum and carry

Allows building N-bit adders

Simple technique

Adders (cont.)

Adders (cont.)

A 16-bit ripple-carry adder

Adders (cont.)

Carry-ins

Carry

ins are generated independently

C0 = A0 B0

C1 = A0 B0 A1 + A0 B0 B1 + A1 B1

...

Requires complex circuits

Usually, a combination carry lookahead and

ripple-carry techniques are used

PLAs

No need to simplify the logical expressions

Take N inputs and produce M outputs

Each input represents a logical variable

Each output represents a logical function output

Internally uses

An AND array

N inputs and their complements

An OR array

A blank PLA with 2 inputs and 2 outputs

Implementation examples

Simplified notation

Preliminary ALU design

2s complement

Required 1 is added via Cin

Final design

16-bit ALU

4-bit ALU

Have memory property

Combinational

C

bi i

l circuit

i i

Feedback circuit

Past input is encoded into a set of state variables

Uses feedback (to feed the state variables)

Simple feedback

Uses flip flops

Introduction (cont.)

Main components of a sequential circuit

Clock Signal

Synchronization point

Start of a cycle

End of a cycle

Intermediate point at which the clock signal changes

levels

Timing information

Clock period, ON, and OFF periods

Propagation delay

inputs

SR Latches

Level-sensitive (not edge-sensitive)

A NOR gate implementation of SR latch

SR Latches (cont.)

In clocked SR latch, outputs respond at specific instances

D Latches

D Latch

Edge-sensitive devices

Latches

Low level

High level

Flip-flops

Positive edge

Negative edge

74164 shift

Register chip

Require separate data in and out lines

JK Flip-Flops

JK flip-flop

(master-slave)

J

0

0

1

1

K

0

1

0

1

Qn+1

Qn

0

1

Qn

Two example chips

D latches

JK flip-flops

Shift Registers

Counters

Use the JK = 11 to toggle

Binary counters

Simple

p design

g

Ripple counter

Increased delay as in ripple-carry adders

Delay proportional to the number of bits

Synchronous counters

Additional cost/complexity

LSB

Q1 changes whenever Q0 = 1

Q2 changes whenever Q1Q0 = 11

Example Counters

A feedback circuit

We use JK flip-flops for the feedback circuit

Si l counter

Simple

t examples

l using

i JK flip-flops

fli fl

We know the output

Need to know the input combination that produces

this output

Use an excitation table

Next state output

JK inputs for each flip-flop

Bi

Binary

counter

t example

l

3 JK flip-flops are needed

Current state and next state outputs are 3 bits each

3 pairs of JK inputs

Design table for the binary counter example

Use Kmaps to

simplify

expression

s for JK

inputs

design

035760

One significant change

Missing states

1, 2, and 4

Use dont cares for these

states

Design table

for the

general

counter

example

K-maps to

simplify JK

input

p

expressions

Final circuit for the general counter example

sequential circuit

Counters are a special case

State transitions are indicated by arrows with labels X/Y

X: inputs that cause system state change

Y: output generated while moving to the next state

Even-parity checker

Pattern recognition

Even-parity checker

Need only two states

0 input does not change the state

1 input changes state

Simple example

two 0s in the last three input bits

FSM requires thee special states to during the initial

phase

S0 S2

After that we need four states

S3: last two bits are 11

S4: last two bits are 01

S5: last two bits are 10

S6: last two bits are 00

State diagram

for the pattern

recognition

example

1.

2.

Derive FSM

State assignment

3.

4.

5.

assignment in the last step

Logical expression derivation

Implementation

State assignment

Three heuristics

Assign adjacent states for

states that are the next states of the same state

States that have the same output for a given input

2

2

Heuristic 1 groupings: (S1, S3, S5) (S2, S4, S6)

3

3

Heuristic 2 groupings: (S1, S2) (S3, S4) (S5, S6)

Heuristic 1 groupings: (S4, S5)

pattern

recognition

example

State assignment

K-map for state assignment

Design

table

K-maps for JK inputs

Final implementation

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