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2016

WORKBOOK
Detailed Explanations of

Try Yourself Questions


Electronics Engineering
Analog Circuits

1
T1.

Diode Circuits and Voltage


Regulator Circuits

Solution:
+

10 V

C1 5 v

5 sint

D2
0.6 V

D1

C 10 v
+ 2

10 k

10 k
0.6 V
D2 off

10 k

10 V
20 V
Negative
clamper

Vc1 = 5v
T2.

T3.

Negative Peak
detector

ID1 =

ID2 = 0

VC2 = 10 v

(a)
In this question we need to determine which
diode is on and which diode is OFF, clearly diode
D3 is OFF because if it is on then current from
current source will flow from n to p terminal of
the diode D3 and this is not possible, hence D3
is OFF.
Applying the same concept, we can say diode
D2 is also OFF.
Diode D1 is on because it is forced by the
battery of 10 V.
(c)
Assume D1on, D2off, D3on

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10 0.6 (20)
= 1.47 mA
20 k

ID3 =
T4.

0 0.6(10)
= 0.94 mA
10k

(d)
When E = 1.0 V D1 on D20ff
I1 =

1 0.7
3300 + 5600 = 0.033 mA
0.7 V

1V

I1

3300

5600

When E = 1.4 V D1on, D2off

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Workbook
13.33 v

0.7 V

I1

1. 4 V

6.67 v

3300

From (i) and (ii)

= v 2
2
From equation with neglected
2v2 + v2 = 20

5600

I1 =

v1

1.4 0.7
= 0.078 mA
5600 + 3300

20
= 6.67 v
3
v1 = +13.33

When E = 2 V, D1on, D2off

v2 =

0.7 V

I1

2V

T6.

3300

(a)
10 V

5600

I1 =
T5.

2 0.7
= 0.146 mA
5600 + 3300

5 mA

Solution:
Here there are two different hire constant involved
During T1
vo = v1et/RC
At
t = T1 = T

= v 1 1
2RC

10 V

Vo1 = 0.7+ 25 V + 10 V = 35.7 V


V11 = v1 1
2

+10V
5 mA

During T2

Vo = v 2e

= v 2e

20 V
+

25 V
+

T / RC

= v2[1 ]
V21 = v 2 1
RC

= 20
2

T7.

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Solution:

Io = 5 A
2 m

...(i)
I

v 12 + v1 = 20
v2 v2 + v1 = 20
v1 + v2 v2 = 20

5 k

Vo 2 = 10 V 25 V 20 V = 55 V

+ v 2 = 20
2

v1 + v 2 v1

V02

10V

v11 + v 2 = 20
v1 v1

5 k

vo = v11 = v1e T / 2RC

t / RC

Vo1

+
0.7 V

+
25 V

IR

...(ii)

10 v

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Electronics Engineering Analog Circuits

I 7 = Io 11
I=
I=
IR =
=

R=
T8.

11
5A
= 7.85 A
7
Io + IR
I Io = 7.85 A 5 A
2.85 A

10
v
=
= 350 k
2.85
A
IR

115 2 50
2k + 50
2k

= 115 2
115 v 2

50 v

(a)

Vin (0.7) = Vout


Vin + 0.7 = 1.1
Vin = 1.1 0.7 = 0.4 v
T9.

vo =

(b)
Positive half cycle
D1on, D2off

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17.9

180

Negative half cycle


D1off, D2 off
V0 = 50v

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2
T1.

Transistor Biasing and Thermal


Stabilization

Solution:

15 V

100 k

5 0.7
33.33k + 101 3k

IC1 = IB1 = 1.28 mA


IE1 = (1 + )IB1 = 1.29 mA
VC1 = 15 IC1 RC1
= 15 1.28 mA 5 = 8.6 V

5 k
Q1

15 V
3 k

50 k

15 V
2 k
5 k
0.7 +

VTH =

15 50k
=5V
100k + 50k

RTH = 100 k 50 k = 33.33 k


15 V

VC1 = 8.6 V

Q2
Q1
2.7 k
RE

5 k

VE2 = VC1 + VEB2


= 8.6 + 0.7 = 9.3 V

33.33 k

IE2 =

+0.7
5V

IB1

= 2.85 mA

3 k

IC2 =

VTH IB1RTH VBE IERE = 0


IB1 =

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VTh VBE
RTh + (1 + ) RE

15 VE 2 15 9.3
=
RE 2
2k

1+

IE 2

100
2.85 mA = 2.82 mA
101
= IC2 RC2
= 2.82 mA 2.7 k = 7.62 V

VC2

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6
T2.

Electronics Engineering Analog Circuits


ICactive = IBactive
= 100 17 A = 1.7 mA
KVL in output loop

Solution:
VCC IC1R2 VCE1 = 0
6 1.5 mA R2 3 = 0
R2 = 2 k
IB1 =

10 V

IC1 1.5mA
=
= 0.01 mA
1
150

ICsat
3 k
VCsat = 2.5 V

IB2 will be equal to IB1 as there is no change in


R1
IC2 = 2 IB2
= 200 0.01 mA = 2 mA
VCE2 = VCC IC2R2
= 6 2 mA 2k = 2 V
The new operating point is
Q(2 V, 2 mA)
T3.

VCEsat = 0.2 V
VE = 2 k 1.7 mA
2

VCsat = 3.6 V
VCEsat = 0.2 V
VE = 2 k 1.7 mA = 3.4 V

Solution:
Assume Q is in active region

ICsat =

ICsat > ICactive

3 k

50 k

T4.
10V

5V

2 k
I B active

IBactive =

5 0.7
50k + 101 2k

10 3.6
= 2.13 mA
3k

Active region

Solution:
Since I1 = 0.2 mA and I2 = 0.3 mA. So n1 = 2
and n2 = 3, because we need to find minimum
number of BJT required.

4.3
= 17 A
252

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3
T1.

Small Signal BJT Amplifiers

(b)

KVL in output loop


12 IE 1 k VEC 2k IE = 0
12 1.3 mA 1k VEC 2 k 1.3 mA = 0
VEC = 8.1 v
Given range 1 VEC 11 v
VEC = 11 8.1 = 2.9 v
The voltage swing is
2VEC = 2 2.9 = 5.8 v

12 V

10 k

1 k

VO
VS

50 k

2 k

T2.

(d)
270

= 100
VA =

Vi

12 0.7 10
(IE)Q =
= 1.3 mA
1k
DC Circuit

RL

12 V

VTh

gm = 2 mS ; ro = 250 k

1 k
RTH

r = re =

+
VEC

VTH

RTh = 50 k 10 k = 8.33 k
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ro
270

2 k

12 50 k
VTH =
= 10 v
50 k + 10 k

100
=
= 50 k
gm 2 mS

C
+

IE
Vi

r
+

V
IB

g m v

+
VTH

RL

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Electronics Engineering Analog Circuits

r
r + 270

V = v i
=

T4.

12 V

50 k
v = 0.994 vi
50 k + 270 i

3.9 k
220 k

VTh + rogmv v= 0
VTh = rogmv v
= (1 + gmro) (0.994vi)
= (1 + 2mS 250 k) 0.994vi
VTh = 497.9 vi
T3.

(d)

C2

C1
Vi

(a)
DC circuit

12 V

Q2
3.9 k (1 + )IB

220 k
Vo

IB

Q1

Vi

B2
r2
B1

C1

+ VBE

C2
+
V2

gm2 V2

IB =
Vo

= 0.0163 mA
IE = (1 + )IB = 1.97 mA

E2
vi

V1

+
r1

gm1V1

Vi = V1
Vo = V2
KCL at the output node
V
gm1V1 + o = gm2 V2
r 2
gm1 Vin +

12 0.7

(1 + ) 3.9 k + 220 k

26 mV
re = VI =
= 13.15
1.97 mA
IE
Vi

220 k
1 Av

Vo

re
1.578 k

IB

220 kAV
Av 1

3.9 k

= 220 k

Vo
= gm2Vo
r 2

Vo + gm 2 = gm1Vi
r
2

Av =

Vo
gm1 r 2
=
Vi 1 + gm 2 r 2

Vo = (220 k 3.9 k) IB
Av =

RC P RL
3.83 k
=
re
13.15

= 291.41

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Workbook

220 k
Vi
=
P re
1A v
Ii

ro =

VA
=
IC

= 0.752 k 1.578 k
= 0.509 k = 509.4

re =

= 17.71
gm

Zi =

T5.

(b)

17.71

VS

hfe =

I c
2 mA
=
= 100
Ib 20 A

(?)
Since collector current at operating point is given
in the question we do not need to solve the circuit
at DC.
The parameters of BJT are

gm =

0.56 V1

V +
1
iS

RS=
100 k

3 k
10.4 k

V0
4 k

4 k = RL

25.6 k

Vbe
0.1 V
=
= 2 k
hie =
Ib
50 A

T6.

The circuit for AC analysis,

Assuming, base current is zero,


V1 = Vs
and
Vo = 0.56 V1 (4 k || 4 k)
Vo
= 112.30
Vs

ICQ 1.46
=
= 0.056 S
26
VT

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4
T1.

Field Effect Transistor


Amplifiers

(a)

MOSFET M3

10 v

ID = kn3 (VGS3 VT)2


0.5 mA = 36

M1

M2
v2

T2.

M3

Ad VD = VG we conclude that each MOSFET


is in saturation.
ID = kn1 (VGS VT)2
MOSFET M1
ID = kn1 (VGS1 VT)2
1 W
. (5 1)2
2 L

(c)
If VTH = 0.4 v
PMOS in depletion mode
VS = 1.5 V

1.5 V

VG = 0.5 V

0.5 V

VSD < VSG + VTH Triode region


VSD = VS VG = 1.5 0.5 = 1 v

VS = 0.9 V

MOSFET M2
ID = kn2 (VGS2 VT)2

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VD = 0

VSD = VS VD = 1.5 0 = 1.5 v


1.5 > 1 V + 0.4 current saturation region

W
= 1.73
L 1

W
= 6.94
L 2

(2 1)2

VSD > VSG + VTH current saturation

VGS1 = 10 5 = 5 v

1 W
0.5 mA = 36

2 L

W
= 27.8
L 3

v1

0.5 mA = 36

1 W

2 L

0.9 V
2 (3

1)2

VD = 0.9 V

VG = 0

0.9 V

PMOS in depletion mode.


VSD = VS VD = 0.9 0.9 = 0
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11

Workbook

VSG = VS VG = 0.9 0 = 0.9


0 < 0.9 + 0.4 triode region
T3.

T5.

(a)
VDD

iD

(b)

M1

3v

rOL (load)
v0

vD1
M1

M2

I1

v2

vGSD

M2
G

Given
VTH = 1 v
So MOSFET is an n channel enhancement
MOSFET in both transistors
VD = VG

vi

Vgs

rOD

rOL

V0 = gm Vgs rOD rOL


Vi = Vgs

3 VDS1 VDS2 = 0

V0 = gm vi (rOD rOL)
V0
Av = V = gmD (rOD rOL)
i

VDS1 + VDS2 = 3 V
3
= 1.5 v (VDS1 = VDS2)
2

gmD = 2 knD iD

VGS2 = VDS2 = 1.5 v = V2


VGS1 = VDS1 = 1.5 v
1
W
2
= n Cox (VGS1 VTH )
2
L
1
2
= 20 3 (1.5 1) A = 7.5 A
2

(b)
It is common drain amplifier.

gm Rs
gm 4k
Av =
=
= 0.95
1 + gm Rs
1 + gm 4k

= 2 1 0.2 = 0.874 mA/v


D = L

Since

I1 = ID1 = ID2

T4.

gmD Vgs

M1 & M2 are in current saturation

VDS2 =

1
1
rOD = rOL = i = 0.01 0.2 = 500 k
D

Av = 0.894 (500 k 500 k) = 224


T6.

(a)
DC circuit
ID
1 mA

100 k

4 k

gm = 4.75 m
gm = 2 kn (VGS VT)
ID

= 2 kn k + VT VT
n

gm = 2 ID kn
gm = 2
W
= 47
L
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1
W
ID n Cox
L
2

5 v

+5 v

ID = IS = I mA
n channel enhancement MOSFET
Assume Q in saturation.
ID = kn (VGS VT)2
I = 1 (VGS 1)2

VGS = 2 V
gm = 2 kn (VGS VT)
= 2 mA/V
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Electronics Engineering Analog Circuits

12
T7.

(b)
In the previous part we calculated
transconductance of the device (gm = 2 mS).
Now, drawing the circuit for AC analysis
50 k
i1

500

I in

W
L = 2
3

VGS1

Current Mirror

As

Vo
= RD || RL
i1

2
VGS2

W
L = 2
1
v0

IG = 0

10 k

4 k

From the figure,


V0 = gm VGS (RD RL)
gm Vgs = i1

T8.

I mA

V0

VS

(a)

gm Vgs

V +
gs

T9.

I mA

W
=1
L 2

W
= 2
L

Iin = 2 I mA
= 2 mA

Vo = 0.283 sint V

(b)

V
CMOS

r
fie
pli
Am

=V
0
V

+V

=V
0

S)
MO
(P

+V

)
OS
M
(N

Vt

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5
T1.

BJTs & FETs at High Frequencies

(a)

Since = and IE = 1 mA so re = 25 .

To calculate the fL1 and fL2 we will draw the small

So for

signal model of the two circuit (we will use


T -model of the device).

fL1 =

where, Req is equivalent resistance across


capacitance CE .
R eq = Re + re in Amplifier 1
and
R eq = (Re || re) in Amplifier 2

RC

So,

V0

fL1 =

1
(Re + re ) CE

fL2 =

1
(Re || re ) CE

gm Vbe
T-Model

+
Vbe

re

So,
Re

24.93
10,000 + 25

fL1
= 2.55 103
fL2
T2.

RC
V0
gm Vbe
T-Model

re

Re

fL1
Re re
10 25
=
=
fL2
(Re + re ) (10 k + 25 )

CE

Amplifier-1

+
Vbe

1
Req CE

CE

(a)
To find fH and fL we draw the small signal model:
The small signal paramters of the BJT are

gm =

IC 0.99 mA
=
= 0.0396 A/V
25 mV
VT

re = 25.0
From the circuit we can see that the capacitance
(C = 10 F) has high pass characteristic so it

Amplifier-2

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Electronics Engineering Analog Circuits

14

decide fL and capacitance (C = 15 pF) has low


pass characteristic so it decide fH .
To find out fL

fL =

1
Req C

Ri b = 53.025 k
So,
and
R eq = 0.1 k + (53.025 || 40 || 5.7) k
Now at high frequency the capacitance
(C = 15 pF) will play its role. The small signal
model for high frequency will be

Here, C is 10 F and Req is the equivalent


resistance seen by the capacitance.
Lets draw the small signal model to find Req:

5.7 k

gm Vbe

40 k

re = 25 k

So,

fH =

0.5 k

Ri b = (re + 0.5 k)
[When emitter resistance is seen through
bas it get multiplied by ( + 1)]

V0
10 k

C = 15 pF

re =
40 k
0.5 k

10 k

40 k
Rib

5.7 k

V0

T-Model

VS

gm Vbe

0.1 k

5 k

0.1 k C = 10F

5 k

1
2 Req C
1
10
103 15 1012
2
3

= 3.183 MHz
So, fH fL = 3.18 MHz

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6
T1.

(d)
Given that

Multistage Amplifiers

ID = 0.4 mA and

K n1 = 0.8 mA/V2
Kn2 = 0.8 mA/V2
4 Kn1 ID = 1.13 mA/V

So

gm1 =

and

gm1 = gm2 = 1.13 mA/V

The gain of the cascade connection will be gm1 Rd


gain = 1.13 mA/V 2.5 k = 2.85

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7
T1

T2

Feedback Amplifiers

(a)
The overall forward gain is 1000 and close loop
gain is 100. Thus, = 0.009.
Now, when gain of each stage increase by 10%
then overall forward gain will be 1331 and using
the previous value of the close loop will be
102.55.
Close loop Voltage gain increase by 2.55%.

T4.

(b)
Given that A >> 1
So the voltage gain

A
1

1 + A

From the circuit we see that feedback factor


is
R2
20
1
=
=
R1 + RL
80 + 20 5

It is voltage shunt
v0
+

IS

Rf
90

T3

vf
+

Rf

If

If
1
=
v 0 Rf

It is voltage series ckt can be called as series


shunt feedback.

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So,

1
5

Voltage gain = 5 (because the


amplifier is an inverting amplifier)
T5.

(b)
The feedback element is Rf it samples voltage
and mix current so shunt-shunt feedback.

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8
T1.

Oscillators

(a)
Consider the following circuit
2R

T2.

(a)
Vy

We need to find

2L

Vx

R
+
L

Vf

Va

+
A

, so

Vx

Vo

Vy

Nodal analysis at node A

Va Vy
Va Vx
V
+ a +
=0
1/ sC
1/ sC
R

First of all we will find the feedback factor


=

R j L
Vf
=

Vo R j L + 2R + 2 j L

Nodal analysis at node-B

1
2R 2L
5 j

L
R

From abouve two equations

Vy Va Vy
+
=0
R
1/ sC
1 + 3sCR + 2s 2C 2R 2 s 2C 2R 2
Vy
= Vx
sCR

For Barkhausen criteria we need


A = 1
and imaginary part of A should be equal to 0
2R 2L
So,
=0

L
R

So,
and

Copyright

R
=
L

f=

R
2L

Vy

So,
T3.

Vx

sCR
1 + 3sCR + s 2C 2R 2

(a)
Now the value of
as

Vf
in the given circuit in same
Vo

Vy
Vx

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Electronics Engineering Analog Circuits

18

So,
Vp = 6 V
when output is 12 V then

sCR
=
1 + 3sCR + s 2C 2R 2

So,

R1

j CR
(1 2C 2R 2 ) + 3 j CR

For Barkhausen criteria, we need


A = 1 0
So, phase of = 0
So imaginary part of = 0
So 1 2 C 2 R 2 = 0
=
T4.

R2
C

Vo

+
2 k
P

1
RC

10 k
10 k

So,

(a)
The output can be 12 V only,
when output is 12 V then

Vp = 10 V

R1
R2
C

Vo

+
2 k
P

10 k
10 k

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9
T1.

Power Amplifiers

(a)
Solving the given question at DC, assuming both the devices are in forward active region.
+9 V

loop 2
9.1 k
I

12 k
IE 2

IB2
IC 1

IB 1

Q2
IC 2

Q1 = 80
100 k

IE 1
loop 1

43 k

24 k
9 V

9 V

So KVL in loop-1

(100 k) IB1 + 0.7 + (24 k) IE1 = 9


(100 k) IB1 + (24 k) 81 IB1 = 8.3

IB1 = 4.06 A

So,

IC1 = 0.325 mA and IE = 0.328 mA


1

Now in loop-2

9 (12 k) IE2 + (9.1k) (IC1 + IB2 ) 0.7 9 = 0


So,

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(9.1k) IC1 0.7 = (9.1k) IB 2 + (12 k) IE 2


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Electronics Engineering Analog Circuits

20

IB 2 = 2.006 A

IC 2 = 0.184 mA and

So, now we can find VCE 1 = 0.186 mA

and

IE 2 = 0.186 mA

VCE 2 = 7.85 V

So, Q -points will be (325 A, 7.16 V) and (184 V, 7.85 V).


T2.

(c)
The DC power = VCC ICQ = 13 V 5 mA = 65 mW
Now, at DC inductor act as short circuit
So,
VCEQ = 8 V

PAC =

So, maximum efficiency =

1
8 25 = 20 mW
2

AC power
20 mW
100 =
100
Power delivered
65 mW
16 mW
100 = 24.6%
65 mW

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10
T1.

Operational Amplifiers

T2.

(c)
when diode is ON it is replaced by short circuit
and the circuit can be drawn as shown below:

(b)
output of op-amp 1
R
R

V1
10 V

Vin
V +

1 k

0.5 k

1 k

VS

It is connected to schmitt trigger (inverting


mode) clockwise.
But inverting amplifier + inverting schmitt trigger
anticlockwise.

V0

12

Vo = 0.5 Vs 5
when diode is OFF then it is replaced by open
circuit and circuit can be drawn as shown below

1 k

T3.

1 k
VS

(b)

Rif =

v0 = vi

Ri
Ri
=
A

1 + A

Ab >> 1

+ Vf

Vo = Vs
Thus, in 1 phase the slope of the transfer
characteristic should be 1 and in another phase
it should be 1/2. Hence, option (c) is correct.

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I f = 10 k

2 k

vin

v0
20 k

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Electronics Engineering Analog Circuits

22

T5.

voltage shunt

(b)
i3

2 k

vin

v0

10 k

Vf 10 k
+

10 k

i3 10 k

20 k

vin

If

i2

B
10 k

+
A
10 k

i1

From the circuit,


VE = io RL
VE = VA (Virtual short concept)
i1 = i2 = i3
If we apply KVL between node B and C,
VB = VC (Virtual short concept)

1
=
10k
10k
105

1
10k

10 10 106
105
R if = 1 k

i1 = i2 = i3 =

T4.

(b)
Redrawing the circuit by replacing amplifier with
its block diagram from the given properties
Ri = ; R0 = 0 ; voltage gain = AV
Rf
iin

vin +

v0 = AV vin

Vin V0
Rf

iin =

V [1 Av ]
Vin Av Vin
= in
Rf
Rf
Vin
Rf
=
iin
1 Av

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v in
20 k

VC VD = i3 10 k =

v in
2

and

VA VB = i1 10 k =

v in
2

VB = VC
VD VE = vin

io =

v in
Rf

T6.

(c)
If diode or BJT it is logarthmic amplifier.
If MOSFET is kept in feedback then it is square
root amplifier.

T7.

(a)
In the given circuit the op-amp diode
combination form a super diode and this
complicated question can be simplified by
replacing the op-amp diode combination by a
single ideal diode as shown below.

AV vin

iin =

Rin =

io

RL

If
1
= V =
10k
0

Ri
A =

Vf
= V = 1
0

Rif =

Rf

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23

Workbook
C

1
5 2 1 03
20 103 106
= 0.5

=
+
RL

vin

Vo

vo(t )
0

10 12 15
t (mS )

Now this circuit is a simple clamper, thus answer


is option (a).
T8.

T9.

(c)
It is inverting op-amp and there is no feedback
inthe ckt op amp will saturate to Vsat.
(d)

1 t
V (t )dt
Rc 0 in
1
Vin t
=
10k 2f

V0 (t) =

At t = 2 mS
=

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10k 2f

0.5
1.0
1.5

T10. (a)
From the figure we can see that when input is
positive then diode is off and op-amp works in
open-loop with output equal to +Vsat .
When the input is negative then the diode turn
on and it get replaced by a 0.7 V battery, so
now output is equal to Vin 0.7.
So option (a) is correct.

5 2 mS

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11
T1.

T2.

Function Generators, PLL &


Wave Shaping Circuits

(c)
From the Hysteresis voltage transfer
characteristic we can see that the Schimitt
trigger has to be non-inverting.
The saturation level is 10 V and the upper and
lower threshold are +3 V and 3 V respectively,
so option (c) is correct according to all
requirements.

So,
R1 = 2 k
Similarly when output is +10 V then threshold is
+8 V so
Vi

2 k

(b)
The saturation level of output are 10 V.
When output is 10 V then threshold voltage is
5 V so
Vi

So,

Vo

+
R

2 k

T3.

5=

2
10
R1 + 2

20
R1 + 2

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Vo

R2

10 2
=s
R2 + 2

20 = sR2 + 16
4 = sR 2
R2 = 0.5 k

Threshold voltage is

(c)
First op-amp form a high pass filter with cut-off
frequency equal to 79.7 Hz.
Second op-amp form a low pass filter with cut-off
frequency equal to 318.30 Hz. So the series
combination of low pass filter and high pass
filter form a band pass filter.

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Workbook
T4.

25

(d)
Vi

I1

M1

M2
Q

I2

Output

Vi

t (ns)

40

43

43

43

83

t (ns)

86

t (ns)

t (ns)

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