David Maliniak, Electronic Design Automation Editor


PCBs Are Not So Simple Anymore
rinted-circuit boards (PCBs) are at the heart of the modern electronic packaging found in almost every consumer electronics product. In essence, a PCB creates the connections between components within a system. Mass reproducibility for circuits with even a modicum of complexity and/or speed requires a PCBbased packaging scheme. When designed correctly, PCBs bring predictability. A correct design minimizes wiring lengths and lays out the board so signal-integrity issues are controlled. It also makes it much easier to find components during troubleshooting and repair. Even high-pin-count ICs can be removed, if necessary, and replaced.

The printed-circuit-board design infrastructure has grown, and PCBs themselves will face future challenges.
Up to about 10 years ago, advanced PCB design technologies like microvias, high-density interconnects (HDIs), embedded passives, and high-pin-count FPGAs were available primarily to power users in global organizations designing bleeding-edge products. But these design technologies are rapidly entering the mainstream, making them challenges for a broader spectrum of PCB designers than ever before.

Today’s PCB Design Environment
Most of today’s PCBs are pushing if not exceed-

A Supplement to Electronic Design/January 19, 2004

Sponsored by Mentor Graphics

ing the limits of classic board design 1. PCB design complexity is increasing at an accelerated rate with the addition of high-density (Fig. 1). In mobile telecom, interconinterconnects, embedded components, gigabit data rates, and other technologies. nect and board dimensions are shrinking rapidly, while designs are using fewer but more complex components with higher pin counts. At the same time, boards for networking and computer applications are growing, with more interconnect and ground plane layers. Data rates of up to 10 Gbits/s are resetting frequency standards for ICs. As IC vendors replace parallel bus architectures with serial asynchronous architectures (Third Generation I/O or “3GIO”), challenges such as jitter, lossy lines, and bit speed design, FPGA-on-board integration, team error rates are replacing delay, timing, crosstalk, design, and PCB fabrication, design, and interovershoot, and other traditional high-speed connect to library, constraint, and data managedesign challenges. In other words, it’s no longer ment) is a critical aspect of a company’s investreliable or viable to follow “rules of thumb” in today’s high-speed rout2. Connections between ICs using the 3GIO architecture are routed using carefully matched ing and verification. differential pairs. The relatively new 3GIO technology uses standards for encoding and decoding electrical signals in serial asynchronous architectures. Already, Intel Corp. has incorporated 3GIO technology into its PCI Express standardization environment. A significant percentage of today’s PCBs are currently operating in a frequency range of 1 to 10 GHz. From a PCB design perspective, most of today’s high-speed design tools lack the advanced modeling and verification requirements utilized by 3GIO technology. With the onset of serial asynchronous architectures, these tools must further accommodate new design concepts for routing highly constrained differential pairs (Fig. 2). ment in a PCB design solution. This pullout Understanding current and future PCB design challenges in all areas of PCB design (from high- looks at each of these challenges.
Sponsored by Mentor Graphics


What Goes Into A PCB


asic PCBs comprise a rigid sheet of epoxy-impregnated fiberglass material with thin copper sheets affixed to one or both sides. This is known as copperclad. In multilayer boards (those with more than two copper layers), a piece of material called prepreg is placed between core layers. The outer copper surface of the PCB must be processed to form circuit paths, or traces, that make the connections between components. Analogous to wires, the traces are formed using a photolithographic process (Fig. 1). In that process, the copper layers are treated with chemical etching that removes unneeded portions of the copper, leaving only the traces and pads required for component soldering. Pads can be fabricated in many shapes and formats. Components are typically attached to boards in one of two fashions: surface mounting or through hole, in which case the board must be drilled after photolithography is completed. Through holes can be plated in cases where connections are required between the surface copper and either internal copper layers or the reverse side of the board (Fig. 2).
Solder flow Copper plating Solder mask Component lead

Photoresist film Copper film Core material UV light Expose photoresist Mask

Develop photoresist Etch copper Strip photoresist Copper wires

Result Core material

THE PHOTOLITHOGRAPHIC PROCESS 1. The most common process for creating the circuit traces on a PCB is subtractive. A mask, or photoplot of the circuit-trace artwork, is placed over the photoresist after a photoresist film is applied to the copper cladding. The photoresist is then exposed and developed, and the superfluous copper is chemically etched from the board. The remaining photoresist is stripped from the surface of the traces, leaving a finished board.

ANATOMY OF A PLATED-THROUGH HOLE 2. Many boards still carry through-hole components, as distinguished from surface-mount types, and require plated-through holes. Plated holes are required when connections must be made either to internal copper layers or to the opposite side of the board, or to both.

Good solder flow

Copper cladding/foil Adequate spacing

Sponsored by Mentor Graphics

The PCB Design Flow
Every PCB is unique in its size, function, and usage and is custom designed and fabricated (see the figure). The following steps explain the basic process for creating a PCB.
Logical design • Design capture • FPGA design integration Physical design • Component placement • Interconnect routing

Step 1: System design
The system-design phase of PCB design involves creating a schematic diagram. This includes collecting the symbols for all of the off-the-shelf and custom components that are needed for the PCB to function as designed. The schematic must also represent the interconnects between the components.

Step 2: Functional verification
Designers must ensure that the PCB will function as designed before it is fabricated. The functional verification step confirms the original schematic by using software models for each component and interconnect to simulate the board’s functionality.

1 2 3 4 5 6

Verification • Functional verification • Signal-integrity analysis • Timing analysis Part selection/creation

• Electromagnetic interference • Manufacturability • Testability Library and design data management

The PCB design process contains three primary elements: logical design, physical design, and verification.

Step 3: Physical design
After schematic creation and verification, it’s time to create a representation of the physical PCB. To do so, the designer places the schematic’s parts on the board and connects them as defined by the schematic. Routing is accomplished with conductive paths called traces, which may run along and between multiple layers of a board. Traces transition from one layer to the next through via holes.

traversing the board’s traces aren’t degraded by effects such as crosstalk, overshoot, and undershoot that can result in logic errors. Designers must also ensure that all transmitted signals arrive at their destinations at the proper time.

Electromagnetic verification:
This process determines whether the PCB works within any applicable health standards. For example, if the PCB is designed for a mobile phone, this step will determine the level of radiation emitted and whether it falls within the required guidelines.

Step 4: Final verification Design for manufacture:

Once the board has been created, three different verification steps ensure that the board can be manufactured as designed. This step verifies whether or not the physical design of the PCB can be manufactured the way it is designed. The design is checked against its specific design rules. If violations of these rules are uncovered, the board must be revised and resimulated.

Putting It All Together


Signal integrity and timing verification:
While designing the PCB, engineers determine the board’s functionality as well as its speed. Signal-integrity checks ensure that signals

The steps outlined above are only a framework for PCB design. Ideally, one should embark on the verification process as early as possible so errors can be caught when they are much easier to correct. There are tools that allow designers to verify designs as they are creating the board. Pre-defined rules that encapsulate the manufacturing, timing, and radiation requirements are incorporated with these tools, such as autorouters, to warn designers when a part is not placed properly or when an interconnect will cause a timing or signal problem.

PCB Fabrication, Packaging, And Interconnect


ntil recently, most design teams used traditional laminate structures and vias (both through and blind, or interlayer, vias) during PCB fabrication, packaging, and interconnect. But IC packages such as ball-grid arrays (BGAs), chip-on-board (COB), and chip-scale packages (CSPs) are driving the need for build-up structures and microvia technology (see the figure). Such packages enable designers to produce smaller PCBs. The advances in build-up material and microvia technology also permit designers to build passive components into the boards. These resistors, capacitors, and inductors are embedded within laminate layers as opposed to being mounted on either surface of the PCB. The use of embedded passives further reduces the overall size of the board, saving additional laminate material costs. To successfully reap these benefits, PCB design tools must use true 45° routing, localized rule definition, complex rules for microvia routing, advanced interconnect, and the automation of large device geometry/footprint creation. This includes accounting for fine-pitch parts, mixed routing rules, specialized algorithms, and place and route inside the laminate material. High-density, high-pin-count IC packages are driving the need for
high-density interconnect (HDI) layers.

FPGA-On-Board Integration


s ASIC design costs rise and the price/performance ratio of FPGAs improves, PCB design teams are turning to FPGAs more often. In fact, boards often contain one or more FPGAs with over 1500 pins. PCB and FPGA design occurs concurrently yet independently. Tight links between the two design processes can shorten a product’s overall time-to-market. Alliances between PCB design tool vendors and FPGA vendors have aided advanced FPGA device modeling and high-pin-count symbol and part creation. It is now possible to create and fracture PCB schematic symbols and geometries directly from the FPGA design tool. It’s also possible to manage design constraints and pinout assignments between the PCB and the FPGA for any number of FPGAs (see the figure). This integration automates tedious The PCB and the FPGA design solutions require tight bidirectional integration. manual design processes as well as reduces routing and timing problems once associated with traditional FPGA-on-board integration. high-speed verification and analysis. Kits typically include buffer models, comVendor alliances also have yielded FPGA design kits to drive PCB layout and ponent footprints, constraint rules, and reference designs.

Team Design


ith time-to-market so critical a driver, companies are using concurrent/parallel design techniques during multiple stages of the PCB design process. Worldwide, 24/7 design schedules are traditional concurrent design methods. In reality, however, these approaches are more serial than parallel. Therefore, the schedule breaks down if the design engineer isn’t available. A more modern team design methodology lets multiple designers work simultaneously on the same layout (see the figure). Reserved areas are drawn on a board, which is then split into partitions that are assigned to various team members. Team members can view and respond to the work their peers are contributing to their respective partitioned areas and the overall master design. This method greatly reduces designcycle time through parallel design Team design methodologies enable processes. It also facilitates designconcurrent, parallel PCB design as team collaboration, effective resource well as enabling specialists (e.g., RF, management, and shorter layout cycles. analog, and digital) to design on the same PCB in parallel instead of serially.

Library, Constraint, And Data Management


ith team approaches to PCB design on the rise, effective library, constraint, and design data management is a must. A company with far-flung design centers will have a central library that contains all of its fully qualified/preferred parts. The local design sites must have access to this central library to build and update their local library but may only want those parts from the central library that apply to their types of products (commercial, military, consumer, and so on). This requires a sophisticated global library management system. Another example of the need for data and infrastructure management is that

many companies use several different design tools, all of which require the same design rules, or constraints, in different formats. Manual entry of constraints into each tool is time consuming and error-prone. Toss in high-pin-count devices with even more complex constraints and we find design librarians stretched very thin. Thus, management of work-inprocess (WIP) design data and release management is suffering. In response to these challenges, many companies are rushing to implement constraint management systems.



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