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CD4027BMS

CMOS Dual J-K


Master-Slave Flip-Flop

December 1992

Features

Pinout

High Voltage Type (20V Rating)

CD4027BMS
TOP VIEW

Set - Reset Capability


Static Flip-Flop Operation - Retains State Indefinitely
with Clock Level Either High or Low

Q2 1

16 VDD

Q2 2

15 Q1

Medium Speed Operation - 16MHz (typ.) Clock Toggle


Rate at 10V

CLOCK 2 3

14 Q1

RESET 2 4

13 CLOCK 1

K2 5

12 RESET 1

J2 6

11 K1

SET 2 7

10 J1

Standardized Symmetrical Output Characteristics


100% Tested For Quiescent Current at 20V
Maximum Input Current of 1A at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC

9 SET 1

VSS 8

Noise Margin (Over Full Package Temperature Range):


- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V

Functional Diagram

5V, 10V and 15V Parametric Ratings

SET 1

Meets All Requirements of JEDEC Tentative Standard


No. 13B, Standard Specifications for Description of
B Series CMOS Devices

VDD
16

15 Q1

J1 10
K1 11
CLOCK1 13

F/F1

14 Q1

Applications
RESET1 12

Registers, Counters, Control Circuits

SET2

J2

K2

CLOCK2

Description
CD4027BMS is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K masterslave flip-flops. Each flip-flop has provisions for individual J, K,
Set Reset, and Clock input signals. Buffered Q and Q signals
are provided as outputs. This input-output arrangement provides for compatible operation with the Intersil CD4013B dual D
type flip-flop.

RESET 2

1 Q2
F/F2
2 Q2

8
VSS

The CD4027BMS is useful in performing control, register, and


toggle functions. Logic levels present at the J and K inputs
along with internal self-steering control the state of each flipflop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and reset functions
are independent of the clock and are initiated when a high level
signal is present at either the Set or Reset input.
The CD4027BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
H4T
Frit Seal DIP
H1E
Ceramic Flatpack H6W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999

7-780

File Number

3302

Specifications CD4027BMS
Absolute Maximum Ratings

Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V


(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for
10s Maximum

Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER
Supply Current

Input Leakage Current

SYMBOL
IDD

IIL

CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND

IIH

LIMITS
TEMPERATURE

A
A

-55oC

+25oC

-100

nA

+125o

VDD = 18V, VIN = VDD or GND

VIN = VDD or GND

VDD = 20

-1000

nA

-55oC

-100

nA

+25oC

100

nA

+125oC

1000

nA

100

nA

50

mV

-55oC

Output Voltage

VOL15

VDD = 15V, No Load

1, 2, 3

+25oC, +125oC, -55oC

Output Voltage

VOH15

VDD = 15V, No Load (Note 3)

1, 2, 3

+25oC, +125oC, -55oC 14.95

VDD = 18V

UNITS

200

+25

+125oC

VIN = VDD or GND

MAX

VDD = 20

MIN
-

oC

VDD = 18V
Input Leakage Current

GROUP A
SUBGROUPS

Output Current (Sink)

IOL5

VDD = 5V, VOUT = 0.4V

+25oC

0.53

mA

Output Current (Sink)

IOL10

VDD = 10V, VOUT = 0.5V

+25oC

1.4

mA

Output Current (Sink)

IOL15

VDD = 15V, VOUT = 1.5V

+25oC

3.5

mA

Output Current (Source)

IOH5A

VDD = 5V, VOUT = 4.6V

+25oC

-0.53

mA

Output Current (Source)

IOH5B

VDD = 5V, VOUT = 2.5V

+25oC

-1.8

mA

Output Current (Source)

IOH10

VDD = 10V, VOUT = 9.5V

+25oC

-1.4

mA

Output Current (Source)

IOH15

VDD = 15V, VOUT = 13.5V

+25oC

-3.5

mA

-2.8

-0.7

0.7

2.8

N Threshold Voltage

VNTH

VDD = 10V, ISS = -10A

+25oC

P Threshold Voltage

VPTH

VSS = 0V, IDD = 10A

+25oC

VDD = 2.8V, VIN = VDD or GND

+25oC

VDD = 20V, VIN = VDD or GND

+25oC

VDD = 18V, VIN = VDD or GND

8A

+125oC

VDD = 3V, VIN = VDD or GND

8B

Functional

Input Voltage Low


(Note 2)

VIL

VDD = 5V, VOH > 4.5V, VOL < 0.5V

1, 2, 3

Input Voltage High


(Note 2)

VIH

VDD = 5V, VOH > 4.5V, VOL < 0.5V

1, 2, 3

Input Voltage Low


(Note 2)

VIL

VDD = 15V, VOH > 13.5V,


VOL < 1.5V

Input Voltage High


(Note 2)

VIH

VDD = 15V, VOH > 13.5V,


VOL < 1.5V

7-781

-55oC
+25oC,

NOTES: 1. All voltages referenced to device GND, 100% testing being


implemented.
2. Go/No Go test with limits applied to inputs.

VOH > VOL <


VDD/2 VDD/2

+125oC, -55oC

1.5

+25oC, +125oC, -55oC

3.5

1, 2, 3

+25oC, +125oC, -55oC

1, 2, 3

+25oC, +125oC, -55oC

11

3. For accuracy, voltage is measured differentially to VDD. Limit


is 0.050V max.

Specifications CD4027BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER
Propagation Delay
Clock To Q, Q
Propagation Delay
Set To Q Reset To Q
Propagation Delay
Set To Q, Reset To Q
Transition Time

Maximum Clock Input


Frequency

SYMBOL
TPHL1
TPLH1
TPLH2

TPHL3

TTLH
TTHL

CONDITIONS (NOTE 1, 2)

GROUP A
SUBGROUPS TEMPERATURE

VDD = 5V, VIN = VDD or GND

VDD = 5V, VIN = VDD or GND

VDD = 5V, VIN = VDD or GND

VDD = 5V, VIN = VDD or GND

FCL

VDD = 5V, VIN = VDD or GND

LIMITS
MIN

MAX

UNITS

+25oC

300

ns

10, 11

+125oC, -55oC

405

ns

+25oC

300

ns

10, 11

+125oC, -55oC

405

ns

+25 C

400

ns

10, 11

+125oC, -55oC

540

ns

+25oC

200

ns

10, 11

+125oC, -55oC

270

ns

+25oC

3.5

MHz

10, 11

+125oC, -55oC

3.5/1.35

MHz

MIN

MAX

UNITS

30

60

NOTES:
1. VDD = 5V, CL = 50pF, RL = 200K
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current

SYMBOL
IDD

CONDITIONS

NOTES

VDD = 5V, VIN = VDD or GND

1, 2

TEMPERATURE
-55oC,

+25oC

+125oC
VDD = 10V, VIN = VDD or GND

1, 2

-55oC,

+25oC

+125oC
VDD = 15V, VIN = VDD or GND

Output Voltage

VOL

VDD = 5V, No Load

1, 2

1, 2

+125oC

120

+25oC, +125oC,

50

mV

-55oC,

+25oC

-55oC
Output Voltage

VOL

VDD = 10V, No Load

1, 2

+25oC, +125oC,
-55oC

50

mV

Output Voltage

VOH

VDD = 5V, No Load

1, 2

+25oC, +125oC,
-55oC

4.95

Output Voltage

VOH

VDD = 10V, No Load

1, 2

+25oC, +125oC,
-55oC

9.95

Output Current (Sink)

IOL5

VDD = 5V, VOUT = 0.4V

1, 2

+125oC

0.36

mA

-55oC

0.64

mA

+125oC

0.9

mA

-55oC

1.6

mA

Output Current (Sink)

Output Current (Sink)

Output Current (Source)

Output Current (Source)

Output Current (Source)

IOL10

IOL15

IOH5A

IOH5B

IOH10

VDD = 10V, VOUT = 0.5V

1, 2

VDD = 15V, VOUT = 1.5V

1, 2

VDD = 5V, VOUT = 4.6V

1, 2

VDD = 5V, VOUT = 2.5V

1, 2

VDD = 10V, VOUT = 9.5V

1, 2

7-782

+125oC

2.4

mA

-55oC

4.2

mA

+125oC

-0.36

mA

-55oC

-0.64

mA

+125oC

-1.15

mA

-55oC

-2.0

mA

+125oC

-0.9

mA

-55oC

-1.6

mA

Specifications CD4027BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER

SYMBOL

Output Current (Source)

IOH15

Input Voltage Low

VIL

CONDITIONS
VDD =15V, VOUT = 13.5V

VDD = 10V, VOH > 9V, VOL < 1V

NOTES

TEMPERATURE

MIN

MAX

UNITS

1, 2

+125oC

-2.4

mA

-55oC

-4.2

mA

+25oC, +125oC,

1, 2

-55oC
Input Voltage High

VIH

Propagation Delay
Clock To Q, Q

TPHL1
TPLH1

Propagation Delay
Set To Q, Reset To Q

TPLH2

Propagation Delay
Set To Q, Reset To Q

TPHL3

Transition Time

Maximum Clock Input


Frequency Toggle Mode
Input TR, TF = 5ns
Minimum Data Setup
Time

Minimum Set or Reset


Pulse Width

VDD = 10V, VOH > 9V, VOL < 1V


VDD = 10V
VDD = 15V

Input Capacitance

+25oC

130

ns

90

ns

130

ns

+25 C
+25 C
+25 C

90

ns

1, 2, 3

+25oC

170

ns

VDD = 15V

1, 2, 3

+25oC

120

ns
ns

1, 2, 3

+25 C

100

VDD = 15V

1, 2, 3

+25oC

80

ns

VDD = 10V

1, 2, 3

+25oC

MHz

VDD = 15V

1, 2, 3

+25oC

12

MHz

VDD = 5V

1, 2, 3

+25oC

200

ns

1, 2, 3

+25oC

75

ns

VDD = 15V

1, 2, 3

+25oC

50

ns

VDD = 5V

1, 2, 3

+25oC

180

ns

VDD = 10V

1, 2, 3

+25oC

80

ns

1, 2, 3

+25oC

50

ns

VDD = 5V

1, 2, 3

+25oC

140

ns

VDD = 10V

1, 2, 3

+25oC

60

ns

1, 2, 3

+25oC

40

ns

1, 2, 3, 4

+25oC

45

VDD = 10V

1, 2, 3, 4

+25oC

VDD = 15V

1, 2, 3, 4

+25oC

1, 2

+25oC

7.5

pF

VDD = 10V

TRCL
TFCL

1, 2, 3

1, 2, 3

VDD = 15V
Clock Input Rise Or Fall
Time (Note 5)

VDD = 10V

FCL

TW

1, 2, 3

VDD = 15V
Minimum Clock Pulse
Width

VDD = 15V

VDD = 10V

TW

+25oC, +125oC,
-55oC

1, 2, 3

VDD = 10V

TTHL
TTLH

TS

1, 2

VDD = 5V

CIN

NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded in a parallel clocked operation, trCL should be made less than or equal to the sum of the fixed propagation delay time at 15pF and the transition time of the output driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current

SYMBOL
IDD

CONDITIONS
VDD = 20V, VIN = VDD or GND

7-783

NOTES

TEMPERATURE

MIN

MAX

UNITS

1, 4

+25oC

7.5

Specifications CD4027BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER

SYMBOL

N Threshold Voltage

VNTH

N Threshold Voltage
Delta

VTN

P Threshold Voltage

VTP

P Threshold Voltage
Delta

VTP

Functional

CONDITIONS

NOTES

TEMPERATURE

MIN

MAX

UNITS

1, 4

+25oC

-2.8

-0.2

VDD = 10V, ISS = -10A

1, 4

+25oC

VSS = 0V, IDD = 10A

1, 4

+25oC

0.2

2.8

1, 4

+25oC

+25oC

VOH >
VDD/2

VOL <
VDD/2

1, 2, 3, 4

+25oC

1.35 x
+25oC
Limit

ns

VDD = 10V, ISS = -10A

VSS = 0V, IDD = 10A


VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND

Propagation Delay Time

TPHL
TPLH

VDD = 5V

3. See Table 2 for +25oC limit.

NOTES: 1. All voltages referenced to device GND.


2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC


PARAMETER
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)

SYMBOL

DELTA LIMIT

IDD

0.2A

IOL5

20% x Pre-Test Reading

IOH5A

20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS


MIL-STD-883
METHOD

GROUP A SUBGROUPS

Initial Test (Pre Burn-In)

100% 5004

1, 7, 9

IDD, IOL5, IOH5A

Interim Test 1 (Post Burn-In)

100% 5004

1, 7, 9

IDD, IOL5, IOH5A

Interim Test 2 (Post Burn-In)

100% 5004

1, 7, 9

IDD, IOL5, IOH5A

100% 5004

1, 7, 9, Deltas

100% 5004

1, 7, 9

CONFORMANCE GROUP

PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
Group B

Subgroup B-5
Subgroup B-6

Group D

READ AND RECORD

IDD, IOL5, IOH5A

100% 5004

1, 7, 9, Deltas

100% 5004

2, 3, 8A, 8B, 10, 11

Sample 5005

1, 2, 3, 7, 8A, 8B, 9, 10, 11

Sample 5005

1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas

Sample 5005

1, 7, 9

Sample 5005

1, 2, 3, 8A, 8B, 9

Subgroups 1, 2, 3, 9, 10, 11

Subgroups 1, 2 3

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

CONFORMANCE GROUPS
Group E Subgroup 2

TEST

READ AND RECORD

MIL-STD-883
METHOD

PRE-IRRAD

POST-IRRAD

PRE-IRRAD

POST-IRRAD

5005

1, 7, 9

Table 4

1, 9

Table 4

7-784

CD4027BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION

OPEN

GROUND

VDD

Static Burn-In 1
Note 1

1, 2, 14, 15

3 - 13

16

Static Burn-In 2
Note 1

1, 2, 14, 15

3 - 7, 9 - 13, 16

Dynamic BurnIn Note 2

4, 7 - 9, 12

5, 6, 10, 11, 16

1, 2, 14, 15

3 - 7, 9 - 13, 16

Irradiation
Note 3

9V -0.5V

50kHz

12, 14, 15

3, 13

25kHz

NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V
2. Each pin except VDD and GND will have a series resistor of 4.75K 5%, VDD = 18V 0.5V
3. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V 0.5V

Logic Diagram
RESET
*4(12)
Q
CL

2(14)

MASTER

*6(10)

*5(11)

CL

p
TG
n

p
TG
n

SLAVE

Q
1(15)

K
CL

CL

SET
*7(9)
CL

CL

CL

p
TG
n

p
TG
n

CL

CL

VDD

* ALL INPUTS ARE

CL

PROTECTED BY
CMOS PROTECTION
NETWORK

*3(13)
CLOCK

LOGIC DIAGRAM AND TRUTH TABLE FOR CD4027BMS (ONE OF TWO IDENTICAL J-K FLIP-FLOPS)
TRUTH TABLE
NEXT STATE

PRESENT STATE
INPUTS

OUTPUT

OUTPUTS
CL*

Logic 1 = High Level


Logic 0 = Low Level

No Change

* = Level change
X = Dont care

7-785

VSS

CD4027BMS

AMBIENT TEMPERATURE (TA) = +25oC

GATE-TO-SOURCE VOLTAGE (VGS) = 15V

25
20
15

10V

10
5

5V
0

10

15

AMBIENT TEMPERATURE (TA) = +25oC

15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V

7.5
5.0
2.5

5V
0

5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 1. TYPICAL OUTPUT LOW (SINK) CURRENT


CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC


GATE-TO-SOURCE VOLTAGE (VGS) = -5V

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)


-15
-10
-5

0
-5
-10
-15

-10V

-20
-25

-15V

AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

DRAIN-TO-SOURCE VOLTAGE (VDS) (V)


-15
-10
-5

FIGURE 2. MINIMUM N OUTPUT LOW (SINK) CURRENT


CHARACTERISTICS

-30

-5

-10V

10

8
6
4

CD = 15pF
CL = 50pF
SUPPLY VOLTAGE
(VDD) = 15V
10V

102

10V

8
6
4

5V

10

8
6
4

AMBIENT TEMPERATURE (TA) = +25oC


INPUT tr = tf = 20ns

102

4 68

4 68

4 68

103
104
105
INPUT FREQUENCY (fI) (Hz)

4 68

106

-15

FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT


CHARACTERISTICS

2
3

-10

-15V

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

DISSIPATION PER DEVICE (PD) (W)

8
6
4

GATE-TO-SOURCE VOLTAGE (VGS) = -5V

FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT


CHARACTERISTICS
104

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

30

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

Typical Performance Characteristics

4 68

AMBIENT TEMPERATURE (TA) = +25oC


250

200
SUPPLY VOLTAGE (VDD) = 5V
150

100

10V

50
15V

107

FIGURE 5. TYPICAL POWER DISSIPATION vs FREQUENCY

20

40
60
80
100
LOAD CAPACITANCE (CL) (pF)

FIGURE 6. TYPICAL PROPAGATION DELAY TIME vs LOAD


CAPACITANCE (CLOCK OR SET TO Q, CLOCK OR
RESET TO Q)

7-786

CD4027BMS

AMBIENT TEMPERATURE (TA) = +25oC


250

CLOCK FREQUENCY (fCL) (MHz)

PROPAGATION DELAY TIME (tPHL, tPLH) (ns)

Typical Performance Characteristics (Continued)

200
SUPPLY VOLTAGE (VDD) = 5V
150

100
10V
15V

50

AMBIENT TEMPERATURE (TA) = +25oC


trl tf = 5ns
CL = 50pF
30
25
20
15
10
5

20

40
60
80
100
LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL PROPAGATION DELAY TIME vs LOAD


CAPACITANCE (SET TO Q, OR RESET TO Q)

10
15
SUPPLY VOLTAGE (VDD) (V)

20

FIGURE 8. TYPICAL MAXIMUM CLOCK FREQUENCY vs


SUPPLY VOLTAGE (TOGGLE MODE)

Chip Dimensions and Pad Layout

Dimensions in parentheses are in millimeters


and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)

METALLIZATION:
PASSIVATION:

Thickness: 11k 14k,

AL.

10.4k - 15.6k, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN


DIE THICKNESS:

0.0198 inches - 0.0218 inches

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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