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ECE 574: Modeling and synthesis of digital systems using Verilog and VHDL

Fall Semester 2015

Design and implementation (in VHDL) of a light sensor and VGA


display to run on the Nexys4DDR board
Report and Signoff due Week 7 (October 15) Preliminary
This project involves the design of a number of interfaces to peripheral devices. It reads a light
sensor ADC using an SPI, and also drives a VGA display monitor. The project also uses the Xilinx
Core Generator (for the DCM) and use of existing IP (Digilent VGA Controller). There are multiple
parts to this project. To be successful will require a good design and debugging approach. Make
multiple simpler projects that you can test and debug separately and then combine them together.

Preliminary:
Modify the simple seven segment display from the tutorial to create a seven_seg module
that can display from "0000" to "FFFF" on the four seven segment displays. The input to
the module should be a 16-bit wide bus, with four bits used to indicate the value to be
displayed on each of the seven segments.
Make this a separate module you will use this module in this and later projects.
Test this out by using the slide-switches to enter various numbers.
Part 1: Light Sensor Interface
Create an SPI interface to be able to read the 8-bits of light sensor information from the
PmodALS module provided.
Use a DCM to create the 4MHz clock required for the ADC SCLK.
o Note: only connect the 100MHz FPGA clock to the DCM (nothing else)
o You will need to use an ODDR2 component to drive the SCLK output (see
example at end of this doc)
Add a period constraint to your UCF to match the Nexys3 board 100MHz clock
frequency.
Use a counter or shift register to create the ADC CS signal.
o Verify the SCLK and CS signals are correct with an oscilloscope.
Use a shift register to read in the 8-bits of ADC data
Display the light sensor value on two of the seven segment displays.
Capture a new light sensor value every 1KHz
Use the other two seven-segment displays to display an incrementing count value (at a
10Hz rate) in decimal from 99 to 00 and repeating.
Capture an SPI ADC 16-bit transfer using an oscilloscope (show the CS, SCLK, and
SDO signals on the same scope capture) and describe and include this in your report.

Part 1:
1

Create a VGA display using the VGA controller provided by Digilent (just the 640 by
480 version) see information at end of this doc.
Use a DCM to create the 25MHz required for the VGA pixel clock.
Use the slide-switches to select and display the following patterns
o Complete blue display
o Complete green display
o A black screen with a white rectangle 10 pixels in from the outside edges (one
pixel wide)
(These should be relatively easy once you start working with the VGA controller
provided by Digilent)

Part 2:
Assume the screen is divided into blocks, with each block 24 pixels high by 32 pixels
wide, and the top left corner block is at block x,y position (0,0) and the bottom right
block is at x,y position (19, 19)
Create a yellow block and place it at a starting position determined by the value of the
slider-switches (use 4 switches for the x position and 4 switches for the y position).
Use four pushbuttons to move the yellow block either up, down, left or right one block at
a time when the pushbutton is pressed (you will need to debounce the pushbutton
switches)
When the yellow block hits the outside of the display it should stop
Display the current position of the yellow block on the seven segment displays in decimal
using two digits for x position and two digits for y position (0000 to 1919)
Part 3:
Read the AD703 Serial Input, Dual 8-bit DAC data sheet
Use the PMOD DA1 Module provided in class
o Just use the first AD7303 and only DAC A (ignore the other 3 DACs)
Implement the DAC SPI interface with a state machine and shift register.
o Confirm its operation using a test bench
Modify the DCM from part 1 to also generate a 10MHz serial clock to the DAC
o You will need to use an ODDR2 component to drive the SCLK output (see
example at end of this doc)
Verify the DAC interface is working by first using a constant value to drive the DAC (use
the slider switches).
Create a set of 16 constant values (in the range 0 to 255) and load the DAC with these
values at a rate of 100KHz. Select the constant values so the resulting waveform will be
an approximation of a 6.25KHz sine wave.
Use an oscilloscope to
o Capture the complete 16-bit transfer using this data (show the SCLK, SYNC, and
DIN lines on the same scope capture) describe this picture in your report.
o Verify the sine wave waveform (take a scope screen capture and include in your
report)
Combine all the parts into one project that you can demo to the TA.

As usual, this is not a complete description make whatever additions or changes you think are
necessary.
You need to include a package in your design with a few constants defined.
Prepare a sign-off sheet and demo your system and write your report before the deadline.

Reference Material
Read the Seven Segment and VGA Port section in the Nexys2 Reference Manual.
Read the Digilent PmodALS Reference Manual and the Texas Instruments ADC081S021 ADC
data sheet.

Read the DAC data sheet and PmodDA1 reference manual from Digilent.
Look at the DCM tutorial
Download the VGA Component Reference Design from Digilent from my website
Download the VGA Component Reference Design from Digilent from my website. This design
is in VHDL. Do NOT modify this code, just instantiate it in your top-level.

------------------------------------------------------------------------- vga_controller_640_60.vhd
------------------------------------------------------------------------- Author : Ulrich Zoltn
-Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------- Software version : Xilinx ISE 7.1.04i
-WebPack
-- Device
: 3s200ft256-4
------------------------------------------------------------------------- This file contains the logic to generate the synchronization signals,
-- horizontal and vertical pixel counter and video disable signal
-- for the 640x480@60Hz resolution.
------------------------------------------------------------------------- Behavioral description
------------------------------------------------------------------------- Please read the following article on the web regarding the
-- vga video timings:
-- http://www.epanorama.net/documents/pc/vga_timing.html
------

This module generates the video synch pulses for the monitor to
enter 640x480@60Hz resolution state. It also provides horizontal
and vertical counters for the currently displayed pixel and a blank
signal that is active when the pixel is not inside the visible screen
and the color outputs should be reset to 0.

ODDR2 to drive the SCLK output to the DAC


------------

ERROR:Place:1205 - This design contains a global buffer instance,


<sclk_buf>, driving the net, <sckk>, that is driving the
following (first 30) non-clock load pins off chip.
< PIN: sclk.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due
to limitations in the global routing. If the design does route there may be
excessive delay or skew on this net. It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1.

You can find a VHDL template (example code) for the clock forwarding circuit from within ISE.
Click on the <lightbulb> icon to bring up the Language Templates pane. From within this
pane, select:
VHDL > Synthesis Constructs > Coding Examples > Misc > Output Clock
Forwarding Using DDR
-- Place this code in the top-level HDL file
-- Before the 'begin' keyword
signal sclk
signal clk_10M
signal clk_10M_inv

: std_logic;
: std_logic; -- from the DCM
: std_logic;

-- Place the following after the 'begin' keyword


Clk_10M_inv <= NOT clk_10M;
-- Clock forwarding circuit using the double data-rate register
-Spartan-3E/3A/6
-- Xilinx HDL Language Template, version 14.7
ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE",
-- Sets output alignment to "NONE", "C0", "C1"
INIT => '0',
-- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC")
-- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q =>
sclk,
-- 1-bit output data to SCLK for DAC
C0 => clk_10M,
-- 1-bit clock input
C1 => clk_10M_inv, -- 1-bit clock input
CE => 1,
-- 1-bit clock enable input
D0 => '0',
-- 1-bit data input (associated with C0)
D1 => '1',
-- 1-bit data input (associated with C1)
R => 0,
-- 1-bit reset input
S => 0
-- 1-bit set input
);

-- End of clock_forward_inst instantiation

From Xilinx UG382 Spartan-6 FPGA Clocking Resources

Grading Guidelines

[50 pts] Implementation


o [50 pts] Design works on board and meets requirements
[20 pts] Source Code VHDL in Appendix
o Code style and comments (well-commented and tab-indented code!)
o Use of case vs. if, spaghetti code vs. structured, etc.
o Recognizable implementation of "standard" elements (for example: state
machines, counters, shift registers, decoders)
o Use of packages and other VHDL code structuring elements (sensible use of
modularity)
o No latches or other synthesis problems
[30 pts] Lab Report
o [5 pts] Brief Introduction / Problem Statement
o [10 pts] General Overview of approach to solution and description and
oscilloscope pictures (include Block and State Diagrams with descriptions)
o [5 pts] FPGA Resource usage (# flip-flops with explanation) and listing and
explanation of warning messages (dont copy all the Xilinx reports just the
relevant sections)
o
[5 pts] Conclusions
Problems faced in implementation
Solutions used to solve problems
Lessons learned from the project
Suggestions for further improvements and extensions
[10 pts] Extra points
o Possible extra points for good additional features or capabilities (need to demo on
board and include description in report)