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OBJECTIVES

To construct a given circuit and obtain its truth table. To obtain the simplified Boolean function of the given circuit by means of a K-map. To design and construct a circuit that implements the simplified Boolean function using a minimum number of NAND gates. To verify that the original circuit and the one derived from the simplified Boolean function produce identical logic level outputs for all possible input combinations.

MATERIALS

Alexan Digital Trainer two 7400 quad two-input NAND gate one 7410 tri three-input NAND gate insulated connecting wires cutter or scissors

**Figure 7-1 Circuit diagram—with pin assignments and logic gate analysis—
**

for the implementation of the original circuit to be simplified

Laboratory Activity No . 7| 2

7400

7410

Figure 7-2. Connection diagram of the circuit in Figure 7-1

PROCEDURE

Figure 7-1 shows the original logic diagram requiring both a 7400 and a 7410 IC. This circuit is constructed on the digital trainer as shown in Figure 7-2, and a truth table is generated based on the circuit’s logic level outputs for all eight possible combinations of the three inputs 𝑥, 𝑦, and 𝑧. The results of this initial set of observations are illustrated in Figure 7-3, and consequently interpreted in Table 7-1. As illustrated in Figure 7-3, LED4 of the data status monitor, which corresponds to the single output of the original logic diagram lights up at four input combinations: 011, 100, 101, and 111. Since the ON state of LED4 represents a logic-1 output, we obtain the resulting truth table depicted in Table 7-1. The four 1’s from the last column of the table can be plotted accordingly in a three-variable K-map as shown in Figure 7-4. The first two 1’s in the second row can be combined to give the two-literal term 𝑥𝑦′. The remaining two 1’s in the third column form two adjacent squares that can be represented by the two-literal term 𝑦𝑧. The simplified function then becomes
𝐹

= 𝑥𝑦 ′ + 𝑦𝑧 .

This simplified function can now be implemented using only a single 7400 quad twoinput NAND gate as shown in Figure 7-5. This new circuit is constructed on the digital trainer as shown in Figure 7-6. Then, after double-checking all pin connections and supplying power to the trainer, the ON-OFF state of LED4 is again monitored for all eight possible input

Laboratory Activity No . 7| 3

combinations. The results of this second set of observations are illustrated in Figure 7-7 and converted into truth values in Table 7-2.

SWITCHES

INPUT S1 S2 S3

DATA STATUS

INPUT

LED1 LED2 LED3

OUT

LED4

0 1 2

D1

**Table 7-1. Truth Table
**

Corresponding to Figure 7-3 INPUT

D2 D3

OUTPUT

IN4

3 4 5 6 7

D1 D2 D3 IN1 IN2 IN3 IN4
𝒙

0 0 0 0 1 1 1 1 𝒚

0 0 1 1 0 0 1 1 𝒛

0 1 0 1 0 1 0 1 𝑭

0 0 0 1 1 1 0 1

**Figure 7-3. Output diagram of the
**

original circuit shown in Figure 7-1

yz x

0 1 00
𝑚

0

01
𝑚

1

11
𝑚

3

10
𝑚

2

1 1 𝒚𝒛 𝑚

4

1 𝑚

5

1 𝑚

7 𝑚

6

0 𝒙𝒚

′

Figure 7-4. K-map

corresponding to Table 7-1

**Figure 7-5 Circuit diagram—with pin assignments and logic gate
**

analysis—for the implementation of 𝐹 = 𝑥𝑦 ′ + 𝑦𝑧 using a single 7400 quad two-input NAND gate

7400

Figure 7-6. Connection diagram of the circuit in Figure 7-5

Laboratory Activity No . 7| 5

RESULTS AND DISCUSSION

SWITCHES

INPUT S1 S2 S3

DATA STATUS

INPUT

LED1 LED2 LED3

OUT

LED4

0 1 2 3 4 5 6 7

D1 D2 D3 IN1 IN2 IN3 IN4

**Table 7-2. Truth Table
**

of 𝐹 = 𝑥𝑦 ′ + 𝑦𝑧 𝒙 0 0 0 0 1 1 1 1 𝒚 0 0 1 1 0 0 1 1 𝒛 0 1 0 1 0 1 0 1 𝒙𝒚′ 0 0 0 0 1 1 0 0 𝒚𝒛 0 0 0 1 0 0 0 1 𝑭 0 0 0 1 1 1 0 1

**Figure 7-7. Output diagram of the
**

simplified circuit 𝐹 = 𝑥𝑦 ′ + 𝑦𝑧

As expected, the circuit derived from the simplified Boolean function 𝐹 = 𝑥𝑦 ′ + 𝑦𝑧 produces exactly the same logic level outputs for all eight possible combinations of the three input variables 𝑥, 𝑦, and 𝑧 . We can further verify this result by generating the (theoretical) truth table for 𝐹 = 𝑥𝑦 ′ + 𝑦𝑧 , as shown in Table 7-2. Again, as expected, the truth values of 𝐹 consist of four 1’s corresponding to the minterms 𝑚3 , 𝑚4 , 𝑚5 , and 𝑚7 . This proves that the original and the simplified logic diagrams shown in Figures 7.1 and 7-5, respectively, implement the same Boolean function and are therefore equivalent.

CONCLUSION

The results of this experiment prove that a complex logic diagram consisting of several gates or ICs can be reduced to a simpler logic diagram that consists of fewer gates or ICs but still produces the same output.

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