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2, APRIL 1989


A 10-bit 5=Msample/s CMOS Two-step

Flash ADC

Ahstruct -A 10-bit, S-Msample/s, two-step flash analog-to-digital converter (ADC) in 1.6-pm CMOS requires 54 kmil* and 350 mW. The fully
differential architecture is based on a resistor string and capacitor-array
structure. A sample-and-hold circuit (S/H) is internal to the architecture,
eliminating the timing requirements that get more severe with increasing
resolution. Monotonicity can be guaranteed with minimal component
matching and comparator offset cancellation. The exponential growth of
area and power with increasing resolution in flash converters makes 10-bit
resolution a brute-force and unfeasible solution. Subranging architectures use as few as 2* - 1 rather than 2 - 1 comparators for large
savings of area and power. Previous two-step architectures were limited by
op-amp gain and settling time requirements. This new architecture eliminates this potential error source by eliminating the op amp. The comparator is critical in the design of a high-speed ADC. By using simple
comparator stage models the optimum number of comparator stages for
the fastest response can be determined. A comparator gain stage uses a
diode-connected MOS transistor load to eliminate the need for commonmode feedback (CMFB) that adds complexity and uses area and power.


HE rapidly growing field of digital video that includes image recognition and hgh-definition television has created the need for inexpensive, high-speed
( > 5 Msamples/s), and moderate-resolution (10 bit)
ADCs. The first video ADCs were expensive hybrids
and later 8-bit monolithic flash converters were made in a
bipolar technology. Now advanced CMOS processes are
able to reach video conversion rates [1]-[5]. Video ADCs
fall into the 8-10-bit resolution and 5-20-Msample/s
conversion ranges. Although 8-bit resolution is acceptable
for video at the consumer level, the next generation of
converters will need 10-bit resolution for high-definition
television because of its increased dynamic range and so
that digital signal processing can be applied at the studio
level. CMOS is preferred for its lower cost and so that in

Manuscript received August 29, 1988; revised December 6, 1988. This

work was supported by the National Science Foundation under Grant
J. Doernberg was with the Electronics Research Laboratory, Department of Electrical Engineering and Computer Sciences, University of
California, Berkeley, CA 94720. He is now with Hewlett-Packard Laboratories, Palo Alto, CA 94304.
P. R. Gray and D. A. Hodges are with the Electronics Research
Laboratory, Department of Electrical Engineering and Computer Scicnces, University of Cahfornia, Berkeley, CA 94720.
EEE Log Number 8826152.
U.S. Patent 4 742 330.

the future the ADC can be integrated into a DSP chip to

make a monolithic image processor.
This paper describes a 10-bit, 5-Msample/s, two-step
flash A/D converter fabricated in a 1.6-pm CMOS process. The new archtecture is based on a resistor string and
capacitor arrays and was developed to overcome the disadvantages of the previous approaches-flash, pipelined, and
classical two-step converters. With minimal capacitor
matchng requirements and comparator offset voltage cancellation, the converter is monotonic. To minimize chargeinjection errors the converter is fully differential. A highspeed comparator archtecture using three comparator
stages was designed to provide a gain of more than 1000,
and a comparison time of less than 10 ns. The total area of
the converter excluding the bonding pads is 54 kmil.
Power dissipation is 350 mW of which 60 mW is dissipated
in the resistor string.
Sections I1 and I11 will examine flash converters and
multistep converters looking at their advantages and disadvantages. The prototype architecture is described in Section IV with error sources analyzed in Section V. The
comparator design is described in Section VI. Section VI1
covers testing and the experimental results.
Flash converters use 2 - 1 comparators and 2 matched
resistors for n-bit resolution. Thus when the resolution
increased by 2 bits from the currently available 8 bits, to
10 bits, the flash converters area and power increase by a
factor of 4. The timing requirements are also four times
more severe. A 4.2-MHz full-scale input changes 3.4 least
significant bits (LSBs)/ns at an 8-bit level. At a 10-bit
level it is 13.5 LSBs/ns. As the die area increases the
propagation delay differences also increase. adding to timing errors. There have been two bipolar 10-bit flash converters reported. Both suffer from large power dissipation
of 2.0 and 3.7 W, large input capacitance of 200 and 300
pF, large device count of 40 000 and 70 000 transistors,
and similarly large areas, 9.2 X 9.8 and 7.0 x 7.0 mm. Even
with state-of-the-art technologies the flash architecture is
clearly not the right approach to use for an inexpensive.
video-rate, 10-bit monolithic ADC.

0018-9200/89/0400-0241$01.00 01989 IEEE



The proposed solutions to the flash converter's drawbacks span a range of multistep converters that include
pipelined, subranging, and classical two-step converters.
The pipelined architecture uses several stages operating
concurrently to achieve a high overall throughput. The
subranging and classical two-step architecture use two
steps and trade a factor of 2 speed reduction for a large
area savings. However, previous pipelined and classical
two-step flash converters have been limited by a combination of op-amp gain and speed, area and power. The new
subrangmg architecture eliminates these problems.
A . Pipelined Architecture

The pipelined architecture uses two or more stages that

each do an A/D conversion and pass a residual voltage on
to the next stage to do another conversion. Each stage
consists of a S/H, ADC, DAC, subtractor and a gain
block. The S/H holds the input during each conversion
cycle. The ADC does a conversion. Then the DAC creates
a quantized version of the input that is subtracted from the
held input. The result of the subtraction is a small residual
voltage that is amplified and passed on to the next stage
for conversion in the next clock cycle. While the next stage
operates on this input, the previous stage takes a new
sample and converts it, thus increasing throughput via
concurrent operation. One conversion is done each clock
period. This, however, is not as fast as the CMOS flash
converter since the flash converter samples the input,
offset cancels, and makes one comparison per period
whereas the pipeline must do a sample and hold, a comparison, a D/A conversion, a subtraction, and an amplification each period. The obvious advantage is the
potentially fast operation gained by stages operating concurrently while the increased resolution is attained by
adding additional stages. Thus the area and power consumption grow linearly with precision. Results show that
9-bit resolution at a 5-Msample/s conversion rate in 3-pm
CMOS 'technology is possible [3].
The most stringent requirements are on the op amps
used in the S/H, subtractor, and gain block. In the first
stage they must settle to their final values to the full
accuracy of the converter in less than one clock period.
The accuracy requirement is lessened by a factor equal to
the interstage gain in the following stages. Unless some
form of correction is added the DAC must match the ADC
or errors can result.


24. NO. 2, APRIL 1989






LSB Latch Bank

and Decoder/Encoder


Fig. 1. Subranging ADC using 2" resistors and two banks of 2"/2 - 1
comparators. MSB comparators determine which segment the input lies
in. Then switches connect the LSB comparators to the resistors in that
segment and the LSB's are determined.

input, and often the digital output code to latter stages for
the next conversion that increases the precision of the
previous result. This continues until the last stage where
the final precision is obtained. The latter stages can share
parts of previous stages, saving area and elimin.ating the
matching requirements between an ADC and a DAC or
two ADC's by using the same precision elements repeatedly. From this starting point specific subranging converter architectures can be described.
When the term "subranging converter" is used it generally refers to a converter of the form in Fig. 1. It consists
of 2" resistors and 2"/2 - 1 comparators, a switch bank,
and a S/H. Although two sets of comparators, latches, and
decoder/encoders are shown for simplicity, only one set is
needed. In the first step the comparators are switched to
points on the resistor string every 2"12 taps apart and the
most significant bits (MSB's) decision is made. When the
resistor interval where the input voltage lies is known, the
other 2"/2 - 1 comparators are switched to all taps in that
range to do the fine or LSB conversion.
For an n-bit ADC this implementation could use 2 " / 2 - 1
rather than 2" - 1 comparators. This represents a large
savings in area and power.
T h s architecture has been implemented at an 8-bit level
[4]. The limitations to extending it to 10 bits are that it
uses two banks of comparators (2"12 and 2"12 - 1) and
encoders. T h s would be a large increase in area and power
and it would require 1024 resistors. In this implementation
there are two resistor strings. One is for the MSB's and one
is for the LSB's. Poor matching between them will lead to
large differential nonlinearities.
C. Classical Two-step Flash ADC

B. Subranging Architectures

Conceptually a subranging converter has two or more

stages that each do a low-resolution conversion but the
final result is much more precise. The first stage does a
coarse A/D conversion. Preceding stages pass reference
voltages, the unknown input or some form of the unknown

The classical two-step flash ADC is also a subranging

converter but operates on a different principle. It is shown
in Fig. 2 and consists of a S/H, MSB ADC, DAC,
subtractor, gain block, and an LSB ADC. The operation is
seen with an accompanying timing diagram. In the first
phase the input is sampled and held. Then the MSB's are












DIA, Subtract & Gain





Fig. 2. (a) Classical two-step flash ADC block diagram limited to

bipolar technology. Limitations include matching the MSB ADC and
DAC transitions otherwise missing codes and nonlinearity may result.
(b) Timing diagram for the classical two-step flash ADC. Although the
four phases are shown as equal length, the subtraction and gain are the
slowest. They are limited by op-amp settling time and limit the conversion rate.

converted. In the third phase the DAC reconstructs the

input which is subtracted from the held input and the
result is amplified. The fourth phase is the second step
where the LSBs are converted.
Currently this archtecture has not been implemented in
CMOS. However, it can achieve 10-bit resolution with a
20-Msample/s conversion rate in a bipolar technology but
at a 900-mW power dissipation [6]. Because of the high
precision required, the converter actually uses two 6-bit
stages and error correction.
D. Potential of Two-step A D C Architectures

The new two-step ADC architecture is based on using

212- 1 rather than 2 - 1 comparators as in a flash converter. This could yield a large savings in area and power
at the expense of two clock cycles rather than one clock
cycle for the conversion.
The main drawbacks to pipelined and classical two-step
converters have been the need for high-speed, high-gain op
amps. The other limitations have been matching ADCs
and DACs to each other and architectures that have
needed 2 matched components. Subranging converters
have used multiple sets of comparator banks and encoders.
The 10-bit converter was bipolar. Only 8 bits were attained
in CMOS [ 5 ] . This implementation was pipelined to improve the conversion rate and uses four banks of comparators rather than the two banks shown in Fig. 1.
What is needed is a subranging architecture that eliminates the op amps, 2 precision matched elements, and
multiple comparator and encoder banks that waste area
and power.
The prototype ADC block diagram is shown in Fig. 3.
I t consists of a S/H, MSB ADC, LSB ADC, two DACs.
and an incrementer. It is quite similar to the classical
two-step ADC except that it has one more DAC and an
incrementer. Note, however, that there are no op amps.

Fig. 3. Prototype subranging ADC block diagram Notice that there arc
no op amps. The timing is similar to that in Fig. 2(b). The ADCs and
DACs share components to eliminate matching requircments among

Power Supply Noise

Charge Injection Errors
Fa%,High-Gam Comparator


Fully Dillcrential Circuils

Fully Dlllercntid Circuils

Multistage Cornparalor

The operation is also similar to that of the classical

two-step ADC. As before, the first ADC converts the
MSBs. Its output is fed directly to one DAC creating a
quantized version of the input. Since the DAC output is
used as a voltage reference for the LSB ADC, the subtraction operation is inherent.
The MSB converters output also goes to an incrementer
and then to a second DAC whose output is the second
voltage reference for the LSB ADC. Since the digital
inputs to the two DACs differ by 1 LSB of the MSB
ADC, the two DAC outputs will encompass the unknown
input. Both of these references are a subset of the voltages
used as references to the MSB ADC hence the term
subranging ADC. With this subranging setup the gain
block can be eliminated. The first ADC finds the range in
whch the input lies and the second subdivides that range
for increased resolution.
Many of the components are shared so that two ADCs
and two DACs are not needed. By using one set of
components in all four blocks the problem of matching
them from block to block is eliminated. A S/H is shown
as a separate block but is merged into the MSB and LSB
ADCs. Lastly. the incrementer is just conceptual and
automatically implemented in hardware.

A . Circuit Design Problem und Solutioris

Table I shows five circuit design problems and the
solution used. First, so that the ADC can be integrated
with a digital signal processor for digital video and imaging, the prototype runs on 5 V. In order to reject power
supply noise and reduce charge injection errors the circuits
are fully differential. To insure monotonicity the comparators are offset canceled. The key to the ADC will be the
comparator design.



MSB Converter





24, NO. 2,







i l l l l L






I 1 1 I




- +

set to


Fig. 4. Prototype converters MSB ADC and DAC. It operates like a

standard CMOS flash converter. The 32-C capacitor is used as part of
an S/H. It is a 5-bit array used for subrangin in the LSB conversion.
The DAC and ADC transitions match eack other since the same
resistor string is used for both.

The DAC and MSB ADC are shown in Fig. 4. The
resistor string, 31 capacitors, 31 comparators, and a latch
bank and binary encoder form the MSB converter. Each
shaded capacitor is actually a binary-weighted capacitor
array that will be used in the second step for the subranging LSBs conversion. It has switches set so that it is just
one capacitor of value 32 C in the first step where it stores
the input voltage minus the comparator offset voltage.
The operation is common to most CMOS flash ADCs.
First, the feedback switch is closed around each comparator storing the comparator offset voltage on the capacitor.
At the same time the capacitor bottom-plate switch is in
the sample position storing the unknown input voltage
on the capacitor. Thus the comparator offset voltage is
canceled and does not cause an error. Next, the feedback
switches are opened and the bottom-plate switch is thrown
to the compare position.
The resulting comparator outputs are in a thermometer
code: ONES up to the comparator whose input is the
resistor-string tap voltage below the unknown input voltage, then ZEROS above the tap that is just below the input
voltage. The comparator outputs are then latched and
encoded to binary.

The LSB ADC is made up of 31 ADC subsections, a
latch bank, and a binary encoder as shown in Fig. 5. The
latch bank, encoder, capacitors, and comparators in each
of the subsections are the same as those used in the MSB
ADC. By using 31, 1-bit output, ADC subsections, each
with its comparator set at 1 of the 31 possible thresholds
between the MSB transitions, a second-step flash decision
is made.
Each LSB ADC subsection consists of the 5-bit capacitor array and comparator, shown shaded, from the MSB
ADC. Thts configuration operates like the classical
McCreary charge-redistribution ADC [ 81. The array capacitors have stored the unknown input voltage and it is
compared to the 31 voltages between V,l and V,,. The
code that the switches are set to is the setting of the
capacitor bottom-plate switches and is the threshold of the
ADC subsection between V,, and Y2:

C. DAC and Loading Compensation

On the left side of Fig. 4 is the 5-bit resistor string and a
two-output analog multiplexer that compose a DAC that
generates V,, and V,, for the LSB ADC. The two-output
analog multiplexer connects V,, to the tap corresponding
to the MSB output code and connects V,, to the next tap
above it. The resistor string is the same one used in the
MSB ADC so the DAC and ADC transitions match exactly and no additional area is required.
Resistor-string matching sets the static integral nonlinearity (INL) but the resistor string has the limitation that
when a dynamic load is applied to it the tap voltages are
perturbed and the INL is degraded [7]. To study thts and

Thus the converter is subranging between the two references.

When used in the usual successive-approximation mode
it takes five cycles or comparisons for a 5-bit conversion.
However, by using 31 subADCs, each preset to one of the
31 codes, a flash decision is made. The differential nonlinearity (DNL) is limited by the capacitor matching and
comparator offset voltage. With only 8-bit capacitor
matchng (easily attainable) and comparator offset cancellation, monotonicity can be guaranteed.







This ratio of the voltages is the ratio of the resistance of

half of the string to the total resistance. Summing the
resistors in each term:




Time (r)


Output 40



2 3 4
Time (T)

If any resistor is assumed to be made up of a mean value

and a standard deviation then R , = R uR and (3) can be
written as


01 2345678910
Number of Stages

PToduct for eaih stage. (c) Time for an-n-st&e comparator to make a
decision. (Output reaches dotted line in Fig. 6(b).) Six stages is optimum but the curve is flat for three to ovcr ten stages.


the error effect the negative sign is taken in the right

denominator term. With these conventions


The main error sources can be put into two categories,

those from the architecture and those from the comparator. The error sources in the architecture are component
matching in the resistor string and the capacitor arrays.
The main comparator-related errors were listed in Section
IV-A and are charge injection from the comparator feedback switches and offset voltage from transistor mismatches in the comparator. They will be described in more
detail in Section VI.
A . Resistor Matching

The resistor string is used in the first-step flash decision.

Thus it sets the integral nonlinearity of the ADC. This can
be seen in Fig. 6(a) where the t h n line is the 10-bit INL
that follows the heavy solid line that is the 5-bit INL of the
MSB's from the first step.
To find the resistor matchng requirement for an n-bit
resistor string with N-bit matching, assume that the resistor values are normally distributed with mean R and
standard deviation uR. Then the sum of the resistors will
also be normally distributed with a mean equal to the sum
of the means and the standard deviation equal to the
square root of the sum of the squares of the standard
deviations of the resistors. The worst error that can be
tolerated is &1/2 LSB at an N-bit level and occurs at the
middle tap [9]. At that tap the ratio of the tap voltage to
Vrcf is

This can be simplified to show that ' J R / R ,the r ~ ~ x i m u ~

mismatch for less than 1/2 LSB error, is:


- 2(fl-1)/2-N


This is where n is the resolution and N is the linearity in

bits. For the case n = N , where n-bit precision is needed
with N-bit accuracy:

uf?- 2(fl-1)/2-fl

= 2-(n+1)/2



F~~ the prototype, 5-bit resolution and IO-bit precision is

needed and u , / ~ is 0.23 percent,
B. Cupucitor Matching
Capacitor array matching consists of two parts. The first
is the matching in each array. The second is matching the
arrays to each other.
The capacitor matching in an array is analogous to the
resistor-string matchmg analysis of the previous section:

For the prototype with 5-bit resolution and precision

needed in the second step uc/C < 12.5 percent.
With this analysis the capacitors mismatch in value
within l a so 68.3 percent of the fabricated single arrays



will have the required matching. However, each working

die needs 31 arrays with all matchmg to within l a .
1. Multiple Capacitor-Array Matching


68.3 percent of the individual arrays will match. Thus for

every l-bit increase in resolution and precision uC/C must
decrease by a factor of 1/a.
To find the equivalent matching for all 31 arrays to
match let k be the probability that one array has the
required matching and that the 31 arrays have the same
68.3-percent chance of all matching:

24, NO. 2 , APRIL 1989

For a single-pole amplifier the gain is the familiar equation:

At at time t = r the gain is 0.63A.

The graph in Fig. 6(a) shows the gain of a latch and a
single-pole amplifier on the y axis as a function of time on
the x axis in units of r . The amplifier gain is assumed to
be 10. It is seen that the amplifier has greater gain than the
latch for time less than 27. A latch is needed to store the
comparator result but preceding it with amplifiers will
speed up the comparison.
A . Optimum Number of Comparator Stages

( k ) 3 1= 0.683.


k = 0.9877. T h s corresponds to 3 . 2 4 ~ .Now rather than

using l-sigma matching, 3.24-sigma matching is required, so uc/C must decrease by 1/3.24. Let m be the
equivalent matching needed:

Substituting (8) for uc/C and simplifying:



2 In (3.24)

In (2)


+ 3.40.


Let there be n gain stages each with gain A . The total

gain is

G = A.


Each stage is assumed to have a gain-bandwidth product

(GBW) that is a constant, but gain can be traded for
bandwidth. Two models and methods will be used to
determine the number of stages needed. The first is a
simple gain-bandwidth product optimization, and the second uses the time response of an n-stage cascade of
single-pole amplifiers. For both models




Thus for 5-bit matching in all 31 arrays the capacitors

need the equivalent of 8.4-bit matching, uc/C G 3.8 percent. This matching is easily attainable.

The comparator design is centered on meeting several
specifications. Comparator gain is usually about 2 as a
rule-of-thumb. This is so that it can amplify a voltage that
is less than 1/2 LSB up to a fraction of the supply voltage
that can then be stored in a latch. Here a gain of 1000 is
The errors from feedback-switch charge injection and
the offset voltage must be less than 1/2 LSB. The charge
injection errors are minimized by using a fully differential
arclutecture, by choosing a small feedback switch, and by
canceling any residual error as shown in Section VI-A-1.
The comparator offset voltage must be less than 1 LSB
to guarantee monotonicity. Tlus is aclueved by storing the
offset voltage on the sampling capacitor during the first
step described in Section IV-B.
The simplest comparator is a positive-feedback latch. It
has a gain that is the ratio Vo,,,/Vin and is et/. The
stage time constant is r , the reciprocal of the bandwidth.
At a time t = T the gain is e.


where r = 1 stage delay (l/stage bandwidth, U,). Then t is

the comparison time:
t = n-stage delay = n r




To minimize the comparison time with respect to the

number of stages dt/dn is set equal to zero and n is
- = 0 -+ n = ln(G).
Exponentiating the result and using (14):

The two important results are that the optimum number of

stages n for the fastest response is n = ln(G) and the gain
per stage, A, is e.
The second method of finding the optimum number of
stages also uses an n-stage cascade of single-pole amplifiers with time constant T and gain A , but solves for the
output voltage Yo,, when a step input applied [lo]:

Fig. 6(b) is plots of (19) for different numbers of stages

and has the percentage of output on the y axis and time in


et d.






0 256 512 768 1023

Output Code


Fig. 7. Three-stage comparator is capacitor coupled to cancel each

stages offset voltage independently. The gain block is based on a
differential pair input and diode-connected load devices that eliminate
the need for CMFB that uses area, power, and time.

units of 7 on the x axis. Since a latch will follow the

amplifiers and the latch has gain, one time constant was
allotted to the latch giving a gain of e. Thus consider the
amplification complete when the output is at l / e of the dc
value shown by the dotted line. Fig. 6(c) has time to reach
l / e of the final value in units of T on the y axis and
number of stages on the x axis.
The fastest response is obtained with six stages but the
curve is flat for three to over ten stages. It is concluded
that three stages is best since it is only 0.637 slower, a
small part of the total conversion cycle, and gives a savings
of 50 percent in comparator area and power.
1. Three-Stage Comparator
Three fully differential comparator stages with feedback
switches and input capacitors are shown in Fig. 7. Below is
a timing diagram for opening the feedback switches. By
closing the feedback loop around each stage independently, the possible instability problem of a three-stage
amplifier with one feedback loop around all three stages is
eliminated. This way each amplifiers offset is stored at its
input. A second advantage is that by implementing the
timing shown in Fig. 7 and developed by Allstot [11] the
charge injection from the first stage can be canceled if the
ADC has an external S/H. When switch FBO opens its
charge injection error is a voltage on capacitors C,,, and
C, and it is amplified by the first stage and stored on
capacitors C,, and C,, before the other feedback switches
are opened. T h s can be repeated with switch FB1 opening
before switch FB2 to cancel its charge injection error, but
t h s is not necessary.
The comparator schematic is shown shaded in Fig. 7.
The stage was designed for a gain of 10 and a 35-MHz
bandwidth. Central in the design was the elimination of
common-mode feedback (CMFB) that has several drawbacks including reduced speed and increased area and
power consumption.
The stage is made up of a differential pair input, current
source, and cascodes to reduce the Miller capacitance at
the input. The loads are diode-connected transistors. They
are resistors so the common-mode output voltage is set by
the bias current and the load resistance. The gain is the

g l 2 640 768 896 1023

Output Code


VS0 -40 ~ 3 -20

0 -10 0
Input Level (dB)

Fig. 8. (a) INL versus output code. INL is limited by resistor-string

loading. Loading compensation reduces the 1NL from 5.8 to 3.0 LSRs.
(b) DNL versus output code. Maximum DNL is 0.6 LSBs and limited
by capacitor matching and uncanceled comparator offset voltage. (c)
SNR versus input level. The maximum SNR is 50 dH obtained using
resistor-string compensation.

input stage transconductance times the output resistance:


This gives a gain of

To increase the gain the input
transistors transconductance is increased by a factor of
by injecting ten times more current into them from
the p-channel current sources, M3 and M4, to give an
overall gain of 10 for the stage.

The ADC prototype was tested in two ways. First, the
INL and DNL were measured with a code density test
[12]. Second, an FFT was run on data collected from a
digitized sine wave and the SNR was computed. The
converter was running at a 5-Msample/s rate. A lowfrequency (50 Hz) input was used rather than the external
S/H needed for the charge-injection cancellation described in Section VI-A-l. compensation voltages were
applied to the resistor-string quarter-point taps for the
SNR test and some of the INL measurements to reduce
the loading effects.
A . Integral Nonlinearity

The INL is shown in Fig. 8(a). On the y axis is the INL

in LSBs at a 10-bit level; on the x axis is the output code.
A layout error has prevented complete testing of the
negative range at a 10-bit level. There are three curves.



24, NO. 2, APRIL 1989

Conversion Rate
Maximum DNL
Maximum INL (With comp.)
Maximum SNR (Wilh comp.)

10 bits
5 Msampleslscc

0.6 LSB


3.0 LSB
50 dB
I .6 pm CMOS

Input Capacitance
Power Dissipation

350 mW

54k mils

dotted line is for an ideal 9-bit converter. About 6 dB

below it is a solid line for the prototype ADC. The
maximum SNR is 50 dB.

D. Die Photo

Mux & Interconnect

I Cap B-P Switch I

C ICornpl Digital

Fig. 9. Die photograph of prototype resistor-string, capacitor-array,

two-step flash CMOS ADC. The die is 260x280 mil2 with 54 kmi12 of
active area. Each horizontal block contains a comparator (Comp),
capacitor array (C), and capacitor bottom-plate switches (Cap B-P
SW). The labeled vertical columns are the resistor string (R), analog
multiplexer and interconnect (Mux and Interconnect),Cap B-P SW, C,
Comp, and digital logic (Digital).

Looking first at the thin solid line, this is the integral

nonlinearity of the 10-bit converter for positive inputs. It
follows the heavy solid line that is the converter doing only
the 5-bit first decision. Thus we would expect the 10-bit
performance to follow this line in the negative range
without the layout error. The maximum INL is 5.8 LSBs.
It is limited by the dynamic loading on the resistor string.
At low conversion rates the INL is limited by the resistor
Next, the heavy dotted line is the INL for a 5-bit first
decision with compensation voltages applied to the resistor
string. The maximum INL is reduced to 3.0 LSBs since
the compensation voltages reduced the loading effect.

Fig. 9 is a die photo of the prototype chip. The horizontal rows in the center and right are for each comparator
and its associated capacitor array and switches. The vertical columns start on the left with the resistor string. To its
right is the interconnect from the resistor-string taps to the
comparator inputs for the MSB first decision and for the
analog multiplexer. In the middle are the capacitor bottom-plate switches. On the right are the capacitor arrays
and comparators. To the far right is the decoder/encoder,
digital logic, and buffers.
The prototype chip is 260 x 280 mil2 with an active area
of 54 kmi12. It was fabricated in a 1.6-pm double-metal
CMOS process.


Table I1 shows the ADCs measured performance characteristics and other key specifications. A 10-bit, 5-Msample/s A/D conversion in CMOS is now possible with a
new two-step flash archtecture based on a resistor string
and capacitor arrays. Key to the design was a three-stage
fully differential comparator.

The authors would like to thank MOSIS for making the

masks and the General Electric Corporation for fabricatA plot of the DNL versus output code under the same ing the chip. They would also like to thank T. Baji for
test conditions as the INL was measured is shown in Fig. work on the converter, J. Pena-Fino1 for help with the
8(b). The output code is on the x axis. Note that it is only layout, L. Rugg for building the test setup, and S. Lewis
for the positive range, codes 512 to 1023. The maximum for helpful discussions.
DNL is 0.6 LSBs. Since the DNL never drops to - 1 LSB
there are no missing codes.

B. Differential Nonlinearity

C. SNR versus Input Level

The SNR data are plotted in Fig. 8(c). SNR in decibels
is on the y axis and input level in decibels is on the x axis.
The conversion rate and input frequency are the same as in
the nonlinearity tests. Since only the positive range is being
tested the converter is being run as a 9-bit ADC. The

[ l ] T. Kumamoto et al., A n &bit high-speed CMOS A/D converter,

IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp. 976-982, Dec.
(21 A. Yukawa, A CMOS 8-bit hgh-speed A/D converter IC, IEEE
J. Solid-State Circuits, vol. SC-20, no. 3 , pp. 775-179 June, 1985.
[ 3 ] S. H. Lewis and P. R. Gray, A pipelined 5 MHz 9b ADC, in
ISSCC Dig.Tech. Papers (New York, NY), Feb. 1987, pp. 210-211.
[4] A. G. F. Dingwall and V. Zazzu, An 8-MHz CMOS subranging
8-bit A/D converter, IEEE J. Solid-state Circuits, vol. SC-20, no.
6, pp. 1138-1143, Dec. 1985.


et ul.: ~ O - B I T~-MSAMPLE/S


T. Matsuura et al., An 8b 20MHz CMOS half-flash A/D converter, in ISSCC Tech. Pupers, Feb. 1988, pp. 220-221.
T. Shimizu. M. Hotta. K. Maio. and S. Ueda. A 10b 20 MHz
two-step parallel ADC with intemal S/H, in ISSCC Dig. Tech.
Pupers, Feb. 1988, pp. ??4-225.
A. G. F. Dingwall, Monllithc expandable 6 bit 20 MHz
CMOS/SOS A/D converter, IEEE J . Solid-Stute Circuits, vol.
SC-14, no. 6. DD. 926-932. Dec. 1979.
J. L. McCreaG, All-MOS ch:!ge
redistribution analog-to-digital
conversion techniques-Part 1, I E E E J . Solid-Stute Circuits, vol.
SC-10, no. 6, pp. 371-379, Dec. 1975.
S. H. Lewis, Video-rate analog-to-digital conversion using
pipelincd architectures, Ph.D. dissertation, Univ. of Calif., ERL
memo USB/ERL M87/90, pp. 88-94, Nov. 18, 1987.
T. Baji, A high-speed, high-precision comparator design for a
10-bit 15 MHz A/D converter, ERL, Univ. of Calif., Berkeley,
Memo. UCB/ERL M85/86, pp. 46-50, Aug. 7, 1985.
D. J. Allstot. A precision variable-supply CMOS comparator,
IEEE J . Solid-State Circuits, vol. SC-17, no. 6, pp. 1080-1087, Dec.
J. Doernbere. H.-S. Lee. and D. A. Hodees. Full-meed testing of
A/D converters. I E E E J . Solid-Stute fircuits, vol: SC-19, no. 6,
pp. 820-827, Dec. 1984.

Joey Doernberg (S82) was born in Los Angeles.

CA, on October 28, 1959. He earned the B.S.
degree with highest honors and the M.S. and
Ph.D. degrees in electrical engineering from the
University of California, Berkeley, in 1981, 1983
and 1988, respectively.
In 1989 he joined Hewlett-Packard Laboratories in Palo Alto, CA, where he is currently doing
research and development on high-speed data
communication links. He is also interested in
analog interface circuits, A/D and D/A converters, and A/D con verter testing.
Dr. Doernberg is a member of Phi Beta Kappa, Eta Kappa Nu, and
Tau Beta Pi

Paul R. Gray (S65-M69-SM76-F81) was born

in Jonesboro, AR, on December 8, 1942. He
received the B.S., M.S., and Ph.D. degrees from
the University of Arizona, Tucson, in 1963, 1965,
and 1969, respectively.
In 1969 he joined the Research and Development Laboratory, Fairfield Semiconductor, Palo
Alto, CA, where he was involved in the application of new technologies for analog integrated
circuits, including power integrated circuits and
data conversion circuits. In 1971 he joined the

Department of Electrical Engineering and Computer Sciences, University
of California, Berkeley, where he is now a Professor. His research
interests during this period have included bipolar and MOS circuit
design, electro-thermal interactions in integrated circuits. device modeling, telecommunications circuits, and analog-digital interfaces in VLSI
systems. He is the co-author of a college textbook on analog integrated
circuits. During year-long industrial leaves of absence from Berkeley. he
served as Project Manager for Telecommunications Filters at Intel Corporation, Santa Clara, CA, in 1977-1978, and as Director of CMOS
Design Engineering at Microlinear Corporation, San Jose, CA, in
1984-1985. At Berkeley he has held several administrative posts including Director of the Electronics Research Laboratory (1985-1986). and
Vice-chairman of the EECS Department for Computer Resources
Dr. Gray has been co-recipient of best-paper awards at the International Solid-state Circuits Conference, the European Solid-state Circuits
Conference, and was co-recipient of the IEEE R. W. G. Baker Prize in
1980, the IEEE Morris K. Liebmann award in 1983, and the IEEE
Circuits and Systems Society Achievement Award in 1987. He served as
editor of the IEEE JOURNAL
CIRCUITSfrom 1977 through
1979, and as Program Chairman of the 1982 International Solid State
Circuits Conference. He currently serves as President of the IEEE SolidState Circuits Council.

David A. Hodges (S59-M65-SM71-F77)

earned the B.E.E. degree at Corncll University.
Ithaca. NY, and the M.S. and Ph.D. degrccs in
electrical engineering at the University of California, Berkeley.
From 1966 to 1970 he worked at Bell Telephone Laboratories, first in the components area
at Murray Hill, NJ, then as Head of the Systems
Elements Research Department at Holmdel. NJ.
He is now a Professor of Electrical Engineering
and ComDuter Sciences at the University of California, Berkeley, where he has been a mcmber of the faculty since 1970.
He has been active in teaching and research on microelectronics technology and design and on communications and computer systems. Since
1984 he has led a research group at Berkeley on computerintegrated manufacturing systems.
Dr. Hodges is founding Editor of the new IEEE TRANSACTIONS ON
He is a former Editor of the IEEE
and a past Chairman of the International Solid-state Circuits Conference. He was co-recipient of the 1983
IEEE Morris N. Liebmann Award. He is a Fellow of the IEEE and a
member of the National Academy of Engineering.