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International Journal of Advanced Engineering Research and Technology (IJAERT) 206

Volume 2 Issue 6, September 2014, ISSN No.: 2348 8190

Design of 1.2Volt, 1GSPS, 2, 3, 4 And 6 Bit Flash ADC Using EIS


Comparator and Fat Tree Encoder
Dharmendra Kumar Gangwar1, Divakar Shahi2, Sh. Nishant Tripathi3,
1,2

M.Tech Student at National Institute of Electronics and Information Technology (NIELIT) Gorakhpur
Scientist-C at National Institute of Electronics and Information Technology (NIELIT) Gorakhpur

ABSTRACT
The simulation result of the 45nm CMOS EIS (Efficient
Inverter scheme) comparator and fat tree encoder circuit
for 2, 3, 4, and 6 bit flash A/D converters are presented
in this paper. Flash A/D converter requires 2n-1
comparators. Each one different from all others depends
on the particular design. The used analog power supply
in this Flash ADC is only 1.2V. Low voltage analog
design is necessary to compile so As to get decreasing
digital supply voltage used for the complete mixedsignal chip. Supply voltages in deep submicron CMOS
technologies decrease due to the short channel effects
and decrease with the technology length. Optimal design
method of Flash ADCs presented in this paper
significantly improves the linearity of the A/D converter
against the CMOS process variation. These 2, 3, 4, and 6
bit Flash ADC consumes .2 watt, .492 watt, .991
watt and 4.556 watt respectively.
Keyword: 45nm, CMOS, EIS, Flash A/Ds, PTM, LTSpice

The following figure-1 shows the output


waveform of the comparators of 2 Bit Flash ADC.

Figure-1 Comparator Output of 2 Bit Flash ADC


2.2 Encoder Output waveform:
2.2.1 1-out-of-N code Output waveform:
The following figure-2 shows the output
waveform of the 1-out-of-N code.

1. INTRODUCTION
A flash Analog to Digital Converter (ADC)
architecture is mainly used for its high-speed conversion
rate application. The latest VLSI design trend for signal
processing system demands high-speed and low power
consumption.
The simulation of Flash ADCs is done in 45nm
PTM CMOS technology using LT-Spice. The transient
analysis of the ADCs is made by giving a ramp input
signal ranging from 562mV to 680 mV for all Flash
ADCs at a 1.2V Power Supply. The digital codes are
obtained correctly for all Flash ADCs as shown in
following figures.

Figure-2 1-out-of-N code of 2 Bit Flash ADC


2.2.2 Fat Tree Encoder Output waveform:

2. 2-BIT FLASH ANALOG TO DIGITAL


CONVERTER

The following figure-3 shows the output


waveform of Fat Tree Encoder.

2.1 Comparator output waveform:

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International Journal of Advanced Engineering Research and Technology (IJAERT) 207


Volume 2 Issue 6, September 2014, ISSN No.: 2348 8190

Figure-3 output of 2 Bit Flash ADC

3. 3-BIT FLASH ANALOG TO DIGITAL


CONVERTER

Figure-5 1-out-of-N code of 3 Bit Flash ADC


3.2.2 Fat Tree Encoder Output waveform:

3.1 Comparator Output waveform:


The following figure-4 shows the output
waveform of the comparators of 3 Bit Flash ADC.

The following
figure-6 shows the output
waveform of Fat Tree Encoder.

Figure-6 output of 3 Bit Flash ADC


Figure-4 Comparator Output of 3 Bit Flash ADC

4. 4-BIT FLASH ANALOG TO DIGITAL


CONVERTER

3.2 Encoder Output waveform:


3.2.1 1-of-n code Output waveform:

4.1 Comparator Output waveform:

The following figure-5 shows the output


waveform of the 1-out-of-N code.

The following figure-7 shows the output


waveform of the comparators of 4 Bit Flash ADC.

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International Journal of Advanced Engineering Research and Technology (IJAERT) 208


Volume 2 Issue 6, September 2014, ISSN No.: 2348 8190

The following figure -9 shows the output


waveform of Fat Tree Encoder.

Figure-9 output of 4 Bit Flash ADC

5. 6-BIT FLASH ANALOG TO DIGITAL


CONVERTER

Figure-7 Comparator Output of 4 Bit Flash ADC


4.2 Encoder Output waveform:

5.1 Comparator Output waveform:

4.2.1 1-out-of-N code Output waveform:

The following figure-10 shows the output


waveform of the comparators of 6 Bit Flash ADC.

The following figure-8 shows the output


waveform of the 1-out-of-N code.

Figure-10 Comparator Output of 6 Bit Flash ADC


5.2 Encoder Output waveform:
5.2.1 1-out-of-N code Output waveform:
Figure-8 1-out-of-N code of 4 Bit Flash ADC
4.2.2 Fat Tree Encoder Output waveform

The following figure-11 shows the output


waveform of the 1-out-of-N code.
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International Journal of Advanced Engineering Research and Technology (IJAERT) 209


Volume 2 Issue 6, September 2014, ISSN No.: 2348 8190

Flash Comparat
ADC -or Unit

Encoder
Unit

Total
Power

Sample/
Sec

2-Bit

166.24nw

34.44nw

200nw

1GSPS

3-Bit

377.13nw

115.02nw

492.15
nw

1GSPS

4-Bit

797.28nw

193.94nw

991.22
nw

1GSPS

6-Bit

3.530w

1.025w

4.555
w

1GSPS

7. CONCLUSION
Figure-11 1-out-of-N code of 6 Bit Flash ADC
5.2.2 Fat Tree Encoder Output waveform:
The following figure-12 shows the output
waveform of Fat Tree Encoder.

Here we have simulated all Flash ADC such as 2


Bit, 3 Bit, 4 Bit, and 6 Bit using LT-Spice. In design of
the EIS TIQ Comparator circuits are with different Wp
and Wn values and simulated in LT-Spice by using PTM
Low Power 45 nm Metal Gate / High-K / StrainedSi,CMOS technology with 1.2V power supply. The
static power consumption in comparator is found to be
negligible and so the total power consumption is reduced
to its minimum level thereby making this CMOS EIS
TIQ comparator acceptable for low power consumption
and high speed Flash ADC.
REFERENCE
[1] Jincheol Yoo, A TIQ Based CMOS Flash ADC for
System on Chip Application, A Thesis in Computer
Sciences and Engineering, .2003
[2] Ali Tangel and Kyusun Choi, The CMOS Inverter
as A Compactor in ADC Design, Analog Integrated
Circuit and Signal Processing, 39 147-155, 2003
[3] S.S. Khot, P.W.Wani, M. S.Sutaone, Shubhang
Tripathi Design Of A 45 M TIQ comparator for High
Speed and Low Power 4-Bit Flash ADC ACEEE Int. J.
On Electrical and Power Engineering Vol.02 No. 01 Feb
2011.

Figure 5.12 output of 6 Bit Flash ADC

[4] Omar Gonzales, Jonathan Yu, Georgekorbes 6- Bit


Analog to Digital Converter Dept. of Electrical
Engineering, Son Jose State University.

6. RESULT
The following Table-6.1 shows the power
dissipation calculation of all Flash ADCs which has been
stated in this paper. Here 1.2 volt power supply and
input signal range 562mv to 680mv is used.

[5] R.Jacob Baker, CMOS Circuit Design, Layout and


Simulation Second Edition Willey IEEE Press 2004.
[6] Meghana Kulkarni, V.Sridhar, G. H. Kulkarni The
Quantized Differential Comparator in Flash Analog to

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International Journal of Advanced Engineering Research and Technology (IJAERT) 210


Volume 2 Issue 6, September 2014, ISSN No.: 2348 8190

Digital Converter Design (IJCNC) Vol.2, No.4, July


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Authors
DHARMENDRA KUMAR GANGWAR received the
B.Tech Degree in
Electronics and Communications
Engineering from Invertis
Institute of Engineering And
Technology Bareilly in 2012.
He is currently working toward
the M.Tech degree in Electronic Design and Technology
in the Department of Electronic Design and Technology,
National Institute of Electronics and Information
Technology (NIELIT) (An Autonomous body of
Department of Electronics & Information Technology,
Government of India) Gorakhpur Centre Gorakhpur273010
dharmendra.gangwar7@gmail.com
DIVAKAR SHAHI received the B.Tech Degree in
Electronics and
Communications Engineering
from IIMT College of
Engineering Greater Noida
in 2012. He is currently working
toward the M.Tech degree in
Electronic Design and Technology in the Department of
Electronic Design and Technology, National Institute of
Electronics and Information Technology (NIELIT) (An
Autonomous body of Department of Electronics &
Information Technology, Government of India)
Gorakhpur Centre, Gorakhpur-273010
divakarshahi05@gmail.com
SH. NISHANT TRIPATHI
nishant@nielit.gov.in
Scientist-'C'
Department of ED&T
National Institute of Electronics
and Information Technology
(NIELIT)(An Autonomous body of Department of
Electronics & Information Technology,
Government of India) Gorakhpur Centre, Gorakhpur273010

[15] Choi, M., & Abidi, A. A. (2001) A 6-b 1.3Gsample/s A/D converter in 0.35-m CMOS, IEEE
Journal of Solid-State Circuits, vol. 36, no. 12, pp. 18471858.

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