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Pin diagram 0f 8086 Microprocessor or The hardware model of 8086

Friday, November 18, 2011 Microprocessor and Assembly Language Programming 2 Comments
Pin
diagram
of
8086 microprocessor
The 8086 is a 16-bit microprocessor intended to be used as the CPU in a microcomputer. The
8086 Microprocessor- Internal Architecture shows the details of internal architecture. Following
figure shows the logical pin diagram of 8086 microprocessor. All the signals can be classified
into six groups: 1. Power supply and frequency signals. 2. Clock signal 3. Address bus. 4. Data
bus. 5.Mode selection. 6. Control and status signals. 7. Externally initiated signals, including
interrupts.

Fig: 8086 and pin diagram
1.

Power supply and frequency signals
Vcc is on pin 40 supplies +5V power supply.
Pin 1 and 20 for ground reference.
2.
Clock signal
Pin 19 for clock input (CLK): an 8086 requires a clock signal from some external, crystalcontrolled clock generator to synchronize internal operations in the processor with maximum
frequencies ranging from 5 MHZ to 10 MHZ.
3. Multiplexed address/data Bus
AD0 through AD15 are used at the start of machine cycle to send out addresses and later in the
machine cycle they are used to send or receive data. (This is also known as multiplexing the
bus.) However, the-low order address bus can be separated from these signals by using a latch.
4. Multiplexed address bus
The 8086 has 4 signal lines A16/S3 through A19/S6. The double mnemonic on these pins
indicates that address bits A16 through A19 are sent out on these lines during the first part of a
machine cycle and the status information, which identifies the type of operation to be done in
that cycle, is sent out on these lines S3 through S6 during a later part of the cycle.
5. Mode selection
The operating mode of the 8086 is determined by the logic level applied to the

MNMX¯¯¯¯¯¯¯¯¯¯
input on pin 33. If pin 33 is asserted high, then the 8086 will function in minimum mode, and
pins 24 through 31 will have the functions shown in parentheses next to the pins i.e.
INTA¯¯¯¯¯¯¯¯¯¯¯¯¯¯,
ALE,
DEN¯¯¯¯¯¯¯¯¯¯¯¯,
DT/R¯¯¯¯,
M/IO¯¯¯¯¯¯,
WR¯¯¯¯¯¯¯¯¯,
HLDA, and HOLD. If the 8086 is in minimum mode in systems, it works as a single
microprocessor on the system buses.
If the
MNMX¯¯¯¯¯¯¯¯¯¯
pin is asserted low, then the 8086 is in maximum mode. In this mode pins 24 through 31 will
have the functions described by the mnemonics next to the pins i.e. QS1, QS0,
S0¯¯¯¯¯¯,
S1¯¯¯¯¯¯,
S2¯¯¯¯¯¯,
LOCK¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯,
RQ¯¯¯¯¯¯¯¯/GT1¯¯¯¯¯¯¯¯¯¯,
and
RQ¯¯¯¯¯¯¯¯/GT0¯¯¯¯¯¯¯¯¯¯.
If the 8086 is in maximum mode in systems, it has two or more microprocessors sharing the
same buses and this mode is called multiprocessor mode.
6. Control and status signal
This group of signals is to identify the nature of the operations. These signals are as follows.
a.
ALE- Address Latch Enable (pin 25): this is a positive going pulse generated every time the
8086 begins an operation (machine cycle).This output signal indicates the availability of the
valid address is on the address/data lines.
b.
RD¯¯¯¯¯¯¯¯
(pin 32) Read: This is read control signal (active low). This signal indicates that the selected I/O or
memory device is to be read and data are available on the data bus.
c.
WR¯¯¯¯¯¯¯¯¯
(pin 29) Write: This is a write control signal (active low). This signal indicates that the data on the
data bus are to be written into a selected memory or I/O location.
d.
M/IO¯¯¯¯¯¯
(Pin 28): when it is high, reading from and writing to a memory location, and if it is low, reading
from and writing to a port.
e.
S0¯¯¯¯¯¯,S1¯¯¯¯¯¯,S2¯¯¯¯¯¯
(pins 26, 27 and 28): these control bus signals are sent out encoded form of data and an external bus
controller device decodes these signals to produce the control bus signals required for a system
which has two or more microprocessors sharing the same buses.

The signal can be used to reset other devices. HLDA (pin 30) Hold Acknowledge: This signal acknowledges the HOLD request. when DEN is low. The microprocessor also has a S/W function. when DTR¯¯¯¯ is low. READY input (pin 22): This signal is used to delay the microprocessor Read or Write cycles until a slow responding peripheral is ready to send or accept data. the address that it will be writing to on AD0 . I/O. This requires an Arithmetic-Logic Unit (ALU) within . it send data out on the data bus and read the data in on the data bus.f. It accomplishes this task via the three-bus system architecture previously discussed. d. g. It must recognize. DTR¯¯¯¯ (pin 27) Data transmit/receive signal: when DTR¯¯¯¯ is high. RESET (pin 21): This signal indicates that the MPU (microprocessor) is being reset. Its job is to generate all system timing signals and synchronize the transfer of data between memory. RAM. and execute program instructions fetched from the memory unit. the microprocessor waits for an integral number of clock cycles until it goes high.e. b. i. HOLD input (pin 31): when the HOLD line is high . or ports. NMI (Nonmaskable interrupt pin 17) and INTR (interrupt pin 18) input :A signal can be applied to one of these inputs to cause the 8086 to interrupt the program it is executing and go execute a specified procedure. and ports. decode.A19. 7. e. and itself. When this signal goes low. Interrupts and Externally initiated signals: a. this signal indicates that a peripheral such as a DMA (DMA Direct memory Access) controller is requesting the use of the address and data buses. DEN¯¯¯¯¯¯¯¯¯¯¯¯ (pin 26) Data Enable signal: it is used to enable bidirectional buffers on the data bus. the 8086 is used to decide the direction in which the buffers are enabled through the DEN the 8086 transmit the data to ROM. RAM. the buffers will allow data to come in from ROM. h. c. Xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxx 8086 CPU ARCHITECTURE The microprocessors functions as the CPU in the stored program model of the digital computer. BHE¯¯¯¯¯¯¯¯¯¯¯¯/S7 (pin 34) Bus high enable: The bus high enable is used to indicate the transfer of data over the higher order data bus If it goes low.

In the 8088. data can also be stored in a memory location or written to an output device. The EU receives program instruction codes and data from the BIU. the BIU data bus path is 8 bits wide versus the 8086's 16-bit data bus. Another difference is that the 8088 instruction queue is four bytes long instead of six. compare. The 8086 CPU is organized as two separate processors.the CPU to perform arithmetic and logical (AND. NOT. including generation of the memory and I/O addresses for the transfer of data between the outside world -outside the CPU. Programs written for the 8086 can be run on the 8088 without any changes. however. By passing the data back to the BIU. and store the results in the general registers. OR. The important point to note. The BIU provides H/W functions. The only difference between an 8088 microprocessor and an 8086 microprocessor is the BIU. is that because the EU is the same for each processor. that isand the EU. the programming instructions are exactly the same for each. It receives and outputs all its data thru the BIU. called the Bus Interface Unit (BIU) and the Execution Unit (EU). executes these instructions. Note that the EU has no connection to the system buses. etc) functions. .

3. consider what happens when the 8086 or 8088 is first started. Depending on the execution time of the first instruction. To see this. causing the selected byte or word to be read into the BIU. 1. While the EU is executing this instruction. 5. the instruction is passed to the queue. This is a first-in. Assuming that the queue is initially empty. The BIU is programmed to fetch a new instruction whenever the queue has room for one (with . 4. the BIU proceeds to fetch a new instruction. Once inside the BIU.FETCH AND EXECUTE Although the 8086/88 still functions as a stored program computer. Register IP is incremented by 1 to prepare for the next instruction fetch. the EU immediately draws this instruction from the queue and begins execution. the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction. 2. organization of the CPU into a separate BIU and EU allows the fetch and execute cycles to overlap. The BIU outputs the contents of the instruction pointer register (IP) onto the address bus. first-out storage register sometimes likened to a "pipeline".

. After waiting for the memory access. There are three conditions that will cause the EU to enter a "wait" mode. The BIU must suspend fetching instructions and output the address of this memory location. the EU can resume executing instruction codes from the queue (and the BIU can resume filling the queue). The EU must wait while the instruction at the jump address is fetched. For example. A subtle advantage to the pipelined architecture should be mentioned. assumes that instructions will always be executed in sequence and thus will be holding the "wrong" instruction codes. Because the next several instructions are usually in the queue. The BIU will thus have to wait for the EU to pull over one or two bytes from the queue before resuming the fetch cycle. One other condition can cause the BIU to suspend fetching instructions. the BIU can access memory at a somewhat "leisurely" pace. The queue. At four cycles per instruction fetch. The first occurs when an instruction requires access to a memory location not in the queue. This occurs during execution of instructions that are slow to execute. The advantage of this pipelined architecture is that the EU can execute instructions almost continually instead of having to wait for the BIU to fetch a new instruction. the queue will be completely filled during the execution of this single instruction.the 8088) or two (with the 8086) additional bytes. however. In this case control is to be transferred to a new (nonsequential) address. This means that slow-mem parts can be used without affecting overall system performance. Note that any bytes presently in the queue must be discarded (they are overwritten). the instruction AAM (ASCII Adjust for Multiplication) requires 83 clock cycles to complete. The second condition occurs when the instruction to be executed is a "jump" instruction. PROGRAMING MODEL As a programmer of the 8086 or 8088 you must become familiar with the various registers in the EU and BIU.

The data registers are normally used for storing temporary results that will be acted on by subsequent instructions. CX. we must first study the way the 8086/88 divides its memory into segments. Six of the flags are status indicators. the 8086/88 always stores words with the high-order byte in the high-order word address. Sometimes a pointer reg will be interpreted as pointing to a memory byte and at other times a memory word. To fully understand these registers. and DF. Register IP could be considered in the previous group. The final group of registers is called the segment group.The data group consists of the accumulator and the BX. Three of the flags can be set or reset directly by the programmer and are used to control the operation of the processor. These are TF. . and DX registers. These registers are used as memory pointers. reflecting properties of the result of the last arithmetic or logical instructions. The pointer and index group are all 16-bit registers (you cannot access the low or high bytes alone). IF. Register IP is physically part of the BIU and not under direct control of the programmer as are the other pointer registers. The 8086/88 has several instructions that can be used to transfer program control to a new memory location based on the state of the flags. As you will see. but this register has only one function -to point to the next instruction to be fetched to the BIU. These registers are used by the BIU to determine the memory address output by the CPU when it is reading or writing from the memory unit. Thus BX refers to the 16-bit base register but BH refers only to the higher 8 bits of this register. Note that each can be accessed as a byte or a word.

The CPU must perform two memory read cycles: one to fetch the low-order byte and a second to fetch the high-order byte. Be sure to note that five hex digits are required to represent a memory address. This division into 64K-byte blocks is an arbitrary but convenient choice. the 8086 reads 16 bits from memory by simultaneously reading an odd-addressed byte and an even-addressed byte. For this reason the 8086 organizes its memory into an evenaddressed bank and an odd-addressed bank. these oddlength instructions can be handled. . and modems. This is because the most significant hex digit increments by 1 with each additional block. there are a couple of good reasons. In effect.288 words can also be visualized. the answer is yes. there is a penalty to be paid. except for the slightly slower performance of the 8088. The 8088 with its 8-bit data bus interfaces to the 1 MB of memory as a single bank. MEMORY MAP Still another view of the 8086/88 memory space could be as 16 64K-byte blocks beginning at hex address 000000h and ending at address 0FFFFFh.or an odd-addressed boundary) two memory read (or write) cycles are performed. terminals. This is especially important with I/O devices such as printers. there is no difference between the two processors.or 8-bit) data. The last few paragraphs apply only to the 8086. you might wonder if all words must begin at an even address. First. or 1'048. As you can see. We have already seen that the 8086/88 has a 20-bit address bus. At first this might seem a disadvantage: Why saddle a 16-bit microprocessor with an 8-bit memory? Actually. With regard to this. Well. Fortunately for the programmer.SEGMENTED MEMORY Even though the 8086 is considered a 16-bit processor. When it is necessary to access a word (whether on an even. many of the 8086's (and 8088's) operation codes are single bytes. allowing it to output 210. As mentioned. That is. all of which are designed to transfer ASCII-encoded (7. address 20000h is 65. 524. However. Second. the 8088 pays a performance penalty with every word access. Other instructions may require anywhere from two to seven bytes. By being able to access individual bytes. different memory addresses. it allows the processor to work on bytes as well as words. This slows down the processor but is transparent to the programmer.576. (it has a 16-bit data bus width) its memory is still thought of in bytes.536 bytes higher in memory than address 10000h.

stack segment. you risk incompatibility with these future products. and extra segment. This type of information is vital to the programmer. Intel has also reserved several locations for future H/W and S/W products. You should realize that the concept of the segmented memory is a unique one. who must know exactly where his or her programs can be safely loaded. This limited the amount of memory available for the program itself and led to disaster if the . SEGMENT REGISTERS Within the 1 MB of memory space the 8086/88 defines four 64K-byte memory blocks called the code segment. it is a guide showing how the system memory is allocated. data segment. Older-generation microprocessors such as the 8-bit 8086 or Z-80 could access only one 64K-byte segment. The code segment holds the program instruction codes. This mean that the programs instruction. Note that some memory locations are marked reserved and others dedicated. If you make use of these memory locations. The dedicated locations are used for processing specific system interrupts and the reset function. like a road map. This is because. data and subroutine stack all had to share the same memory.The diagram is called a memory map. Each of these blocks of memory is used differently by the processor. The extra segment is an extra data segment (often used for shared data). The data segment stores data for the program. The stack segment is used to store interrupt and subroutine return addresses.

it is allowable for all four segments to completely overlap (CS = DS = ES = SS). Indeed. Thus at . Memory locations not defined to be within one of the current segments cannot be accessed by the 8086/88 without first redefining one of the segment registers to include that location. Also note that the four segments need not be defined separately. This is a little "tricky" because the segment registers are only 16 bits wide. DS. The four segment registers (CS. but the memory address is 20 bits wide. and SS) are used to "point" at location 0 (the base address) of each segment. In effect. Another way if saying this is that the low-order hex digit must be 0. ES. this multiplies the segment register contents by 16. The point to note is that the beginning segment address is not arbitrary -it must begin at an address divisible by 16. The BIU takes care of this problem by appending four 0's to the low-order bits of the segment register.stack should happen to overwrite the data or program areas.

This "real" address is called the physical address. which is equal to . instructions to load these registers should be among the first given in any 8086/88 program. as opposed to its "real" address. As we will see. What is the difference between the physical and the logical address? The physical address is 20 bits long and corresponds to the actual binary code output by the BIU on the address bus lines. This can have disastrous results when the data begins to overwrite the subroutine stack area.any given instant a maximum of 256 K (64K * 4) bytes of memory can be utilized. To specify the logical address XXXX in the stack segment. use the convention SS:XXXX. or vice versa. A logical address gives the displacement from the address base of the segment to the desired location within it. This corresponds to the 64K-byte length of the segment. You should also be careful when writing addresses on paper to do so clearly. When two segments overlap it is certainly possible for two different logical addresses to map to the same physical address. As you might imagine. For this reason you must be very careful when segments are allowed to overlap. An address within a segment is called an offset or logical address. LOGICAL AND PHYSICAL ADDRESS Addresses within a segment can range from address 00000h to address 0FFFFh. the contents of the segment registers can only be specified via S/W. The logical address is an offset from location 0 of a given segment. which maps directly anywhere into the 1 MB memory space.

What you must remember is that the program op-codes will be fetched from the code segment. Xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 8086 pin diagram description . independent of the code segment base. This is because the logical addresses always range from 00000h to 0FFFFh. while program data variables will be stored in the data and extra segments. Perhaps the greatest advantage of segmented memory is that programs that reference logical addresses only can be loaded and run anywhere in memory. As we begin writing programs the consequences of these definitions will become clearer. The requirements for writing relocatable programs are that no references be made to physical addresses. Stack operations use registers BP or SP and the stack segment. meaning that they will run at any location in memory. This is done by reloading register DS to point to the new data. and no changes to the segment registers are allowed. An immediate advantage of having separate data and code segments is that one program can work on several different sets of data. Such programs are said to be relocatable.[SS] * 16 + XXXX. ADVANTAGES OF SEGMENTED MEMORY Segmented memory can seem confusing at first.

when MN/MX is low 8086 is configured to support multiprocessor system. MN/MX. A19 /S6. A17/S4 .For minimum mode.In this mode the 8086 is configured to support small single processor system using a few devices that the system bus . a unique processor system with a single 8086 and for Maximum mode a multi processor system with more than one 8086.is an input pin used to select one of this mode .8086 Pin diagram And Explanation The 8086 can operate in two modes these are the minimum mode and maximum mode . The 8086 has a total of 20 address line . A18/S5 . The AD0-AD15 lines are a 16bit multiplexed addressed or data bus.the upper 4 lines are multiplexed with the state signal that is A16/S3 .when MN/MX is high the 8086 operates in minimum mode . During the 1st clock cycle AD0-AD15 are the low order 16Bit adders.During the .

NIM is the non maskable interrupt input. INTA(interrupt acknowledgement signal ) INTA is the interrupt acknowledgment signal .ES and the instruction Queue. INTR is a maskable interrupt input. DT/R(Data Transmit or receive ):is an o/p signal required in system that uses the data bus transceiver ALE is an address latch enable .the 8086 enter a wait state after execution of the wait instruction until a low is Sean on the test pin.S5.S3 and S4 are decoded as follows A17/S4 A16/S3 Function 0 0 Extra Segment 0 1 Stack Segment 1 0 code or No segment 1 1 Data Segment There for the 1st clock cycle of an instruction execution the A17/S4 And A16/S3 pins Specify which Segment register generate the segment portions of the 8086 address BHE/S7 is used as best high enable during the 1st click cycle of an instruction execution .SS. M/IO is an 8086 output signal to distinguish a memory access and i/o access. TEST is an input pin and is only used by the wait instruction .S4.DS.first clock period of a best cycle the entire 20bit address is available on these line.the BHE can be used in conjunction with AD0 to select the memory RD is low when the data is read from memory or I/O location . Is an o/p signal provided by the 8086 and can be used to demultiplexed AD0 to AD15 in to A10 toA15 and D0 to D15. RESET is the system set reset input signal it terminates all the activities it clear PSW. WR is used by the 8086 for performing write memory or write i/o operation .S6 become the status line .IP. During all other clock cycles for memory and i/o operations AD15-AD0 contain the 16 bit data and S3.

A18/S5. S6: .AD15 (I/O): Address Data Bus These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1) and data during T2. and T4 states. T3. During I/O operations these lines are low. 8-bit oriented devices tied to the lower half would normally use A0 to condition chip select functions. T3 and T4 clock cycles.HOLD and HOLDA a high on the HOLD pin indicates that another master is required to take over the S/M bus CLK clock provides the basic timing signals for the 8086 and bus controls . During memory and I/O operations. A0 bit is Low during T1 state when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. status information is available on these lines during T2. These lines are active high and float to tri-state during interrupt acknowledge and local bus "Hold acknowledge". AD0 . A0 is analogous to BHE for the lower byte of the data bus. A16/S3 (0): Address/Status During T1 state these lines are the four most significant address lines for memory operations.S5: The status of the interrupt enable flag bit is updated at the beginning of each cycle. --> Xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Pin Diagram and Pin description of 8086 The following pin function descriptions are for the microprocessor 8086 in either minimum or maximum mode. A17/S4. The status of the flag is indicated through this bus. pins D0-D7. A19/S6.

S3 & S4: Lines are decoded as follows: A17/S4 A16/S3 Function 0 0 Extra segment access 0 1 Stack segment access 1 0 Code segment access 1 1 Data segment access After the first clock cycle of an instruction execution. This pin is Low during T1 state for the first interrupt acknowledge cycle. BHE /S7 (O): Bus High Enable/Status During T1 state theBHE should be used to enable data onto the most significant half of the data bus. RD (O): READ .D8. the 8086 tri-states the S6 pin and thus allows another bus master to take control of the status bus. BHE is Low during T1 state of read. pins D15 . Thus by decoding these lines and using the decoder outputs as chip selects for memory chips. The S7 status information is available during T2. This feature also provides a degree of protection by preventing write operations to one segment from erroneously overlapping into another segment and destroying information in that segment. write and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. During a "Hold acknowledge" clock period. The signal is active Low and floats to 3-state during "hold" state. the A17/S4 and A16/S3 pins specify which segment register generates the segment portion of the 8086 address. Eight-bit oriented devices tied to the upper half of the bus would normally use BHE to control chip select functions. it indicates that 8086 is in control of the bus.When Low. up to 4 Megabytes (one Mega per segment) of memory can be accesses. T3 and T4 states.

5 volts for 50 Micro sec. TEST (I) TEST pin is examined by the "WAIT" instruction. It also initializes CS to FFFF H. the 8086 will fetch its next instruction from the 20 bit physical address FFFF0H. This signal is active HIGH. causes a type-2 interrupt. execution continues. Ready (I) . the reset input must remain below 1. A subroutine is vectored to via the interrupt vector look up table located in system memory. This input is synchronized internally during each clock cycle on the leading edge of CLK. SS. pulse. (Clock generation chip). This signal is active low during T2 and T3 states and the Tw states of any read cycle. It can be internally masked by software resetting the interrupt enable bit INTR is internally synchronized. INTR (I): Interrupt Request It is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. This signal floats to tri-state in "hold acknowledge cycle". IP and flags to all zeros. except after power-on which requires a 50 Micro Sec. Reset (I) Reset causes the processor to immediately terminate its present activity.The Read strobe indicates that the processor is performing a memory or I/O read cycle. Otherwise the processor waits in an "idle" state. This input is internally synchronized. To be recognised. after Vcc has reached the minimum supply voltage of 4. ES. A subroutine is vectored to via an interrupt vector look up table located in system memory. The reset signal to 8086 can be generated by the 8284. A transition from a LOW to HIGH on this pin initiates the interrupt at the end of the current instruction. It causes the 8086 to initialize registers DS. NMI (I): Non-Muskable Interrupt An edge triggered input.5V. Upon removal of the RESET signal from the RESET pin. NMI is not maskable internally by software. If the TEST pin is Low. the signal must be active high for at least four clock cycles. To guarantee reset from powerup.

Since the 8086 does not have on-chip clock generation circuitry. 5MHz and 8MHz respectively. M / IO becomes valid in the T4 state preceding a bus cycle and remains valid until the final T4 of the cycle. RESET and CLK. MN/MX (I): Maximum / Minimum This pin indicates what mode the processor is to operate in. The 8086 READY input is not synchronized. MN/ MX = 1. 8086 and 8086-2 are4MHz. the 8086 itself generates all bus control signals. it accesses I/O and when high it access memory. In maximum mode the three status signals are to be decoded to generate all the bus control signals.Ready is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. In minimum mode. CLK (I): Clock Clock provides the basic timing for the processor and bus controller. WR (O): Write . M/IO floats to 3 . This signal is active HIGH. The corresponding 8 pins function descriptions for maximum mode is explained later. Minimum frequency of 2 MHz is required. The crystal connected to 8284 must have a frequency 3 times the 8086 internal frequency. since the design of 8086 processors incorporates dynamic cells. The 8284 clock generation chip is used to generate READY. The READY signal from memory or I/O is synchronized by the 8284 clock generator to form READY. It is asymmetric with 33% duty cycle to provide optimized internal timing. Correct operation is not guaranteed if the setup and hold times are not met.state OFF during local bus "hold acknowledge". and 8284 clock generator chip must be connected to the 8086 clock pin. M/IO (O): Status line This pin is used to distinguish a memory access or an I/O accesses. The maximum clock frequencies of the 8086-4. Minimum Mode Pins The following 8 pins function descriptions are for the 8086 in minimum mode. When this pin is Low.

depending on the state of the M /IOsignal. HOLD & HLDA (I/O): Hold and Hold Acknowledge Hold indicates that another master is requesting a local bus "HOLD". The processor receiving the "HOLD " request will issue HLDA (HIGH) as an acknowledgement in the middle of the T1-clock cycle. ALE (O): Address Latch Enable ALE is provided by the processor to latch the address into the 8282/8283 address latch. the processor will float the local bus and control lines. It is active LOW during T2. DT/ R is used to control the direction of data flow through the transceiver. It floats to tri-state off during local bus "hold acknowledge". and floats to 3-state OFF during local bus "hold acknowledge ". T3. and T4 of each interrupt acknowledge cycle. It is an active high pulse during T1 of any bus cycle. HOLD must be active HIGH.Indicates that the processor is performing a write memory or write IO cycle. while for a write cycle. 8286/8287 transceiver is used for the data bus. T3 and Tw of any write cycle. ALE signal is never floated. DEN is active LOW during each memory and IO access. DEN (O): Data Enable It is provided as an output enable for the 8286/8287 in a minimum system which uses the transceiver. Maximum Mode The following pins function descriptions are for the 8086/8088 systems in . WR is active for T2. the processor will lower the HLDA and when the processor needs to run another cycle. It will be low beginning with T2 until the middle of T4. It is active LOW. To be acknowledged. After "HOLD" is detected as being Low. it is active from the beginning of T2 until the middle of T4. This signal floats to tri-state off during local bus "hold acknowledge". DT/ R (O): DATA Transmit/Receive In minimum mode. INTA (O): Interrupt Acknowledge It is used as a read strobe for interrupt acknowledge cycles. Simultaneous with the issue of HLDA. it will again drive the local bus and control lines.

Queue status allows external devices like In-circuit Emulators or special instruction set extension co-processors to track the CPU instruction execution.e.processor to perform a specific task and (2) An in-circuit Emulator to trap execution of a specific memory location.1 during T3 or Tw (when ready is inactive). Any change by S2. This mechanism allows (1) A processor to detect execution of a ESCAPE instruction which directs the co. S2 S1 S0 Characteristics 0 0 0 Interrupt acknowledge 0 0 1 Read I/O port 0 1 0 Write I/O port 0 1 1 Halt 1 0 0 Code access1 0 1 Read memory 1 1 0 Write memory 1 1 1 Passive State Table 3 QS0. MN/MX = 0). The condition of queue status is shown in table 4. the queue status is presented each CPU clock cycle and is not related to the bus cycle activity. T1 and T2 states and is returned to passive state (1. S0 during T4 is used to indicate the beginning of a bus cycle. QS1 QS1 Characteristics .1. Since instructions are executed from the 8086 internal queue. QS1 provide status to allow external tracking of the internal 8086 instruction queue. QS1 (O): Queue – Status Queue Status is valid during the clock cycle after which the queue operation is performed. QS0. Only the pins which are unique to maximum mode are described below. S1. S1. S0 (O): Status Pins These pins are active during T4. These status lines are encoded as shown in table 3.. S2.maximum mode (i. These are used by the 8288 bus controller to generate all memory and I/O operation) access control signals.

Register is any register and memory GT0 . The LOCK signal is activated by the "LOCK" prefix instruction and remains active until the completion of the instruction. RQ/GT0 and RQ/GT1 (I/O): Request/Grant These pins are used by other processors in a multi processor organization. Memory . Hence they may be left un-connected. This signal is active Low and floats to tri-state OFF during 'hold acknowledge'. is the address of the semaphore. Example: LOCK XCHG reg. not to gain control of the system bus while LOCK is active Low. Each pin is bi-directional and has an internal pull up resistors.. Local bus masters of other processors force the processor to release the local bus at the end of the processors current bus cycle. .0 0 No operation 0 1 First byte of opcode from queue 1 0 Empty the queue 1 1 Subsequent byte from queue Table 4 LOCK (O) It indicates to another system bus master.