You are on page 1of 54

Design of a Fully On-Chip LDO with Improved

Transient Response for Analog Subsystems
Submitted in partial fulfillment of the requirements
of the degree of

Master of Technology
in

VLSI System Design
By

Saurabh Dixit
Roll No: 124570
Supervisor

Dr. Patri Sreehari Rao
Associate Professor

Department of Electronics and Communication Engineering
NATIONAL INSTITUTE OF TECHNOLOGY
WARANGAL - 506 004
2014

Dissertation Approval for M. Tech.
This Project Work entitled Design of a Fully On-Chip LDO with Improved Transient
Response for Analog Subsystems by Saurabh Dixit is approved for the degree of Master of
Technology in VLSI System Design.

Examiners
_________________________
_________________________
_________________________

Supervisor
Dr. Patri Sreehari Rao
Associate Professor

Chairman
Prof. N.V.S.N. Sarma

Date: ____________
Place: ___________

Declaration
I declare that this written submission represents my ideas in my own words
and where others ideas or words have been included; I have adequately
cited and referenced the original sources. I also declare that I have adhered
to all principles of academic honesty and integrity and have not
misrepresented or fabricated or falsified any idea/data/fact/source in my
submission. I understand that any violation of the above will be cause for
disciplinary action of the institute and can also evoke penal action from the
sources which have thus not been properly cited or from whom proper
permission has not been taken when needed.

_____________________
(Signature)
_____________________
(Name of the student)
_____________________
(Roll No.)
Date: ___________

ii

Abstract
Modern power management System-on-a-Chip (SoC) design demands for fully
integrated solutions in order to decrease certain costly features such as the total chip area and
the power consumption while maintaining or increasing the fast transient response to signal
variations. Low-Dropout (LDO) voltage regulators, as power management devices, must
comply with these recent technological and industrial trends.

An ultra low power capless low-dropout voltage regulator with resistive feedback
network and a gain enhanced feed forward path compensation strategy is proposed. The
feedforward path used enhances the fast load and line LDO transient responses.

The designed LDO is for 1.2V output voltage and full load current of 100mA with a
load capacitance of 100pF, has a dropout voltage of .2V, quiescent current of 69 µA. The
transient response is improved using the fast feed forward path and the compensation
capacitor. Reference voltage is generated by using an accurate band gap reference circuit
(.8V).

iii

Contents
Abstract ........................................................................................................................ iii
List of Figures .............................................................................................................. vi
List of Tables ............................................................................................................... vii
Chapter 1 Introduction .................................................................................................1
1.1 Role of regulators in power management ......................................................... 1
1.2 External v/s Internal Compensation ................................................................. 3
1.3 Internal Compensation ...................................................................................... 4
1.4 Problem Definition ........................................................................................... 4
1.5 Motivation ........................................................................................................ 5
1.6 Organisation of the Report ............................................................................... 5

Chapter 2 Review of Literature ...................................................................................6
2.1 Capacitor-less LDO voltage regulator .............................................................. 6
2.2 State of the art ................................................................................................... 7
2.2.1 Slew-Rate Enhancement Compensation ................................................. 8
2.2.2 Buffered Flipped Voltage Follower Compensation ................................ 9
2.2.3 Reversed Nested Miller Compensation................................................. 10
2.2.4 Q-Reduction Compensation .................................................................. 11
2.2.5 Pole-Zero Cancellation Compensation ................................................. 12
2.2.6 Multipath Miller Zero cancellation compensation (MMZCC) ............. 12
2.2.7 Gain-Enhanced feed-Forward path compensation (GFPC) .................. 13

Chapter 3 LDO Characterisation ..............................................................................15
3.1 Conventional LDO topology .......................................................................... 15
3.2 Pass Device ..................................................................................................... 17
3.3 Error Amplifier ............................................................................................... 18
3.4 Comparator ..................................................................................................... 20
3.5 Band Gap Reference ....................................................................................... 24
3.6 Low Dropout Regulator Characterization ...................................................... 25
iv

35 5......................... 26 3...............................................................2 Future Scope .... 41 6....................................6 PSRR ........................................................................................................................... 38 5..........2 Dropout Voltage ................................................... 26 3.......2 Transient response Simulations ................................................................................................................................................................41 6........................................................1 Overview ..................... 36 5...........4 PSR simulations....................................................................................... 26 3...................................................................43 Acknowledgements ........................5 Error Amplifier Design....... 40 Chapter 6 Conclusions ................ 26 3...... 26 3...........................4 Settling Time ..... 34 Chapter 5 Results and Discussion ...............................46 v .......................28 4............................................................ 28 4....................................................................3 Line and Load Regulation ......... 41 Literature Cited ...........6.......................................................................................7 LDO Specifications ......2 Pass Transistor Design .................................................................................... 35 5.........................6 Comparison with the Previous works .....6......................................................................... 39 5....................................................................................................... 27 Chapter 4 Design and Implementation................................1 Conclusion ............... 28 4...............6...3 Load regulation simulation ...............................................................................................5 Band Gap Reference TC simulation ...............................................................................................5 Loop Gain ........................6.....................4 Band Gap Reference Design .............................................................................................................................................1 Peak Overshoot and Undershoot .1 Loop Gain Simulations ................................................................. 31 4...........................................................3............... 30 4......................... 25 3.. 38 5......................................................6...................3 Feedback Resistor Design ......................................................6........

2............................. 4......2 Buffered flipped voltage follower topology... 9 Fig.................... 10 Fig.. ...................... 29 Fig...............................................3 Load transient response plot for settling time measurement... ........................ 22 Fig.. 19 Fig....5 Power Supply Rejection plot............................................................ . 8 Fig..........................................3 Example of Preamplifier and latch.............2 Load transient response plot for load varying from 0 to 100mA (rise time of 1µs).....................................................................1 Schematic diagram of the proposed capless LDO regulator........................................ 3..... 2 Fig.................... ......... 13 Fig........6 Plot for Temperature Coefficient over temperature range -40 to 80 °C.. 2................. ......................................4 Load regulation plot ......................... ............ 2......................................... 38 Fig.....7 GFPC topology. .. 2.... 4.... ...............................................................5 Band gap reference circuit with curvature compensation..1 Slew rate enhancement topology.....................List of Figures Fig....... 3...........3 Feedback resistor network design................... .6 Principle of BGR.............. 16 Fig...............................3 Reverse Nested Miller Compensation Topology...............1 Loop gain and Loop phase plots................................ considering the temperature and discharge rate to be constant. 2................................... 13 Fig................. 5.......................................... ............................................................2 Error amplifier topology used in the proposed LDO design [2]............... ............................ 3......4 Q-Reduction Compensation Topology........ 23 Fig...... 1..... ...e...... . ......................................... ... 5.. .............6 MMZCC topology............................... .........................4 An improved Preamplifier....................5 Pole-Zero Cancellation Compensation Topology......... 4............ 32 Fig.............................. 3.. 39 Fig......................1 Typical cell (i............ 29 Fig........... 22 Fig.......2 Pass Transistor design................ 25 Fig. ... 5........................................................ 31 Fig. 11 Fig.......... ...... 2.... Nickel-Metal Hydride) voltage discharge curve over load..................5 Comparator topology used as the feed forward path......... 37 Fig.............................................................................................. 4................................................................................. 3.. 39 vi .. 5... 5......... 4............................................... 5.. 37 Fig......1 Conventional LDO topology....... ... 36 Fig. 2. 3........... 33 Fig. . 12 Fig........................4 Schematic of Band Gap Reference Circuit.........................................

.......... 18 Table 3............................List of Tables Table 3.. 17 Table 3. ............. 27 Table 5.... 40 vii .....1 Comparison with the recent reported prior-art results.. .............................................................................................................2 Comparison of Pass element structures ..........1 LDO Parameters.................................................................................3 LDO Specifications.....................................................

Hence an LDO.1 Role of regulators in power management LDO's have become an essential part of many battery powered systems. and loadindependent voltages. and other off-line supplies incur substantial voltage and current variations across time and over a wide range of operating conditions. is in a great demand. Supplying and conditioning power are the most fundamental functions of an electrical system. be it a cellular phone. Area is one of the biggest issues in portable devices. The fact is transformers. the end results of which are undesired voltage droops and frequency spurs where only a dc component should exist. accurate. and cannot fully perform its functions without a stable supply. These rapidly changing loads cause transient excursions in the supposedly noise-free supply. cannot sustain itself without energy. A loading application. constant.Chapter 1 Introduction 1. They are normally noisy and jittery not only because of their inherent nature but also because highpower switching circuits like central-processing units (CPUs) and digital signal-processing (DSP) circuits usually load it. attenuating these ill-fated fluctuations to lower and more acceptable levels. The role of the voltage regulator is to convert these unpredictable and noisy supplies to stable. or wireless sensor node. generators. batteries. such as music players. . which is fully-integrated with no external capacitors. pager.

its ability to respond quickly. which implies an LDO in the mobile phone should use extremely low battery power. which include SoC. it has battery power as its only source. Not responding quickly to one of these load-current transitions (i. which is an important part of mobile phones. as a composition of cells. which can last a long time only if the LDO dissipates extremely low power. the voltage supplied by a single cell is variable by nature. The requirement is more stringent and acute in emergent state-of-the-art technologies whose susceptibility to breakdown voltages can be less than 2 V. This is only possible when the LDO uses extremely low quiescent current. considering the temperature and discharge rate to be constant. demanding both high-power and fast-response times in short consecutive bursts. The growing demand for space-efficient.. system-in-package (SiP).e. A system-on-chip (SoC) solution.1 Typical cell (i. Thus. Furthermore as can be observed in Fig. determines the magnitude and extent of these transient variations. Regulators also protect and filter integrated circuits (ICs) from exposure to voltages exceeding junction-breakdown levels. drives process 2 . also inherits this characteristic which makes this an important issue in power management design. Once implanted in a body. 1. Nickel-Metal Hydride) voltage discharge curve over load. The important issue with any battery powered system is the power consumption. load dumps) forces storage capacitors to supply the full load and subsequently suffer considerable transient fluctuations in the supply. and system-on-package (SoP) implementations.1. incorporates numerous functions. for instance. Long battery life is also important in many implantable electronic devices.e.The regulation function is especially important in high-performance applications where systems are increasingly more integrated and complex. that is. A real-time clock. requires an extremely long battery life. many of which switch simultaneously with the clock. Fig. single-chip solutions. The bandwidth performance of the regulator. such as pacemakers. 1. any battery.

extend good low-frequency PSR performance to higher frequencies. however. generate and regulate accurate and stable output voltages that are impervious to variations in the input supply. necessarily pull parasitic poles to lower frequencies. the presence of ZESR and pB extends f0dB and decreases the number of decades the loop gain can drop at 20 dB per decade from its lowfrequency value. however. 3 . increasing both loop-gain and bandwidth under low quiescent-current restrictions compromises stability. the maximum voltage an IC can sustain before the onset of a breakdown failure declines with decreasing dimensions and pitch because as the component density increases. increase the regulator’s ability to suppress fast and high-power load dumps and high pA frequencies. Low quiescent currents.5–1 MHz . on the other. limiting the extent to which f0dB should increase to maintain stability. limited load. Unfortunately. especially when considering the error amplifier must drive the parasitic capacitance the necessarily large power pass device presents. References. battery-powered solutions. The costs of on chip integration. references do not supply substantial dc currents. are lower output power and more stringent stability constraints. 1. its total load-current reach is still relatively low. which results in relatively low loop gains when compared to standard op amps.technologies to finer photolithographic and metal-pitch dimensions. which explains why loop gains normally fall below 50–60 dB and nominal unity-gain frequencies below 0. like regulators. Unlike regulators. however. irrespective of the compensation strategy.2 External v/s Internal Compensation The overriding advantages of externally compensated regulators are high output capacitance CO and high error-amplifier bandwidth pA. more easily conforming to the total on-chip integration demands of state-of-the-art portable.and line-regulation performance. and various operating conditions. isolation barriers deteriorate. on one hand. references supply up to 1 mA and regulators from 5 mA to several amps. In practice. Therefore. as output pole PO has a tendency to migrate to lower frequencies during light loading conditions. Maintaining pA at high frequencies to guarantee stable operating conditions. High CO values. Although a good reference may shunt positive and negative noise currents. when considering extended battery-life operation. generally speaking. and by translation. To aggravate matters. is challenging. loading environment. Internally compensated circuits reap the integration benefits of lower output capacitances.

the challenge in designing these point-of-load (PoL) regulators is the unavailability of off-chip capacitors. 4 . Low-dropout performance in dedicated on-chip supplies. Having no external pad or pin to rely on. using this argument to ease dropout requirements is important because higher dropout n-type power devices outperform their lower dropout p-type counterparts in speed and consequently in onchip capacitance silicon-area requirements. may sometimes constrain dropout voltages to low values.3 Internal Compensation The need for higher power levels and quicker response times are as imminent as the demand for higher integration. 1. is not always a requirement because the power dissipated by the rest of the system. as it turns out. on average. Fortunately. The LDO should be suitable to power analog subsystems utilizing very low quiescent current. by the way. the lower power levels these targeted loads demand (and their smaller large-signal changes in load) offset some of the expense (i. reducing.4 Problem Definition The idea is to design a Fully On-chip capacitorless Low Dropout Regulator having fast transient response. though. like when one switching regulator supplies the entire IC and its output is already low to mitigate the losses associated with the high-power sectors of the system. The designed LDO should be stable for the entire range of load variation i. often overwhelms that of the particular load in question. 0 to 100mA. If other considerations allow. as a result.e. as lower capacitances may now satisfy the relatively modest needs of a lighter load. Dedicated on-chip regulators help in this respect because they decouple the otherwise common noise from sensitive loads.1. Headroom.. silicon real estate) associated with on-chip capacitors. the signal-to-noise-ratio (SNR) performance of sensitive analog electronics attached to that supply. The fact is packing more features into a single IC introduces uncorrelated noise into the supply. The LDO should provide constant output voltage with high load regulation. which is where internal compensation schemes thrive.e.

Second chapter deals with literature survey on LDO regulators. Simulation results of the LDO are given in chapter 5. Chapter 6 discusses the conclusion and the future scope for this work.5 Motivation Knowing that the market demand for consumer electronics is growing exponentially the electronic components used in the fabrication of these electronic devices will also grow exponentially so ultimately this demand will also fall over the basic electronic components such as the LDOs. The motivation of this dissertation is to better understand the compensation techniques to enhance the transient characteristics and to propose an LDO compensation technique based on a new multi-path feed forward topology. Gain Enhanced Feed Forward Path Compensation.1. Chapter 4 deals with design and implementation of the LDO. High-performance ultra low power LDOs are part of the response to this emerging need of efficient and robust electronic components. many researchers are proposing different topologies with different compensation techniques. Third chapter deals with characterization of LDO. 5 . Concerning LDOs. 1.6 Organisation of the Report This report is started with the introduction of power management.

Removing the large capacitor from the conventional LDO and replacing it by a smaller one in the range of ten to hundreds of picofarad [10]. its high output impedance raises instability issues. removing the large capacitor leads to other constraints of the LDO responses and performance. some output filtering properties are . than the open loop Unit Gain Frequency (UGF). large in SoC context.Chapter 2 Review of Literature 2. 9]. With the aforementioned replacement. The conventional voltage regulation has the advantage of lower voltage operation and higher power efficiency. To assure a satisfactory transient response it requires an output capacitor in the microfarad range. Furthermore. However. if the pole created by this smaller capacitor is far higher. This large capacitor creates a low frequency pole which becomes dominant and severely slows down the LDO dynamic behaviour [8. frequency wise. a higher close loop bandwidth is achieved which is very advantageous. On the other hand. a more suitable LDO is achieved according to modern design trends.1 Capacitor-less LDO voltage regulator Capacitor-less LDOs. This poses a problem and contradicts the modern design trends. are an alternative to the conventional LDO voltage regulator that aim to circumvent some of the non-desirable characteristics of the latter voltage regulator. easily implemented on-chip.

considering the same input signals for both the conventional and capless LDO. To adapt this capless topology and improve it dynamically. many researchers have been studying different compensation topologies and techniques for LDO stabilization without the large external capacitor. a frequency compensation technique is required to shift the poles and zero back and forth.lost. seen from its output. A brief analysis is also presented for each technique and their advantages and disadvantages are also pointed out. or voltage. the LDO. a more attractive implementation of LDOs for SoC applications. All of the presented strategies rely on at least one sensing loop of the ratio of output current. The small capacitor acts as a charge source during fast transients as well but in a much smaller scale. a fewer number of input/output pads are required and thus the total silicon area of the LDO can be minimized while maintaining the desired LDO responses. therefore the transient responses of the LDO degrade. when possible. Capacitorless LDOs. The sensed parameter is then fed-back to the error amplifier. being set usually by the error amplifier or buffer connected to the pass device gate. also known as capless LDOs. As this pole is now located in higher frequencies. in other words. by comparison to the circuit response with the larger output capacitor. The pole set by the smaller capacitor is no longer the dominant one. The lower oscillations on the conventional LDO output voltage are now higher oscillations in the capless LDO output voltage. 7 . are a step forward in the LDO evolution in a way that less materials are used.2 State of the art Since high-performance low power LDOs are growing in demand and popularity among mixed-signal system designers. The dominant pole now depends on each topology. is no longer a stable system. are presented in this section. The system stability will be regained as soon as the dominant pole and zero are shifted back to locations well below the UGF and the nondominant poles are shifted forth to locations well beyond the UGF. 2. the response of LDOs without the large external capacitor. The most recent compensations techniques and strategies to stabilize and improve the capacitorless LDO responses.

1 Slew rate enhancement topology Note that VG is the pass device’s gate voltage. The slew-rate enhancement compensation circuit. Fig. implements a technique that provides the necessary dynamic current to quickly charge and discharge the gate capacitance of the pass device. The dynamic current. 8 . supplied by the enhancement circuit.1 Slew-Rate Enhancement Compensation For LDO designers. then the driving circuitry is enabled acting on the pass device accordingly to the output node voltage detection. improving its transient response. The core of this technique is the sensing circuit which must be able to detect and act on signal variations. it is a well known fact that the slew-rate at the gate of the pass device limits the load transient response of the regulator [11]. In Fig. If any. In order to maintain the low overall consumption and high efficiency of the LDO.1 the sensing circuitry adopts a voltage detection method based on capacitive coupling and is responsible for tapping the output node voltage and detect undershoot and overshoot signal variations. this transient should be as narrower as possible and the slew-rate enhancement circuitry should be completely turned off in steady state. used to overcome this issue. Slew-Rate (SR) enhancement compensation involves two types of electronic circuits: the sensing circuit and the driving circuit. 2.2.2. C1 and R1 implement a high-pass circuit responsible for the output signal variation detection. 2. boosts the response of the pass device to signal variation but also incurs in a temporary increase of quiescent current.

through a voltage follower buffer. VCTRL holds relatively constant over time as it follows the Band Gap output voltage. provides a large driving force at the gate of the pass device and boosts the loop gain in order to improve load regulation [12]. MS has a key role in the aforementioned vantages. The topology in Fig. and by Vgs (MB) which are independent of the uncertain loading conditions. sufficient conditions to stabilize the LDO.2. The minimum loading constraint is therefore inexistent.2 combines the best merits of the two referred compensations. The drain voltage of MC is determined by the voltage biasing at the gate of transistor. 2.2 Buffered Flipped Voltage Follower Compensation Hua Chen and Ka Nang Leung proposed a buffered flipped voltage follower study based on a single transistor-control LDO. The SR issue was also improved by the push pull output stage [8]. MB. MS is responsible for reducing the impedance seen at the pass device’s gate and for boosting the loop gain of the LDO. 2. With this topology and the restricted setting of parameters.2 Buffered flipped voltage follower topology. Fig. It alleviates the minimum loading requirements of the basic flipped voltage follower LDO. Vref. a 20 to 9 . not present in Fig. Moreover. 2. This technique was built and supported by other previous published studies on flipped voltage followers such as the cascaded and level shifted flipped voltage follower. As to the VB constraints. 2.2.2 achieving improved load regulation results.2. the biasing voltage cannot be set to low or the IN transistor will enter the linear region and cannot be set to high or MB transistor will enter the linear region. others introduced the dynamic biasing technique to the topology present in the Fig.

2.3 Reverse Nested Miller Compensation Topology. and finally the inherent bandwidth improvement due to the fact that the inner compensation capacitor. The major differences between these two topologies and the one presented in Fig. Fig. 2.2. the second stage Operational Transconductance Amplifier (OTA). which is the only inverting one. All these techniques require a 500 pF capacitor at the output node for stability purposes which for low power environment is not ideal. bandwidth and slew-rate trade-offs take place [13]. On the other hand. does not load from the output node. 10 . Reversed active feedback frequency compensation and reversed nested Miller compensation with nulling resistor are two evolutions of the topology shown in Fig.3 represents a Reversed Nested Miller Compensation. 2.3 and operate with the same principles already introduced. 2. Fig.3 Reversed Nested Miller Compensation Nested Miller compensation topologies are usually a three stage amplifier topologies that exploits feedback loops and Miller effects through capacitor compensation use. which for ultra low-power applications is not ideal. 2.40 µA quiescent current is easily achieved.3 are the feedback paths which include transconductance blocks along with passive components. CC2. This technique achieves the desired phase margin and required transient response. The stability is achieved by splitting the low frequency poles in the frequency domain by using compensation capacitors CC1 and CC2 in the feedback loop.

Cm1. the second stage is a non-inverting gain stage and finally the pass device as the third stage.rail push-pull stage that forces the pass device to respond more quickly to signal variations. The second stage is a rail-to. With this technique higher values of phase margin are achieved for a given bandwidth. Q-Reduction technique usually achieves higher bandwidths than the other techniques presented for a given low quiescent current. to stabilize the LDO regulator. A new compensation is shown in Fig. The current buffer in the first stage together with the feed-forward capacitor has a crucial role reducing the Q value of the non-dominant poles.4 Q-Reduction Compensation Topology. The M3 transistor is a low transconductance transistor that is necessary to reduce the Q values of the poles. This topology uses a Miller compensation capacitor. Fig. higher Q values and locations closer the UGF [14]. 2. Cgd. 11 . The gate capacitance will be charged/discharged more quickly further improving the transient response of the LDO. as input stage. The first stage is the differential amplifier.4 Q-Reduction Compensation With the removal of the large external capacitor and with the low power requirements.4 that aims to reduce the high Q values of the poles and shift the poles locations to higher frequencies moving them away from the UGF.2.2. The first stage also has a current buffer to supply the required current to the second stage. the non-dominant poles start to suffer some changes such as. and gate-drain capacitor. both set by the latest SoC trends. a feed-forward capacitor to introduce a left-half-plane zero. Ccf. This topology consists in a three stage circuit. 2.

2.2.5 Pole-Zero Cancellation Compensation Topology. All these techniques using pole–zero cancellation are effective. Fig. Multipath Miller Zero Cancellation Compensation technique [4]. On the other hand. bandwidth efficiency. 2. quiescent current and silicon area are significantly higher. other compensation techniques like multipath nested Miller compensation (MNMC) [5] and hybrid nested Miller compensation (HNMC) [6] are reported to extend the gain bandwidth of the amplifier. and low power at driving 12 . the complexity. Nested Compensation (NGCC) is also proposed to reduce the zeros.2. This topology also permits a power device slew rate improvement.2. With this technique a greater bandwidth can be achieved for a suitable phase margin. 2. Further to MMZCC.5 seen on Surkanti’s study [15] improves the capless LDO frequency response by cancelling the effect of the existing output pole by determining its location and dynamically adding a zero over it. or near it. On the other hand. The addition of the zero will be achieved by the Resistor–Capacitor (RC) series connected to the gate of the pass device. simplifying the transfer function of the nestedMiller amplifier.6 Multipath Miller Zero cancellation compensation (MMZCC) The traditional solutions for RHPZ removal are all based on obstructing the direct path through the Miller capacitor.5 Pole-Zero Cancellation Compensation The multi-stage amplifier topology represented in Fig. counteracts the RHPZ by a parallel path that compensates for the direct feedthrough. The topologies are popular in terms of small area. The technique improves the bandwidth by removing RHP zero that arises in a Miller-compensated amplifier. conversely.

2. 2.small or moderate capacitive loads. 2. The traditional techniques. Hence. Fig.7 can be reduced by 1/AV times when compared with that in Fig.7 GFPC topology. This improved frequency compensation scheme is addressed in several key comments: 1) The transconductance gmf in Fig. 2. on the other hand. The enhancement factor is AV times for the transconductor stage. 2. Fig. MMZCC.6 at driving identical capacitive load condition. intend to obstruct the direct feedforward path through the Miller capacitor.7.2. 2. with low output impedance is added in the feedforward path. 2. a wide-band gain-enhanced voltage amplifier.6. The major advantage is that the positions of the poles are not affected by the additional circuitry. the overall feedforward transconductance is given as g mf ( overall)  AV g mf . or nulling resistor for RHP zero removal. 13 . current buffer.7 Gain-Enhanced feed-Forward path compensation (GFPC) A generic amplifier structure using GFPC technique [3] is depicted in Fig. Contrasting to the feedforward topology in Fig. such as voltage buffer. counteracts the RHP zero by a parallel path that compensates for the direct feed-through effect.6 MMZCC topology.

3) The result of small compensation capacitor leads to smaller silicon area. 14 . and 4) The major non dominant parasitic LHP pole becomes the new second pole that defines the phase margin of the operational amplifier. and note that this parasitic pole.2) The overall g mf (overall) boosted by the voltage gain amplifier reduces significant power consumption of the entire amplifier. is independent of the transconductance in the second gain stage. arised from the gain-enhanced voltage amplifier.

In short. is that an LDO must be able to provide current and voltage to any indefinite number of load blocks. The difference between LDOs and Band Gaps. which is usually a voltage regulator like an LDO. like any other voltage regulator. This reference is established by an electric circuit known as Band Gap.1. must provide a steady voltage to a single block with constant input capacitance. since both provide a steady voltage. must provide a steady and clean voltage at their terminals independently of external variations. To operate. 2.1 Conventional LDO topology LDO voltage regulators fall into the class of linear voltage regulators. The main blocks of the conventional LDO topology are the error amplifier. so LDOs. the pass device and the linear feedback network (R1 and R2). on the other hand. Band Gaps. Band Gaps don’t suffer from fan-out problems like LDOs. .Chapter 3 LDO Characterisation 3. The operation and objectives of this class remain the same. the LDO also needs a voltage reference. The conventional LDO topology is presented in Fig.

Class-A operation. It is also responsible for driving the pass device in function of the comparison result just stated. Class-AB operation allows the symmetrical output oscillation. The opposite process occurs when the LDO output voltage suffers from an overshoot.1 Conventional LDO topology. it can easily surpass 50% of the total LDO design area in SoC context. then the output voltage is defined by the Band Gap through the negative terminal and resistive divider. The pass device is a power device whose only function is to control the amount of current flow to the load. 3. can be designed to push or pull a pass device’s gate. raising the output voltage to the nominal value. as it needs to drive the total current the load. by exclusion. regulation and system control) and the signal inversion on the pass device. forcing the error amplifier output voltage to drop as well thus increasing the pass device’s driving force.. but never both [7]. Due to the advantages of the negative feedback (i. the positive terminal will drop. This device is extremely large.e. the capacitor at the output node will be charged more rapidly. To finalize the cycle. The error amplifier is responsible for the voltage comparison between the reference and the scaled down output voltage obtained by the resistive feedback network. the scaled down version of the output voltage needs to be fed to the positive terminal of the amplifier and. and time response. in low power context. 16 . as core circuitry in conventional error amplifiers. while driving. the Band Gap has to be fed to the negative terminal of the amplifier. Typically. The error amplifier’s ability to drive the pass device is asymmetrical [7] and depends greatly on the type of oscillation felt at the LDO’s output.Fig. a pass device supplies currents from 100 µA to 100 mA. charging or discharging it more quickly. If the output voltage suffers from an undershoot. with a small cost of complexity and silicon area. As the positive and negative terminals assume roughly the same value.

this capacitor poses a problem due to the fact that it is too large to be an on-chip capacitor and therefore goes against the modern design trends.Finally. Allen published a comparative study between LDO voltage regulators with different pass devices [16] where the advantages and disadvantages of each pass device were identified and its study deepened.1. 17 . acts like a charge source during fast load transients improving the response time of the regulator and its stability. To better understand LDO regulators and follow the work proposed in this and the next chapters a few parameters are introduced in Table 3. This study results. Rincón-Mora and P. Line Regulation Measure of the circuit’s ability to maintain a constant output voltage despite input voltage variations. summarized in Table 3. Overshoot Output voltage peak that occurs in load and line transients when the signal exceeds its target value. and the regulated output voltage. However.1 LDO Parameters.2. in conventional LDO topologies. the P-type Metal-Oxide-Semiconductor (PMOS) device. a large capacitor exists at the LDO output in parallel to the load. Dropout Voltage VDO Difference between the minimum input voltage. necessary for the regulator to operate. This large capacitor. identified what is known and accepted today as the most suitable pass device for LDO application. Quiescent Current IQ Current drawn by the regulator when no load is applied. Undershoot Output voltage negative peak that occurs in load and line transients when the signal exceeds negatively its target value. Load Regulation Measure of the circuit’s ability to maintain a constant output voltage despite output current variations. Load Transient Measurement of the system’s speed response to an overshoot or undershoot in the system’s output current Line Transient Measurement of the system’s speed response to an overshoot or undershoot in the system’s input voltage Power Supply Rejection or Measure of the circuit’s ability to regulate its output voltage against low to Ripple Rejection high frequency variations in the input supply. Table 3. as referred earlier.2 Pass Device G. 3.

fully saturating the transistor where the dropout voltage is given by Vec sat. The other reason is that. Once more. Table 3. where the lower dropout voltages the better. VDO. The lowest dropout voltage it can stand is given by (Vsat + 2Vbe) which is superior than 1 V.The most important criterion for the pass device selection was the dropout voltage. derivative amplifier [18]. The NMOS transistor can provide a minimal dropout voltage of Vsat + Vgs while the PMOS transistor can be fully saturated providing a smaller dropout voltage of Vsd sat. 3. Single PNP bipolar transistors are preferred to NPN bipolar transistors because the base of the PNP transistor can be pulled down to ground. since it is composed by bipolar transistors. Single NPN bipolar transistors are not the best option to LDO pass devices because its lowest dropout voltage is given by Vsat + Vbe. 18 . N-type Metal-Oxide-Semiconductor (NMOS) and PMOS transistors can operate as pass devices without increasing the quiescent current and with dropout voltages beneath 1 V. hence its name. the quiescent current increases greatly. In PNP transistors quiescent current is also increased due to the large base current required. when the base of the transistor is fully pulled up to the supply voltage.2 Comparison of Pass element structures NPN Darlington NPN PNP NMOS PMOS Iload-max High High High Medium Medium IQ Medium Medium Large Low Low VDO Vsat + 2Vbe Vsat + Vbe Vec-sat Vsat + Vgs Vsd-sat Speed Fast Fast Slow Medium Medium The NPN Darlington structure is not suited for low power LDOs for two main reasons. On the other hand. The error amplifier response is greatly increased by its feeding damping loop and its derivative output voltage sensing block. superior than 1 V. quiescent current also increases due to the large base current required.3 Error Amplifier The error amplifier present in the proposed topology has a key role in the fast voltage regulation and compensation of the capless LDO. being this last candidate the optimal solution for the pass device of low-power LDOs.

At high frequencies the MOS resistor M21 isolates the gate of the output biasing transistor M6 from the low impedance node of the bias-current mirror network (M4).2 Error amplifier topology used in the proposed LDO design [2]. 3. This makes it possible to drive M6 with signals at high frequencies by means of capacitor C1 and. due to this enhancement of performance. the transistor sizes and power dissipation of the output stage can be greatly reduced for a specified output current capability. Finally. Fig.The new multi-loop strategy is used to enhance the derivative voltage feedback performance by applying a feed-forward path to it. M22 and C1 (removed). the enhancement of the damping loop will contribute to. Since M6 can now sink much more than its bias current under transient conditions (and even at dc with reduced loop gain). The circuit in Fig. the circuit would be considered conventional. by means of transistor M22. in addition with the aforementioned enhancements.2 is shown with an n-channel input differential stage placed in a p-tub shorted to the source node. This has a supply-rejection advantage over the inverted form. Without the elements M2l (replaced by a short circuit). during negative slewing. Furthermore. 19 . The error amplifier used in the proposed regulator is shown in figure 3. This error amplifier has the basic form of an op amp [2]. a two-stage design for driving low-conductance loads. wherein the bulk material of the differential stage would be held at +VDD: there is no backgate bias effect that would cause a threshold voltage variation in the input devices and. the sensing of the fast output voltage variations will also be improved as well as the quality of the load and line transient responses of the capless LDO.2. 3. further improve the overall capless LDO response.

The circuit (Fig. the p-tubs of M0 and M1 may be tied to -VSS. one must understand the requirements for a fast comparator. Note that the transistor M22. the slew rate becomes limited by the total Miller capacitance then effectively across M6 rather than by the load capacitance. The gate of the push-up transistor M5 is driven quickly over the relatively small voltage differential to its threshold. for voltage-follower applications. 3. first mainly C1. There is then a short. relatively slow segment as the capacitances (including the load) charge up and the source of transistor M22 moves toward the positive supply.4 Comparator A high-speed comparator should have a propagation delay time as small as possible. has shorted the gates of the transistors M5 and M6. This feature is important when the gate of transistor M0 is terminated in high impedance while the gate of the transistor M1 is grounded. A current nearly equal to the full bias current 2I of the input stage is driven by transistor M3 to the output node during negative slewing. Thus. the conventional CMOS design becomes output limited in the negative direction if the bias current in M6 is low.2) provides means for large transient signal components to drive the pull-down transistor M6 into strong action during negative slewing. This may be best understood by separating the comparator into a number of cascaded stages. but not yet sufficiently far to turn M22 on. Even with relatively modest capacitive loading. Actually the M6 current has already risen moderately due to the presence of capacitor C2. First. so the slewing is a little faster than this.thus. As the common-mode input swings positive. one may use a cascode input stage to eliminate charge injection through the drain-gate capacitance. In order to achieve this goal. the inputs can swing more positive before the drain voltages of M0 and M1 approach the source voltage. acting as a switch. and improved common-mode range is obtained. The slew rate for no capacitive loading is primarily limited by the input stage current and the main shaping capacitor. Two modifications to the circuit are noteworthy. Second. 3. if maximum power supply rejection is needed. the sources of those devices rise at a slower rate due to the backgate bias effect on Vgs. After the threshold voltage of transistor M22 is passed. If the 20 . produce a charge injection into the input nodes through the gate-source capacitance.

However. A high-speed comparator can be designed using three cascaded low-gain amplifiers as the preamplifier and a latch at the output. The low gain preamplifier must compromise between a high bandwidth and sufficient gain. the amplifiers will be limited by their slew rate. The design of the preamplifier must be done in such a manner that the desired latch input voltage is achieved in minimum time. We know that the gain bandwidth of an amplifier is normally constant. Thus. There are several problems with this preamplifier of Fig. 3. If a number of low-gain wide-bandwidth amplifiers are cascaded. Therefore the stages at the beginning should be designed differently than the stages at the end of the amplifier chain. the delay time can be minimized. Another is that there is no isolation between the latch outputs and the inputs to the preamplifier.input change is slightly larger than Vin (min). The connection with the latch (for the last preamplifier) is shown. A simple preamplifier circuit is shown in figure 3. a single amplifier has a limited capability. then the function of the stages is to amplify the input with as little delay per stage as possible. This combines the best aspect of circuits with a negative exponential response (the preamplifier) with circuits with a positive exponential response (the latch). for initial stages.3. Rapid changes in the output of the latch can propagate through the drain-gate capacitances of M1 and M2 and appear at the input of the latch. The basic principle behind the high-speed comparator is to use a preamplifier to build up the input change to a sufficiently large value and then apply it to the latch [17]. One is that the gain is very small even for large differences of W/L values.3. this means that the bandwidth must be as large as possible. it is more important to have a high slew rate capability so that the voltage across the inter stage capacitors and the load capacitor rises or falls quick enough. 21 . We note that the signal swings in the initial stages will be small. Transistors M5 and M6 are used to increase the current in M1 and M2 so that the gain is enhanced by the square root of the difference of currents in Ml and M2 to the currents in M3 and M4. the important Parameter is to have a high bandwidth so that there is little delay in amplifying the signal and passing it on to the next stage. Therefore. Fig. As the signal swing begins to approach the desired range. 3. at the end of the cascade of amplifiers. Since the preamplifier is working in the linear region.4 shows a preamplifier that solves these two Problems.

3. Fig.3 Example of Preamplifier and latch. The input input-offset voltage of the 22 .4 An improved Preamplifier. 3.Fig. The use of a preamplifier before the latch also has the advantage of reducing the input offset voltage of the latch by the gain of the preamplifier.

comparator will now become that of the preamplifier. In the latch portion of the comparator circuit. In this case it is advisable to follow the latch by circuits that can quickly generate large amounts of current.5. Fig. Also. as without these the latch will remain in a single state. which can be autozeroed. the resistor R1 in the preamplifier portion is used so as to track the signals in both the branches.5 Comparator topology used as the feed forward path. 23 . The latch outputs are used to drive a self-biased differential amplifier [1]. the latch is generally not sufficient. The first stage is a low-gain. 3.5 is used in the feed forward path of the low dropout voltage regulator. resulting in small values of input-offset voltage. When a comparator must drive a significant amount of output capacitance in very short times. high-bandwidth preamplifier that drives a latch. 3. The output of the self-biased differential amplifier drives a push-pull output driver. The comparator circuit shown in figure 3. A high-speed comparator following these principles is shown in Fig. transistors M13 and M14 are used to enable the latch to change its state.

6 and it is called Band Gap Reference. if a reference is temperature-independent. However. is the one commonly used in many advanced designs and commercial products since it can provide a predictable reference voltage. the resultant quality theoretically exhibits zero temperature coefficients. error voltage from the clamping circuit. Bandgap voltage reference. which need high-accuracy reference voltage to provide high-resolution and high speed data conversions in low supply-voltage conditions. an error. there are many sources of error in the voltage reference such as error current from the current mirrors. Undoubtedly. low supply voltages limit the available methodologies and cause severe design problems. With the development of CMOS technology.8V or even subs 1V systems. This error is no doubt significant in the past 5V and 10V systems. it is also possible for low voltage and low temperature dependence. Moreover. Solutions have been proposed but are less useful in low voltage conditions. but is a fatal error in current 1. Reference voltage accuracy determines the maximum achievable performance of all IC systems. 24 So the conventional . typical Bandgap references have non-zero temperature coefficient of typically around 4050ppm/oC. which was firstly proposed by Widlar and was further developed by Kuijk and Brokaw. A perfect voltage reference should contain no error. as well. Reference voltages and/or currents with little dependence to temperature prove useful in many analog circuits. process and temperature. because the reference voltage accuracy determines the maximum achievable performance of all IC system. It is called as band gap reference because dVout/dT is zero when Vout= B. This is shown in figure 3. it is usually process independent. there are many well developed circuits and layout techniques to minimize the errors.2V. Reference voltage circuitry is a very important block in the integrated circuit such as A/D. D/A and other communication systems. Moreover.G of silicon. However. This is no doubt. As many process parameters vary with temperature. If two quantities with opposite temperature coefficient are added with proper weighting. as well as device mismatches.5 Band Gap Reference An ideal voltage reference provides stable voltage independent of supply.3. The output voltage of conventional bandgap reference voltage structures almost equals to 1. low supply voltage becomes important in IC design. By adding VBE to difference of VBE with proper scaling temperature coefficient of the system can be made to zero.

which is proportional to absolute temperature (PTAT). The negative temperature coefficient of the former term compensates the positive temperature coefficient of the latter.8 V supply voltage is presented. 3. 25 .1 Peak Overshoot and Undershoot The maximum tolerable transient supply overshoot and undershoot for analog subsystems driven by low dropout regulator should not exceed 300mV. A curvature compensated bandgap reference (BGR) with .6 Principle of BGR.2V.6. Fig. one is proportional to VBE across the base-emitter of the parasitic BJT in CMOS process. 3. the other is proportional to VT .architecture is improper for use in the latest deep submicron technologies whose power supply is equal to or lower than 1. Therefore peak overshoot and undershoot specification is taken as maximum 200mV. But the temperature dependence of VBE is not linear and therefore doesn’t completely cancel the linear temperature dependence of ΔVBE.6 Low Dropout Regulator Characterization 3. which utilizes the different temperature-dependent emitter of the BJT to obtain the nonlinear current INL to cancel the nonlinear term of VBE. The typical current mode bandgap voltage circuit is built up by two currents.

which is given by 1/λout.5 Loop Gain Loop gain for the LDO is calculated based on the load regulation specification obtained above using the following equation. the temperature coefficient.04mV. pass transistor.TC… … … … … … … … … … (3. optimum dropout voltage is chosen as 200mV. the reference accuracy is  Vo. Considering minimum input voltage with a safety margin to be 1. 3.4 Settling Time Settling time of 2µs is optimum for this purpose. Accuracy  Vlinreg  Vloadreg  Vo2. the line and load regulation are calculated.2)  I o 1  A Here rop is the output resistance of the pass transistor. The temperature coefficient  VTC=35ppm/0C*(TminTmax)*Vo=35*120*1.6. as larger settling time corrupts the frequency of oscillation of internal oscillators of the load driven by this LDO. rop Vo … … … … … … … … … … … … … (3. 3.3. and feedback resistor ratio.6. load regulation specification can be taken as 3µV/mA.4V.3 Line and Load Regulation The accuracy constraint for the LDO output is defined by the following equation. 3. Similarly. LOR  3.ref=20*120*0.1) Vo From accuracy constraint.8*10-6=1. So the error amplifier as 55dB and the remaining gain will be provided by the pass transistor.6 PSRR It is sufficient to choose -40dB at low frequencies since the audio sub systems that gets excited by this LDO has a mechanism of rejecting all power supply ripple frequencies beyond audio range.6. From this we get loop gain as 70dB.92mV. the larger the pass transistor required.6.ref  Vo2.6. reference accuracy. 26 . Thus.2 Dropout Voltage The higher the dropout voltage the larger the power consumption of the circuit and the smaller the dropout voltage. Loop gain is distributed between error amplifier.2*10-6=5.

7 LDO Specifications Table 3.4V Output Voltage (VOUT) 1. Parameters Specifications Technology 180nm CMOS Input Voltage(VIN) 1.2V Output Load Capacitor (CL) 100pF Quiescent Current (IQ) <70µA Output Current (ILOAD) 100mA Load Regulation <3µV/mA Phase Margin >70o Loop Gain ~70dB Gain-Bandwidth >1MHz Settling Time <1µs Dropout voltage <200mV 27 .3 LDO Specifications.3.

VDS≥ VGS– VT. error amplifier. 4.Chapter 4 Design and Implementation 4. .1 Overview The proposed LDO design is divided in to 4 parts. of 200 mV. The schematic of the proposed capless LDO is shown in figure 4. In device parameters. pass transistor.2 Pass Transistor Design The dropout voltage of the LDO was selected to be 200mV for a maximum load current of 100 mA based on current LDO regulator requirement.1. the pass transistor is designed to deliver a drain current of 100mA while maintaining a saturation voltage. comparator and BGR design.

IMAX defines the maximum output current.Fig. forcing the dimensions of the pass transistor.2 Pass Transistor design. W/L.1 Schematic diagram of the proposed capless LDO regulator regulator. 4. 4. for a desired minimum VDROP OUT. Fig. 29 .

Large gate capacitance along with variable low-frequency load impedance makes stabilizing a capacitor-less LDO difficult. 30 ... VDROPOUT  VDSAT  2 I max .. ... .. .... Equation (4. .1) w  p Cox l The LDO is designed at maximum load current and minimum input voltage and such that pass transistor is in saturation. This relationship is shown in equation (4.. This current through the series connected feedback resistors is solely determined by the output voltage... . . notably the gatesource capacitance CGS. To meet the requirements of maximum load current and minimum dropout voltage the pass transistor of a very large dimension is required. ... This degradation in load regulation can only be counteracted by providing more current to the LDO.. Subthreshold operation produces a significantly slower response. For large variations in the load current. The Miller effect with CGD further increases the effective gate capacitance. . Pass transistor subthreshold operation is another major concern.2) shows the relationship of RF1and RF2 with output voltage... Such a large device introduces significant parasitic capacitances into the network. ..3 Feedback Resistor Design The feedback resistors RF1 and RF2 are designed to draw a current IF.. improving the speed of the circuit. .. The gate-source capacitance of this PMOS pass-transistor measured 26pF..First order approximations were used to find the rough device dimensions.1). 4. (4.. This may cause significant degradation in the voltage regulation for applications where the load current drops to low current levels in a short span of time. the PMOS transistor will undergo a transition from operating in the saturation region to operating in the subthreshold saturation region.

... .4 Band Gap Reference Design The design of voltage reference mainly improves accuracy and rejects errors. .Fig... RF 1  RF 2  Vout ...3) shown below. but it is a costly procedure.... .3) RF 1  RF 2 Assuming the value of IF and using the values for VRef and Vout... (4. . ... .3 Feedback resistor network design.... ... . the errors in every part should be minimized by circuit and layout techniques. VRe f  Vout RF 1 ... . . the values of RF1 and RF2 can be obtained... .. Thus..... For RF section LDO of mobile phone where accuracy is primary requirement. . As a result specifications became very tight.... ... a large portion of market demand is driven by portable electronic applications whose operating voltage range is very low and whose power requirement is also low. As a result. . .. . (4... . . 4.. Their temperature drift characteristics need to be tight.. .. . Currently. as well as voltage clamping. Laser trimming can be used to optimize the performance of Band gap voltage references.......... current mirror. . . Considerations should be focused on BJT ratio and resistor ratio matching... These considerations are discussed below.. .. There are many reference topologies available for variety of applications and process technologies. accuracy of BGR has to be very high...2) IF The values of RF1 and RF2 can be found by relation (4. 4. layouts on BJT’s and resistors should be well planned and designed so that consistent performance can be achieved.. . 31 . .. .

. .. ........... The minimum supply voltage of the circuit is determined by the VEB plus saturation voltage of a Pchannel transistor...6)  T0   T0  32 .. . VT is the thermal voltage.. . (4. . .4 Schematic of Band Gap Reference Circuit..... while I2 is a current due to VEB and R2 as given by I2 = VEB /R2.. .....4) Where N is the emitter area ratio... and R2= R2A = R2B..4. ....6).. so I1= VTln N / R1.The principle of typical BGR can be illustrated by Fig.... thus the output voltage of the band gap circuit is given by. ... The reference voltage is formed by two currents I1 and I2.. According to an empirical relationship. . For I1 it is a PTAT current formed by Q1. .. . (4... .. . ... ∆VBE is the VBE difference between Q1 and Q2.5) 1   The compensation of the TCs of VT and VEB can be ensured by a proper choice of the R2/R1 ratio and N. T  T  VEB T   VBG  VBG  VEB 0 T       VT ln  . .R3  R3 R2   R2 VEB  R VT ln N  . . VRe f  I1  I 2 . .. 4. . .. Due to the current mirror formed by M1.. VBE  VEB1 VEB2 VT ln N . the VBE voltage in a BJT can be given by equation (4.. . Q2 and R1. 4. .. The TCs of resistors are cancelled if resistors are made with the same resistive layer. M2 and M3.. (4. Fig.

. 4.. .. VNL= VBBQ1. . The structure of curvature-compensated BGR is shown in Fig. thus leading to 33 ... VBE does not change linearly with the temperature.5 Band gap reference circuit with curvature compensation.VBBQ3(T) = VT ln (T/TO).7) Curvature compensation current proportional to VNL can be achieved now by subtracting from both I1 and I2.. 4. From above equation.Where η is a process-dependent constant and is around 4..6)... which drain from M1 and M2 the required current INL. .5 is PTAT (α = 1) while the current in the p-channel MOS transistors is at first order temperature independent.5. 4.2 and inject it into a diode connected bipolar transistor Q3. The simple bandgap architecture shown in Fig. The current in Q1 and Q2 in Fig. Therefore.. . Fig.. we produce a VEB with α=0.4 only corrects the first term in Equation (4.. Various approaches to compensate for the nonlinear term have been proposed. The basic idea is to correct the nonlinear term by a proper combination of the VEB across a junction with a temperature-independent current (α = 0) and the VEB across a junction with a PTAT current (α = 1). (4... . 4. as shown in Fig. thus leading to a second order temperature dependence. while α = 1 if the current in the BJT is PTAT and α = 0 when the current is temperature independent.2(T) . This is obtained by introducing resistors R4A and R4B (equal).. if we mirror the current flowing in p-channel MOS transistors M1. .

. ...... Load Regulation is given by LRload  rop VO  . A theoretical zero TC VREF can be obtained. and feedback resistor ratio. So the error amplifier as 55dB and the remaining gain will be provided by the pass transistor.. . . .... Loop gain is distributed between error amplifier.. However...5 Error Amplifier Design From load and line regulation specifications we get loop gain for the error amplifier. pass transistor. UGB should be atleast 1MHz.. . the nonlinear voltage in VEB is cancelled.. . rop is the output resistance of pass transistor...9) I O 1  A From specifications load regulation is given by 3µV/mA.. it cannot always be achieved due to the non ideal PTAT and temperature dependence of resistors. . So the following specifications are taken for the error amplifier. 34 .. (4. Gain >= 55dB UGB >= 1MHz Slew rate = 2V/µs Phase margin >700.. . (4...... . For the LDO to respond in 1µs. . .... which is given by 1/λout. From this we get loop gain as 70dB. .....8) When the resistors ratio R2/R4 = η − 1. . . ... V ln N  VEB VT  T  VREF   T   ln  R3 R2 R4  T0   R1 R  3  R2   T   R2 R2    V  V ln N  V ln  EB T T R R 1 4  T0    ... . . 4.... ... .

the results of the performed simulations are presented.2 V. it includes the power line distribution capacitances as well as parasitic capacitances. Bandwidth is 4. bandwidth and phase margin can be obtained for Iout= 100 mA.742 MHz and Phase Margin is 77.4 V regulating to Vout= 1. Vin= 1. 5.096 mW. The designed capless LDO circuit consumes a total biasing current (quiescent current) of around 69 µA with a total power consumption of 0.1 shows the AC response of the design where the loop gain. The conditions of the simulations and its considerations are also given as well as their validity. All simulations were executed for the minimum dropout voltage across the pass device of 200 mV.93° for the output load capacitor of 100pF.1 Loop Gain Simulations The overall stability of the system is defined from its loop gain and phase response. Fig. . As can be observed from the plots the obtained Loop Gain is 68 dB.Chapter 5 Results and Discussion In order to fully characterize the proposed capless LDO. It is assumed that the capacitance seen by the output node of the LDO forward is 100 pF. 5.

2 Transient response Simulations Fig. the output voltage suffered from an undershoot of 153. and an overshoot of 196.1 Loop gain and Loop phase plots.3. As expected. 5. 36 .24 mV to the 100 mA – 0 mA output current transition. The simulation was performed to the minimum dropout voltage where the output current quickly (rise/fall time=1 µs) varied from 0 mA to 100 mA. as shown in figure 5.79 mV to the 0 mA − 100 mA output current transition. 5. 5.1 µs for the output voltage undershoot case (measured when the output voltage is within ±10% of the regulation value). The settling time.2 presents the capless LDO load transient response of the proposed capless LDO. is approximately 1.Fig.

The load transient results achieved are considered good results due to the fact that the regulation is possible even with low quiescent current while the under and overshoot results are kept relatively low.2 Load transient response plot for load varying from 0 to 100mA (rise time of 1µs). Fig. 37 . 5.Fig. 5.3 Load transient response plot for settling time measurement.

5. LNR = 1/PSRDC. The line regulation value can also be obtained by the system’s PSR response through its mathematical relationship.05 dB and −14.4. 38 .4 PSR simulations The behaviour of the proposed capless LDO to ripples in the power supply node is presented in Fig. 5.5.4 Load regulation plot 5.77 µV/mA V/mA at load current of 100 mA as shown in Fig.5. Fig.3 Load regulation simulation Simulated value of the load regulation is: 2. The PSR values achieved with the proposed capless LDO to the usual values of frequency (1Hz Hz and 20 kHz) are −15. The PSR results achieved are not according to the specifications and much can still be done to improve the response at issue. namely to improve the attenuation of undesirable ripples at the supply node throughout different segments of the frequency requency range.73 dB B respectively. 5.

From the designed BGR. which produces an output reference voltage VRef of 0.4V operation has been presented. 5.6 Plot for Temperature Coefficient over temperature range -40 to 80 °C.Fig. 5. 39 .5 Band Gap Reference TC simulation The proposed CMOS band gap reference with 1.58 ppm/°C over the temperature range of -40 to 80 °C. simulation result predicts a temperature coefficient of at most 19. Fig.5 Power Supply Rejection plot. 5.8V. The output reference voltage can be varying by adjusting current mirror and the resistor.

79 40 [23] [24] This work .35 0.6 Comparison with the Previous works Table 5.1 Comparison with the recent reported prior-art results Ref.5 3.5 7 41.18 0.7 69 ∆VOUT[mV] N.5.1 shows the performance comparison of the proposed work with respect to the recent prior-art works of capacitorless LDO.A. It indicates that the optimal trade-off performance can be obtained in the proposed work.11 0. [19] [20] [21] [22] Year 2009 2010 2011 2012 2013 2014 2014 Tech.[µm] 0.35 0.18 VDrop[mV] 200 200 200 150 200 200 200 COUT(pf) 100 100 0-100 100 40 100 100 Cm(pf) 3 7 10 - - - 3 IMax[mA] 100 100 100 100 200 100 100 IMin[µA] 50 0 0 0 500 0 0 IQ[µA] 27-270 20 14-53.35 0.18 0. <97 <339 236 385 277 153. Table 5.

This LDO presents a good stability with a phase margin of 77. The topology is validated through simulation results. bandwidth and transient response of LDO without increasing power or area consumption as the compensation capacitors involved are of low values. These two . The improved design will be suitable for application to SoC to reduce power and cost consumption.2 Future Scope Some of the future enhancements that can be made for this project work are as follows: 1. Error amplifier with PMOS current mirror load has good DC PSR at LDO output and NMOS current mirror load will have a high PSR bandwidth at LDO output.79 mV when the output current changes from 0 to 100 mA and 196. 6. This structure enhanced the gain.Chapter 6 Conclusions 6. The output voltage spike of the LDO with the proposed circuit decreases to 153. This LDO compares favourably with that of other published designs.1 Conclusion This thesis presented a stable LDO voltage regulator with an improved gain enhanced feed forward path compensation using a comparator. The LDO consumes a total biasing current of around 69 µA.24 mV for the current change from 100 mA to 0.93° for ILOAD of 100mA.

The improvement of the LDO PSR with the pole cancellation technique should be achieved by introducing an internal zero that does not affect the signal path. 42 . but it comes at the expense of power and silicon area.error amplifiers can be connected in parallel to achieve both. 2.

and J. Chan. Huijsing. A.K. April 2005. 43 . 1709–1717. Feb 1983. Leung. Solid-State Circuits. P.121. Chen. “Two novel fully complementary self-biased CMOS differential amplifiers”. G. “Design of low-power analog drivers based on slewrate enhancement circuits for CMOS low-dropout regulators”. “An output capacitor-less low dropout regulator with direct voltage-spike detection”. IEEE Transactions on Circuits and Systems – II: Express Briefs. IEEE Journal of Solid-State Circuits.12.933. N. Karnik. G. C.2. France. H. Huijsing. In Proc.R. G. “A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement”. September 2007. T. [10] Pui Ying Or and Ka Nang Leung. T. 1994. [5] R. USA: McGraw-Hill. Hazucha. Eschauzier. Huijsing.. H. no. vol. IEEE Journal of.1. Rincon-Mora. IEEE Journal of. Dec. and S. “A 100-MHz 100-dB operational amplifier with multipath nested miller compensation structure. [2] Saari. [3] Chan. Dec. H. pp. R. “Analog IC Design with Low-Dropout Regulators”. 168. “Area-efficient linear regulator with ultra-fast load regulation”. Eschauzier and J.50.26. H. [9] P. Lee. A. “A programmable 1. IEEE J. [8] Tsz Yin Man. IEEE Trans. 40(4):933–940. Kerklaan.Literature Cited [1] Bazes.18. Parsons. Hogervorst. L. Feb 1991. no. Philip K. [11] H. [6] R. Solid-State Circuits. 52(9):563–567. pp. D.. 127. H. Gifsur-Yvettes. vol. M. IEEE Journal of Solid-State Circuits. and M. September 2005. ESSCIRC 1993. C. V.165. vol. 29. H. P. K. Brokar. 54(9):755–759. February 2010. 941. T. 27. Mok. Circuits Systems – II: Express Briefs. Solid-State Circuits. and J. no. Editions Frontieres. 1497–1504. Bloechel. New York. 45(2):458–466. Finan. Y. vol. P.5 V CMOS class-AB operational amplifier with hybrid nested miller compensation for 120 dB gain and 6 MHz UGF”. Solid-State Circuits. pp. pp. 1992. Eschauzier. Dec. “An operational amplifier with multipath miller zero cancellation for RHP zero removal”. vol. pp. and K. Circuits and Systems II: Analog and Digital Signal Processing. “Low-Power High-Drive CMOS Operational Amplifiers”. “Gain-enhanced feedforward path compensation technique for pole-zero cancellation at heavy capacitive loads”. IEEE Transactions on. [7]G. IEEE J. 2009. Mok. 2003 [4] R.

“A fast-transient LDO based on buffered flipped voltage follower”. “An ultrafast adaptively biased capacitorless LDO with dynamic charging control”. and Philip KT Mok. “A capacitor-less CMOS active feedback lowdropout regulator with slew-rate enhancement for portable on-chip application”. IEEE. N. 1. Circuits and Systems II: Express Briefs. Zhou.2 (2010): 80-84. Chan. June 2013.6. 2012. 2010. [22] X. Circuits Syst. 2011 IEEE International Symposium on. New York. IEEE Journal Solid-State Circuits. IEEE Trans. K. 54(7):1459–1470. 42(3):658–664. 2002. 44 . “A quiescent power-aware low-voltage output capacitorless low dropout regulator for SOC applications”. Ming. 59. Leung. Circuits and Systems II: Express Briefs. Zhang. [16] Gabriel Alfonso Rincón-Mora and Phillip E. Circuits and Systems. P. Q. Texas A&M University. IEEE Trans. Allen and Douglas R. “A Capacitor less LDO Regulator with Fast Feedback Technique and Low-Quiescent Current Error Amplifier”. “A high-precision low-voltage low dropout regulator for SoC with adaptive biasing”. Jan. and K. Holberg. Chenchang. pp.[12] Hua Chen and Ka Nang Leung. “A low-dropout regulator for SoC with qreduction”. [15] P. S. and Wing-Hung Ki. pages 1–4. and B.60. Circuits and Systems (ISCAS). December 2005. IEEE Transactions on . no. A. Furth. Conf. USA: Oxford University Press. Lau.R.326. S. [17] Philip E. ISCAS 2009. Circuits and Systems – I: Regular Papers. and P. 2009. vol. “Advances in reversed nested miller compensation”. Allen. Garimella. K. [14] S. “Pole-zero analysis of multi-stage amplifiers: A tutorial overview”. “A capacitor-less low dropout voltage regulator with fast transient response”. and P. [19] Zhan. [18] Robert Jon Milliken.. 2011. pp. Briefs. [20] Ho. IEEE International Symposium on. of Electron Devices and Solid-State Circuits. [23] Young-Il Kim. Mok. 40–44. IEEE 54th Int. [21] Chong. March 2007. August 2011. Z. “CMOS Analog Circuit Design”. T. 2009. “Study and Design of Low Drop-Out Regulators”. K. II. Surkanti. on Circuits and Systems. Sang-sun Lee. Midwest Symp. July 2007.M.330. Edward NY. IEEE. Master’s thesis. IEEE Transactions on57. [13] Alfio Dario Grasso. Gaetano Palumbo and Salvatore Pennsisi. no. Exp. vol. IEEE Int. Li.

Rasoul.. Integration.[24] Fathipour. et al. 45 .2 (2014): 204-212. “High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator”. the VLSI Journal 47.

K. at first. I would like to thank the Head of Department. Sunil Kumar Bhat and Mr. Saurabh Dixit Roll No.S. I would like to thank Prof. as my advisor and guide over this period of my master’s program. His devotion in the field of VLSI has been a great inspiration in finishing my master’s studies. 124570 46 .Acknowledgements I have been very fortunate to have Dr. National Institute of Technology Warangal for his invaluable guidance and motivation. Mr. Department of Electronics and Communication Engineering.S. I am grateful to him for his invaluable guidance and motivation.R. for their constant help in the discussion of the problems about this project. Patri Sreehari Rao. I am also grateful to my parents for their constant and much needed priceless support. At last I would like to thank Mr. Prof. So. Debashish Dwibedy. Suresh Alapati. Department of Electronics and Communication Engineering. I would like to thank him for allowing me to do this work with his constant support and encouragement throughout the completion of the project.V. National Institute of Technology Warangal.N.Tech.N Sarma and all my faculty members in ECE department for their help during my M. Krishna Prasad. research scholar.