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Arithmetic Circuits:

Signed Numbers, Binary Adders

and Subtractors

Signed numbers

• For signed numbers, in the binary system, the sign

of the number is denoted by the left-most bit

– 0 = positive

– 1 = negative

• For an n-bit number, the remaining n-1 bits

represent the magnitude

magnitude magnitude

MSB MSB

Unsigned number Signed number

1

Negative numbers

• For signed numbers, there are three common

formats for representing negative numbers

– Sign-magnitude

– 1’s complement

– 2’s complement

• Sign-magnitude uses one bit for the sign (0=+, 1=-)

and the remaining bits represent the magnitude of

the number as in the case of unsigned numbers

• For example, using 4-bit numbers

+5=0101 -5=1101

+3=0011 -3=1011

+7=0111 -7=1111

• Although this is easy to understand, it is not well

suited for use in computers

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 17-3

• In the 1’s complement scheme, an n-bit negative

number K, is obtained by subtracting its equivalent

positive number, P, from 2n-1

K=(2n-1)-P

• For example, if n=4, then

K=(24-1)-P=(15)10-P=(1111)2-P

-5=(15)10-5=(1111)2-(0101)2=(1010)2

-3=(15)10-3=(1111)2-(0011)2=(1100)2

• From these examples, clearly the 1’s complement

can be formed simply by complementing each bit of

the number, including the sign bit

• Numbers in the 1’s complement form have some

drawbacks when used in arithmetic operations

2

2’s complement representation

• In the 2’s complement scheme, an n-bit

negative number K, is obtained by

subtracting its equivalent positive number, P,

from 2n

K=2n-P

• For example, if n=4, then

K=24-P=(16)10-P=(10000)2-P

-5=(16)10-5=(10000)2-(0101)2=(1011)2

-3=(16)10-3=(10000)2-(0011)2=(1101)2

• A simple way of finding the 2’s complement

of a number is to add 1 to its 1’s complement

• Given a signed number, B=bn-1bn-2…b1b0, its

2’s complement, K=kn-1kn-2…k1k0, can be

found by:

– examining all the bits of B from right to left and

complementing all the bits after the first ‘1’ is

encountered

• For example if

B=00110100

• Then the 2’s complement of B is

K=11001100

changed bits unchanged bits

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 17-6

3

Four-bit signed integers

b3b2b1b0 Sign-magnitude 1’s complement 2’s complement

0111 +7 +7 +7

0110 +6 +6 +6

0101 +5 +5 +5

0100 +4 +4 +4

0011 +3 +3 +3

0010 +2 +2 +2

0001 +1 +1 +1

0000 +0 +0 +0

1000 -0 -7 -8

1001 -1 -6 -7

1010 -2 -5 -6

1011 -3 -4 -5

1100 -4 -3 -4

1101 -5 -2 -3

1110 -6 -1 -2

1111 -7 -0 -1

• For sign-magnitude numbers, addition is simple, but

if the numbers have different signs the task becomes

more complicated

– Logic circuits that compare and subtract numbers are also

needed

– It is possible to perform subtraction without this circuitry

– For this reason, sign-magnitude is not used in computers

• For 1’s complement numbers, adding or subtracting

some numbers may require a correction to obtain

the actual binary result

• For example, (-5)+(-2)=(-7), but when adding the

binary equivalents of –5 and –2, the result is 0111

with and additional carry out of 1 which must be

added back the the result to produce the final

(correct) result of 1000

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 17-8

4

2’s complement operations

• For addition, the result is always correct

• Any carry-out from the sign-bit position is

simply ignored

(+5) 0101 (–5) 1011

+ (+2) +0 0 1 0 +(+2) +0 0 1 0

(+7) 0111 (–3) 1101

+ (–2) +1 1 1 0 + (–2) +1 1 1 0

(+3) 10 0 1 1 (–7) 11 0 0 1

ignore ignore

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 17-9

• The easiest way of performing subtraction is to

negate the subtrahend and add it to the minuend

– Find the 2’s complement of the subtrahend and then perform

addition

(+5) 0101 0101

– (+2) –0010 +1 1 1 0

(+3) 10 0 1 1

ignore

(- 5) 1011 1011

– (- 2) –1110 +0 0 1 0

(- 3) 1101

5

Adder and subtractor unit

• The subtraction operation can be realized as the

addition operation, using a 2’s complement of the

subtrahend, regardless of the signs of the two

operands

– It is possible to use the same adder circuit to perform both

addition and subtraction

• Recall that the 2’s complement can be formed from

the 1’s complement simply by adding 1

• We can use the XOR operation to perform a 1’s

complement

– Recall x⊕1=x’ and x⊕0=x

– If we are performing a subtract operation, 1’s complement

the subtrahend by XORing each bit with 1

y y y

n–1 1 0

Add/ Sub

control

x x x

n–1 1 0

c n-bit adder c

n 0

s s s

n–1 1 0

6

Arithmetic overflow

• The result of addition or subtraction is

supposed to fit within the significant bits

used to represent the numbers

• If n bits are used to represent signed

numbers, then the result must be in the

range –2n-1 to +2n-1-1

• If the result does not fit in this range, we say

that arithmetic overflow has occurred

• To insure correct operation of an arithmetic

circuit, it is important to be able to detect the

occurrence of overflow

arithmetic overflow

For 4-bit numbers, there are 3 significant bits and the sign bit

+ (+2) +0 0 1 0 + (+2) +0 0 1 0

(+9) 1001 (–5) 1011

c4 = 0 c4 = 0

c3 = 1 c3 = 0

+ (– 2) +1 1 1 0 + (–2) +1 1 1 0

(+5) 10 1 0 1 (–9) 10 1 1 1

c4 = 1 c4 = 1

c3 = 1 c3 = 0

If the numbers have different signs, no overflow can occur

Electrical & Computer Engineering Dr. D. J. Jackson Lecture 17-14

7

Arithmetic overflow

• In the previous examples, overflow was detected by

overflow=c3c4’+c3’c4

overflow=c3⊕c4

overflow=cn-1⊕cn

modified to include overflow checking with the

addition of one XOR gate

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