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IDESA

Implementation of widespread IC design skills
in advanced deep submicron technologies
at European Academia

Advanced RF implementation flow
90nm design verification
22 May 2008
Wieslaw Kuzmicz - Warsaw University of
Technology, Warsaw, Poland

Copyright Statement
The development of this material was funded by the European
Community through the 7th Framework Program.
This material can be used in the curricula of regular master courses at
European academia. Use for commercial benefit is prohibited.

IDESA - IC Design Skills for Advanced DSM Technologies

Outline
Goal of this presentation: discussion of design verification
techniques, with special emphasis on realistic post-layout
simulation and on layout verification issues in DSM
technologies
Verification goals and flows
Circuit extraction for post-layout simulation


Basic concepts
Parasitic extraction
Special cases

Design Rule Checking and Design for Manufacturability

Design Rules and Checks
Recommended rules for DfM

Layout postprocessing and mask preparation
Wieslaw Kuzmicz - Warsaw University of Technology © IDESA 2008 |

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IDESA - IC Design Skills for Advanced DSM Technologies

Chip verification 15 years ago…

and now

Formal verification

complexity: 10x more rules
– DRC
– Nominal circuit extraction, ERC and LVS

Functional verification
– Circuit extraction with parasitics
– Post-layout simulation

2D->3D, extraction for RF
new complex device models

Verification of manufacturability and DfM
– New classes of design rules
• recommended rules
• additional restrictions

– Layout postprocessing
• Modifications for CMP, layer density rules
• Resolution enhancement techniques: OPC, PSM, SRAF
Wieslaw Kuzmicz - Warsaw University of Technology © IDESA 2008 |

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Monte Carlo OK? N Y Chip finishing Pad ring.the old way Design Circuit and layout design DRC OK? N Y Traditional verification flow Extraction.IC Design Skills for Advanced DSM Technologies Analog verification and chip finishing . ERC and LVS OK? N Y Designer’s job Parasitic extraction and postlayout simulations: nominal.IDESA . at PVT corners. and final DRC OK Wieslaw Kuzmicz . logo etc.Warsaw University of Technology © IDESA 2008 | Fab line 5 .

IDESA . PSM. SRAF) Optionally designer’s job Litho simulation Parasitic extraction and post-layout simulations (optional) Often designer’s job Not OK OK Wieslaw Kuzmicz .Warsaw University of Technology © IDESA 2008 | Fab line 6 .IC Design Skills for Advanced DSM Technologies DSM analog verification and chip finishing Circuit and complete layout design Traditional verification flow Not OK Always designer’s job OK DfM layout improvements Layer density verification OK? N Layout redesign Y Traditional verification flow Not OK OK Usually manufacturer’s job Applying RET (OPC.

Warsaw University of Technology © IDESA 2008 | 7 .IDESA .IC Design Skills for Advanced DSM Technologies Derived layers Creating derived layers for circuit extraction M1_to_N_S/D capacitor = NMOS_S/D • Metal1 • !Contact cut Metal1 N implant NMOS_channel = Active • N implant • Poly (note: this capacitor is shorted here) Poly Active Contact cut NMOS_S/D = Active • N implant NMOS_S/D contact = NMOS_S/D • Metal1 • Contact cut Wieslaw Kuzmicz .

IDESA .Warsaw University of Technology © IDESA 2008 | 8 .IC Design Skills for Advanced DSM Technologies Derived layers Creating derived layers for circuit extraction Poly_contact = Poly • Metal • Contact cut Poly Metal1 (note: this capacitor is shorted) M1_to_poly_capacitor = Poly • Metal • !Contact cut Wieslaw Kuzmicz .

IDESA .Warsaw University of Technology © IDESA 2008 | 9 .IC Design Skills for Advanced DSM Technologies Derived layers Creating derived layers for design rule check (DRC) 0.no error here Active DPA = Min polyactive spacing Poly Poly_to_active_error = Poly_DRC • Active_DRC Wieslaw Kuzmicz .5 DPA Poly_DRC Poly Acive_DRC DPA = Min polyactive spacing No overlap .

Markers at marker layers are polygons that may indicate: Regions excluded from circuit extraction (e. I/O pads).g. Devices that cannot be recognized in the usual way (e.IDESA . Regions excluded from other actions (e. dummy fill insertion). I/O pads). Regions selected for some action (e.g. digital part of the chip and analog part of the chip).g. Regions excluded from DRC (e. Wieslaw Kuzmicz .g. dummy fill insertion).IC Design Skills for Advanced DSM Technologies Marker layers Marker layers: auxiliary layers for better control of circuit extraction and DRC.g.Warsaw University of Technology © IDESA 2008 | 10 . Regions that should be treated separately (e. inductors).g.

R=15Ω 1 2 R2 = Rmet1+Rcont +RSD GND M1.120/90 3 Nominal extraction (MOS devices only) 3 R1 = Rmet1+Rcont +RSD R3 = Rpoly NMOS_SD_contact property: resistive.Warsaw University of Technology © IDESA 2008 | 11 . L=90nm.IDESA . Rs=10Ω/ NMOS_S/D property: resistive. Rs=9Ω/ 4 2 1 GND M1. W=120 nm Metal1 property: resistive.120/90 3 Extraction with parasitic resistances Wieslaw Kuzmicz .IC Design Skills for Advanced DSM Technologies Circuit extraction Device recognition and connectivity analysis: MOS devices and resistors NMOS_channel property: MOS device. Rs=0.09Ω/ 1 Poly property: 2 resistive.

IC Design Skills for Advanced DSM Technologies Circuit extraction Device recognition and connectivity analysis: some exceptions Connection exists No connection Connection exists No connection Wieslaw Kuzmicz .IDESA .Warsaw University of Technology © IDESA 2008 | 12 .

Warsaw University of Technology © IDESA 2008 | 13 .contact area) Wieslaw Kuzmicz .IC Design Skills for Advanced DSM Technologies Circuit extraction Device recognition and connectivity analysis: capacitors C: M1 to poly capacitance (area = overlap area) R: contact resistance C negligible R negligible C: M1 to poly capacitance (area = overlap area .IDESA .

35.IDESA .. MOS device model added from the PDK R1 5 R3 6 1 2 GND M1.MODEL NCH NMOS LEVEL=14 VTO=0.120/90 3 R2 7 M1 1 2 3 GND NCH W=120E-9 L=90E-9.. Wieslaw Kuzmicz ..IC Design Skills for Advanced DSM Technologies Circuit extraction Creating netlist From analysis of the database of layers (primary and derived) 1 2 GND M1...35.Warsaw University of Technology © IDESA 2008 | 14 . . R1 1 5 27 Resistances calculated by R2 3 7 30 the extractor R3 2 6 33 .MODEL NCH NMOS LEVEL=14 VTO=0..120/90 3 M1 1 2 3 GND NCH W=120E-9 L=90E-9...

IC Design Skills for Advanced DSM Technologies Circuit extraction Parasitic capacitances in DSM technologies Old technologies: lateral dimensions much larger than vertical ones. DSM technologies: lateral and vertical dimensions comparable. Wieslaw Kuzmicz . many more metal layers.IDESA . Computational complexity of true 3D multilayer capacitance extraction is very high.Warsaw University of Technology © IDESA 2008 | 15 . lateral capacitances no longer negligible. lateral capacitances negligible compared to interlayer (vertical) ones. Extractors simplify this process extracting only “short range” capacitances.

IC Design Skills for Advanced DSM Technologies Circuit extraction Parasitic capacitances in DSM technologies Example: capacitances extracted by Calibre® xRC tool: Lateral single layer capacitance Metal2 Plate capacitance Lateral interlayer capacitance Fringe capacitance Metal2 Fringe capacitance Plate capacitance Metal1 Fringe capacitance Plate capacitance Semiconductor Wieslaw Kuzmicz .Warsaw University of Technology © IDESA 2008 | 16 .IDESA .

resistances of all conducting paths on all layers.IDESA .netlist reduction Extraction of all components (MOS devices.Warsaw University of Technology © IDESA 2008 | 17 . C and D components. Only few of them affect operation of the circuit! Netlist reduction performed by extractors is rather limited.IC Design Skills for Advanced DSM Technologies Circuit extraction Too many components . all interlayer and lateral capacitances and all diodes) creates huge netlists. a wise selection must be made! Wieslaw Kuzmicz . Example: “full” extraction of a simple opamp gives a netlist with 1162 R. NMOS devices: 6 PMOS devices: 3 Diodes: 29 Capacitors: 69 Resistors: 1064 It doesn’t make sense to extract everything.

in the “off” state in most cases.IC Design Skills for Advanced DSM Technologies Circuit extraction: special cases Bipolar devices in CMOS circuits Every NMOS device is also a lateral bipolar npn transistor.Warsaw University of Technology © IDESA 2008 | Collector 18 . n p n p n p p Extraction would add huge number of bipolar devices to the netlist. Every PMOS device on a n-well is also a lateral pnp bipolar transistor. In DSM technologies base width of this device is below 100 nm. Intentionally used bipolar transistors are usually precharacterized library components. and source and drain regions create substrate pnp transistors. Emitter They are often represented by subcircuits in the netlist.IDESA . not easily scalable. Therefore bipolar devices are usually not extracted. Base Grey shape: marker layer “this is bipolar transistor” Wieslaw Kuzmicz .

pn junctions blocking eddy currents). Normally these inductances are very small and can be neglected even in RF circuits. proximity of other wires. extractors do have tools for estimation of parasitic inductances. uncertain return path). However. often represented by subcircuits in the netlist.g. and it is even more difficult to calculate their inductance and Q-factor. They are usually pre-characterized library components. Inductors are shaped as spiral metal wires. Wieslaw Kuzmicz .IC Design Skills for Advanced DSM Technologies Circuit extraction: special cases Inductors and parasitic inductances There is no simple and accurate way to find parasitic inductance of an interconnection wire over a semi-conducting substrate in the vicinity of other wires (skin effect. often over special patterns on other layers (e.Warsaw University of Technology © IDESA 2008 | 19 . it is not easy to extract such structures as inductors automatically.IDESA . Blue shape: marker layer “this is an inductor” Inductors are not easily scalable. Although they are easily recognized by a human.

– Sufficiently accurate if distance larger than 1/10 of the inductor’s dimensions Point-to-point inductance extraction – Extracts self-inductance of single paths – Endpoints (“driver” and “receiver”) must be specified on the layout – Performed for paths longer than 100 µm Wieslaw Kuzmicz .Warsaw University of Technology © IDESA 2008 | 20 .IC Design Skills for Advanced DSM Technologies Circuit extraction: special cases Example: inductances in Calibre® xL tool .IDESA .some options Inductance ERC – Intended to estimate magnetic noise due to mutual inductance of intentional inductors. finds the magnetic noise parameter K defined as the ratio of the mutual inductance between two intentional devices normalized to the geometric mean of the two self inductances.

some options Self.IC Design Skills for Advanced DSM Technologies Circuit extraction: special cases Example: inductances in Calibre® xL tool .Warsaw University of Technology © IDESA 2008 | 21 .IDESA .and mutual inductance extraction – Intended to estimate the effect of magnetic coupling between long parallel paths – “Aggressor” and “victim” paths must be identified: for a given victim all paths within a tube of radius R (default = 60 µm) are aggressors aggressor path R victim path not aggressor path aggressor path Wieslaw Kuzmicz .

34E-14 D2 MN2 3 4 5 0 Nchan W=325E-9 L=65E-9 +PD=1040E-9 AD=6. MN1 1 2 3 0 Nchan W=325E-9 L=65E-9 +PD=1040E-9 AD=6.extraction and modeling If source/drain diodes of MOS devices are treated as internal parts of these devices.Warsaw University of Technology © IDESA 2008 | 22 .IDESA . It is safer to treat source/drain diodes as separate devices. MOS models must not include them.34E-14 G2 S2 D2 G1 G2 S2 and D1 G1 S1 S1 D1 OK for layout 1 (separate source2 and drain1) Wrong for layout 2 (shared source2/drain1) Area and perimeter of the shared D1/S2 diode overestimated -> overestimated capacitance and leakage current. Wieslaw Kuzmicz . it is difficult to avoid ambiguities.IC Design Skills for Advanced DSM Technologies Circuit extraction: special cases Parasitics in MOS devices . If they are extracted separately.

S/D resistances and capacitances) included.Warsaw University of Technology © IDESA 2008 | 23 . The extractor must not extract any parasitics inside the p-cell. p-cell: no parasitics extraction inside (included in device model) Outside p-cell: extraction of parasitic R and C Wieslaw Kuzmicz . with parasitics (e.g. The devices designed using p-cells have models parametrized to match the device layout.extraction and modeling A way to avoid ambiguities is to use parametrized device cells (p-cells).IC Design Skills for Advanced DSM Technologies Circuit extraction: special cases Parasitics in MOS devices .IDESA .

Such isolated shapes are common in DSM layouts. The last two options are “safe” for circuit simulation. Metal1 connection Isolated piece of metal2 Floating net Circuit simulators usually don’t accept floating nets (their potential is undefined). Connect floating nets to ground.IDESA . Extractors offer several options: Extract floating nets and leave them in the netlist. but either underestimate or overestimate the total interconnect parasitic capacitance. Extract floating nets together with their net-to-ground capacitances. Extract floating nets but delete them from the netlist.IC Design Skills for Advanced DSM Technologies Circuit extraction: special cases Floating nets Isolated shapes on conducting layers may be extracted as capacitors with one terminal disconnected.Warsaw University of Technology © IDESA 2008 | 24 . Wieslaw Kuzmicz .

IDESA . or Wieslaw Kuzmicz . Coupling capacitance between adjacent paths can be included.IC Design Skills for Advanced DSM Technologies Circuit extraction: special cases Distributed RC networks Extractors offer option to extract long interconnects as RC networks.Warsaw University of Technology © IDESA 2008 | 25 .

Extractors know very little about real 3D structures of ICs. special markers are used to indicate these devices. usually pre-defined.Warsaw University of Technology © IDESA 2008 | 26 .IC Design Skills for Advanced DSM Technologies Circuit extraction . Some devices are not easily scalable. Extractors do not do any simulation of active devices. Resistances and capacitances are calculated from layer physical properties and device geometry.summary Extraction is a set of logical and geometrical operations on 2D geometrical objects. Extraction of some classes of devices requires understanding of the intention of the designer.good understanding of circuit and device operation is needed to select proper layout and extraction options in order to obtain realistic postlayout simulation results. usually simple formulas are used for computational efficiency. Wieslaw Kuzmicz .IDESA . Extraction in analog and RF domains is not “automatic” .

area of poly and/or metal connected to MOS gates to avoid thin oxide breakdown due to ion-induced charge Layer density rules: min. density of layout features for process uniformity DfM (recommended) rules: yield enhancing recommendations Wieslaw Kuzmicz . overlap.IDESA . enclosure. extension Voltage dependent rules: min.Warsaw University of Technology © IDESA 2008 | 27 .IC Design Skills for Advanced DSM Technologies DRC Simple geometrical rules: min. width. spacing depending on the bias voltage Current density rules: min. metal width necessary for a given average or pulse current Latchup rules: to prevent latchup Antenna rules: max. and max. spacing.

IDESA .Warsaw University of Technology © IDESA 2008 | 28 . and max.IC Design Skills for Advanced DSM Technologies DRC Simple geometrical rules a c b d e a: minimum width b: minimum spacing (same or different layers) c: minimum enclosure d: minimum overlap e: minimum extension f: min. dimension (usually contact cuts) f In DSM technologies: • more rules per layer • many more layers (10+ metal layers) -> huge total number of rules In DSM technologies layer width and spacing are often not independent: larger width -> larger minimum spacing Wieslaw Kuzmicz .

width in spiral inductors: 1.19 µm d: min.5 < w < 5.0 a b c: min. spacing in spiral inductors: 1.2 1.20 < w < 1.0 1.Warsaw University of Technology © IDESA 2008 | 29 .19 µm e: min.example (metal rules) Old technology: simple a: minimum width 1 µm b: minimum spacing 1 µm DSM technology: no longer simple a: minimum width 0.5 5.IC Design Skills for Advanced DSM Technologies DRC Simple geometrical rules .5 µm f: min.20 0.15 µm b: minimum spacing: for width w (µm) min.15 0. spacing for 45° path: 0.5 µm c a b d Wieslaw Kuzmicz . width for 45° path: 0.0 < w 5.5 0.IDESA . spacing (µm) w < 0.

DRC tools don’t know anything about voltages in the circuit. Wieslaw Kuzmicz . Such rules.g.Warsaw University of Technology © IDESA 2008 | 30 . e.IC Design Skills for Advanced DSM Technologies DRC Voltage dependent rules A d1 B d2 C Minimum spacing may depend on the voltage applied. are difficult to verify . if exist. d1 < d2 if A and B are at the same potential while B and C are not.IDESA .

currents in minimum size metal paths in DSM circuits are very low! Wieslaw Kuzmicz . This also reduces contact or via resistance.Warsaw University of Technology © IDESA 2008 | 31 . multiple contacts or vias must be used. If the maximum current exceeds such a limit.IC Design Skills for Advanced DSM Technologies DRC Current density rules Minimum metal width depends on the lithography resolution and on the maximum current density (determined by reliability considerations). improves yield and reliability. Max.IDESA . special tools exist in EDA toolsets for design of power nets in large VLSI circuits. However. DRC tools do not verify the current density. Large widths may be necessary for power and ground nets. Current is also limited in contacts and vias.

5 * IDC 30 * IDC M3 4*(W-0.02) 7. pulse.02) 1*(W-0.width in µm All metal layers are copper layers Wieslaw Kuzmicz . IDC (mA) Layer no.02) 0.5*(W-0.02) 1*(W-0.5*(W-0.02) 5 * IDC 20 * IDC M7 10*(W-0.02) 7.example The maximum current density is a function of metal path width and thickness.IDESA .02) 1*(W-0.5 * IDC 30 * IDC M4 4*(W-0.02) 2.Warsaw University of Technology © IDESA 2008 | 32 .75*(W-0.02) 15 * IDC 60 * IDC M2 4*(W-0.02) 2.02) 5 * IDC 20 * IDC W .02) 1*(W-0. 105°C Ipeak (mA) 125°C 105°C 125°C M1 3*(W-0.5 * IDC 30 * IDC M5 4*(W-0.02) 7.IC Design Skills for Advanced DSM Technologies DRC Current density rules .02) 7.5 * IDC 30 * IDC M6 10*(W-0. current waveform (DC. sinusoidal…) and maximum operating temperature.

IDESA . Example of DSM latchup rule: max. Therefore the general rule to avoid latchup is very simple: make the substrate equipotential using as many contacts to the ground node (for p-wells or p-type substrate) or the VDD node (for n-wells) as possible.IC Design Skills for Advanced DSM Technologies DRC Latchup rules Latchup may occur when at least one of the source/drain pn junctions of MOS devices becomes forward biased.Warsaw University of Technology © IDESA 2008 | 33 . Wieslaw Kuzmicz . distance from the body contact to the boundaries of source/drain regions < 25 µm. For I/O cells guard rings connecting the well or substrate to VDD or ground are used. In a well designed circuit this may happen when the substrate is non-equipotential due to transient currents flowing in it.

Antenna rules specify the maximum area of conducting layers (poly and metal) that can be safely connected to MOS device gates. Ions n p n Antenna error: too large metal1 area Wieslaw Kuzmicz .IC Design Skills for Advanced DSM Technologies DRC Antenna rules Plasma processes (e. no danger exists. This charge may destroy thin gate oxide in MOS devices during fabrication.g.Warsaw University of Technology © IDESA 2008 | 34 . If the total area (sum of areas of all layers exposed to ions) is not too big. reactive ion etching) result in accumulation of charge on conducting paths.IDESA .

IC Design Skills for Advanced DSM Technologies DRC Antenna rules Ion induced damage will not occur if ion charge is drained by a diode connected between the conducting “antenna” and semiconductor substrate. However. during fabrication such a connection may not exist yet when a big conducting “antenna” is already attached to a MOS device gate. m2 does not exist yet. n p n n In CMOS circuits all transistor gates are connected to such diodes in completed circuit. n n n p Wieslaw Kuzmicz .IDESA .Warsaw University of Technology © IDESA 2008 | 35 . m2 Damage during m1 m1 etching.

Warsaw University of Technology © IDESA 2008 | 36 .IDESA .IC Design Skills for Advanced DSM Technologies DRC Antenna rules Antenna effect prevention when a large conducting area must be connected to a gate: m2 m1 Diode insertion n Area too small to collect dangerous charge n n p n Bridging m2 m1 p n n Wieslaw Kuzmicz .

example Maximum ratio R of the area of the conducting layer (“antenna”) connected to the gate to the area of the gate for unprotected gates (no diode): R= Aantenna Agate For poly (area): R < 200 For poly (sidewall area): R < 450 For metal (cumulative area): R < 1000 where Poly sidewall area = poly perimeter * poly thickness Metal cumulative area = sum of areas of all metal layers Wieslaw Kuzmicz .IC Design Skills for Advanced DSM Technologies DRC Antenna rules .Warsaw University of Technology © IDESA 2008 | 37 .IDESA .

IDESA . dummy fills (extra shapes) are added where needed. crucial in DSM processes): Copper is soft->fast polishing “Dishing” Ta is hard->slow polishing Ta barrier Copper To achieve uniform density. Wieslaw Kuzmicz .Warsaw University of Technology © IDESA 2008 | 38 . Density affects etching speed: Faster etching here Slower etching here Resist Density affects chemical-mechanical planarization (CMP.IC Design Skills for Advanced DSM Technologies DRC Layer density rules Fairly uniform density of mask features on some layers is a must for good process control.

density (60% .IC Design Skills for Advanced DSM Technologies DRC Layer density rules Usually min.30%) and max.Warsaw University of Technology © IDESA 2008 | 39 .IDESA . density (20% .80%) These numbers are layer-dependent Checks show areas where density rules are violated Dummy fills may be added: – manually – automatically (markers used to exclude some areas) – by the foundry (markers used to exclude some areas) Dummy fills on conductive layers affect parasitic capacitances In wide metal areas slots must be added or Wieslaw Kuzmicz .

IDESA . areas violating the density rule are indicated. Av.IC Design Skills for Advanced DSM Technologies DRC Layer density rules Layer density rules are checked in moving windows.Warsaw University of Technology © IDESA 2008 | 40 . density = 40%: wrong! Av. density = 40%: OK! Wieslaw Kuzmicz .

Warsaw University of Technology © IDESA 2008 | 41 .IC Design Skills for Advanced DSM Technologies DRC Layer density rules Dummy fills on active Wieslaw Kuzmicz .IDESA .

Warsaw University of Technology © IDESA 2008 | 42 .IC Design Skills for Advanced DSM Technologies DRC Layer density rules Dummy fills on poly Wieslaw Kuzmicz .IDESA .

IC Design Skills for Advanced DSM Technologies DRC Layer density rules Dummy fills on two metal layers Wieslaw Kuzmicz .IDESA .Warsaw University of Technology © IDESA 2008 | 43 .

They are usually not verified. Examples: • Recommended width and spacing larger than minimum • Same orientation for all shapes on the layer • Path spreading (equal distances) • Multiple contacts and vias wherever possible Wieslaw Kuzmicz .IC Design Skills for Advanced DSM Technologies DRC Recommended rules and DfM These rules help to maximize manufacturing yield.Warsaw University of Technology © IDESA 2008 | 44 .IDESA .

areas sensitive to spot defects. usually not available in ordinary PDKs.IC Design Skills for Advanced DSM Technologies DRC Recommended rules and DfM Analysis of critical area Critical area for shorts: area in the layout where a spot defect (extra piece of conducting material) of radius R creates a short Critical area for opens: area in the layout where a spot defect (missing piece of conducting material) of radius R creates a path break Some DRC tools offer critical area analysis.Warsaw University of Technology © IDESA 2008 | 45 . Wieslaw Kuzmicz . This allows to optimize the layout (minimize defect sensitivity). They are process-specific foundry proprietary data.IDESA . Visualization of critical areas helps to find “weak spots” in the layout . The defect density and defect size distribution are needed.

IDESA .IC Design Skills for Advanced DSM Technologies Layout postprocessing and mask data preparation Resolution Enhancement Techniques (RET) Subresolution Assist Features (SRAF) . by means of double exposure with two different masks) Layout postprocessing is normally performed by the foundry.g. reproduced with permission Wieslaw Kuzmicz .Warsaw University of Technology © IDESA 2008 | 46 .use phase shifts and interference to make subwavelength printing possible (e.predistortion of mask shapes in order to improve final (printed) shapes Phase Shifting Masks (PSM) . e. Brunet. OPC picture courtesy of J-M. 2006. IEEE Web Seminar. November 9.addition of unprintable mask features that improve lithography resolution.g. scattering bars Optical and Process Correction (OPC) .

modifications of the original layout beyond correction of simple DRC violations may be needed. Wieslaw Kuzmicz .IC Design Skills for Advanced DSM Technologies DRC .Warsaw University of Technology © IDESA 2008 | 47 .IDESA . DRC-clean designs not always guarantee high manufacturing yield. DfM-oriented layout analysis and layout postprocessing are theoretically possible (tools exist) but require deep processing knowledge and processspecific data normally not available for the designer.summary DRC in DSM technologies is not just simple verification of geometry of layout features. Recommended rules provide guidelines how to improve the layout to make it more “litho-friendly”. To obtain a manufacturable design.

IC Design Skills for Advanced DSM Technologies .