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ABSTRACT
Serial communications is the process of sending data one bit at one time,
sequentially, over a communication channel or computer bus. Serial
communications is used for all long haul communications and most computer
networks, where the cost of cable and synchronization difficulties make parallel
communications impractical. Serial transmission is commonly used with
modems and for non-networked communication between computers, terminals
and other devices. The Universal Asynchronous Receiver/Transmitter (UART)
controller is the key component of the serial communications subsystem of a
computer. The UART takes bytes of data and transmits the individual bits in a
sequential fashion. At the destination, a second UART re-assembles the bits into
complete bytes.
As the name suggests UART transfer the data without any
synchronization signal , that is Receiver and Transmitter are self
synchronized no synchronization signal is sent between those.
We in this project try to develop an efficient UART Controller,
afterwards we will try to make it to work with different baud
rates and make it a power efficient mechanism.

Role Distribution Among Group members.


Piyush Gaur:- Design of the UART Transmitter, Its status registers and
documentation, also developed this initial report, bringing all the fellow
members together to work.

Sumant Gupta:- Design of the UART Receiver, its registers and


schematics and drawing of the block diagrams and documentation.

Priyadarshi Saxena:- Design of the Baud Rate generators and


synchronization, development of the final report.

CHAPTER 1

INTRODUCTION
UART - Universal Asynchronous Receiver/Transmitter

(UART) An integrated circuit used

for serial communications, containing a transmitter (parallel-to-serial converter) and a


receiver (serial-to-parallel converter), each clocked separately. The UART takes bytes of data
and transmits the individual bits in a sequential fashion. At the destination, a second UART
re-assembles the bits into complete bytes.

The UART's status register contains a flag bit which the computer can read to see if the
UART is ready to transmit another byte. Another status register bit says whether the UART
has received a byte from the serial line, in which case the computer should read it from the
receive data register (RDR).
Data on the serial line is formatted by the UART according to the setting of the UART's
control register. This may also determine the transmit and receive baud rates if the UART
contains its own clock circuits or "baud rate generators".
UART is the most commonly used host controller interface because of following reasons:

If UART is used software overhead is very less

Its highly cost effective.

Simple way to send data from one system to another system

Add functional to applications

1.1 Transmitting and receiving serial data


UART transmitter controls transmission by fetching a data word in parallel format and
directing the UART to transmit it in a serial format. Likewise, the Receiver must detect
transmission, receive the data in serial format, strip of the start and stop bits, and store the
data word in a parallel format.
Since the UART is asynchronous in working, the receiver does not know when the data will
come, so receiver generate local clock in order to synchronize to transmitter whenever start
bit is received. Communication may be "full duplex" (both send and receive at the same time)
or "half duplex" (devices take turns transmitting and receiving).

1.2 Character framing

Figure 1.1 A character in UART

Each character is sent as a logic low start bit, a configurable number of data bits (usually 7 or
8, sometimes 5), an optional parity bit, and one or more logic high stop bits. The start bit
signals the receiver that a new character is coming. The next five to eight bits, depending on
the code set employed, represent the character. Following the data bits may be a parity bit.
The next one or two bits are always in the mark (logic high, i.e., '1') condition and called the
stop bit(s). They signal the receiver that the character is completed. Since the start bit is logic
low (0) and the stop bit is logic high (1) then there is always a clear demarcation between the
previous character and the next one.

1.3 Asynchronous Serial Transmission:


Asynchronous transmission allows data to be transmitted without the sender having to send a
clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters
in advance and special bits are added to each word which are used to synchronize the sending
and receiving units.

When a word is given to the UART for Asynchronous transmissions, a bit called the "Start
Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is used to
alert the receiver that a word of data is about to be sent, and to force the clock in the receiver
into synchronization with the clock in the transmitter. These two clocks must be accurate
enough to not have the frequency drift by more than 10% during the transmission of the
remaining bits in the word.
After the Start Bit, the individual bits of the word of data are sent, with the Least Significant
Bit (LSB) being sent first. Each bit in the transmission is transmitted for exactly the same
amount of time as all of the other bits, and the receiver ``looks'' at the wire at approximately
halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. For
example, if it takes two seconds to send each bit, the receiver will examine the signal to
determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and then
examine the value of the next bit, and so on.The sender does not know when the receiver has
``looked'' at the value of the bit. The sender only knows when the clock says to begin
transmitting the next bit of the word.
When the entire data word has been sent, the transmitter may add a Parity Bit that the
transmitter generates. The Parity Bit may be used by the receiver to perform simple error
checking. Then at least one Stop Bit is sent by the transmitter.
When the receiver has received all of the bits in the data word, it may check for the Parity
Bits (both sender and receiver must agree on whether a Parity Bit is to be used), and then the
receiver looks for a Stop Bit. If the Stop Bit does not appear when it is supposed to, the
UART considers the entire word to be garbled and will report a Framing Error to the host
processor when the data word is read. The usual cause of a Framing Error is that the sender
and receiver clocks were not running at the same speed, or that the signal was interrupted.
Regardless of whether the data was received correctly or not, the UART automatically
discards the Start, Parity and Stop bits. If the sender and receiver are configured identically,
these bits are not passed to the host.
If another word is ready for transmission, the Start Bit for the new word can be sent as soon
as the Stop Bit for the previous word has been sent .Because asynchronous data is self
synchronizing, if there is no data to transmit, the transmission line can be idle.
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1.4 UART Errors


1.4.1 Overrun Error:
An "overrun error" occurs when the UART cannot process the byte that just came in before
the next one arrives. The host processor must service the UART in order to remove characters
from the buffer. If the host processor does not service the UART and the buffer becomes full,
then Overrun Error will occur.
1.4.2 Framing Error:
A "Framing Error" occurs when the designated "start" and "stop" bits are not valid. Start bit
acts as a reference for the remaining bits. When the "stop" bit is expected if the data line is
not in the expected idle state a Framing Error will occur.
1.4.3 Parity Error:
A "Parity Error" occurs when the number of "active" bits does not agree with the specified
parity configuration of the UART.
1.4.4 Under run error:
In "underrun error" occurs when the UART transmitter has completed sending character and
the transmit buffer is empty. In asynchronous modes this is treated as an indication that no
data remains to be transmitted, rather than an error, since additional stop bits can be
appended. This error indication is commonly found in USARTs, since an underrun is more
serious in synchronous systems.

CHAPTER 2

SPECIFICATION and IMPLEMENTATION


2.1 Block Diagrams and Schematics.
We propose to implement a UART module containing both in order to provide full duplex
operation of the UART and to design it to act as both transmitter and as a receiver when
configured accordingly. We plan to test this circuit by transmitting from one module and
receiving from the other one.

2.2.1 Transmitter

Figure 2.1 block of a transmitter and Waveform.


Figure 2.1 clearly shows the transmitter block, this is used to transmit parallel data which is
input at din pin.
1. rst pin is for resetting the system.
2. clk16x is the input clock which is 16 times the system clock.
3. parity_def this pin is used to describe the odd or even parity.
4. wr is used to enable the transmitter.
5. din is the input data to be transmitted.
6. sdo is the serial data output starting with the start bit then data and parity and stop bit.
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7.tbre is pulled down to 0 when tx or transmitting shift register is empty.

2.2.2 Receiver

Detection of the Start


Bit.

Figure 2.2 Receiver Block and its Waveform.


Figure 2.2 shows the receiver block to receive the incoming serial data, clk16x and
parity_def, rst has the same meaning as in transmitter.
1. rxd is used to receive serial data.
2. rd is used to enable the receiver.
3.data_rdy is high when output is ready.
4Framing_error occurs when there is an framing error.

5 Parity error occurs when the data is corrupt.


4.3.3 UART
This is the topmost block which contains both the receiver and transmitter and pins for their
configuration, that is whether it should act as a receiver or transmitter at a particular time. It
also contains the baud rate generator and synchronization circuit for the 16xclk and
data.

Figure 2.3 A UART module containing Transmitter and receiver.

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Figure 2.4 BLOCK Diagram of the whole scheme with baud rate generators.

Figure 2.5 FSM of the Transmitter.

Figure 2.6 FSM of the Receiver

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CHAPTER 3

RTL Schematics And Simulation


Results.
A uart module containing both a transmitter and a receiver was implemented, it was done in
order to provide full duplex operation of the UART and was designed to act as both
transmitter and as a receiver when configured accordingly.

3.1 RTL Schematic of the transmitter.


Equal1
A[3..0]
B[3..0]

cnt_byte~[11..8]

EQUAL
SEL

B[3..0]

DATAA
4' hF --

OUT0

DATAB

DATAB

4' h7 --

cnt_clk~[7..4]

Add0
A[3..0]

cnt_clk[3..0]

SEL

DATAA
DATAB

B[3..0]

OUT0

DATAA
DATAB

PRE
OUT0

4' h1 --

A[3..0]
B[3..0]

ADDER
cnt_clk~[3..0]

Equal2

ENA
MUX21

CLR

A[3..0]

4' hB --

B[3..0]

MUX21

CIN

4' h8 --

LessThan1

tsr[7..0]

parity~3

always2~0

DATAA
1' h0 --

LESS_THAN

DATAB

always1~0

=
EQUAL

Equal0

Equal5
4' h9 --

B[3..0]

EQUAL

parity~5

sdo~2

ENA

SEL
DATAA

DATAA
DATAB

4' h0 --

B[3..0]

sdo

tbre~reg0
0

0 1

1 1

tbre~0

tbre~1

PRE
D

tbre

ENA

=
=
EQUAL

MUX21

PRE
D

ENA

MUX21

tbr[7..0]
din[7..0]
clk16x

sdo~4

PRE
D

OUT0

OUT0

DATAB

sdo~3

sdo~reg0
0
0 1

CLR

A[3..0]

4' h0 --

CLR

EQUAL
Equal4

cnt_byte~[3..0]

CLR

CLR

A[3..0]

parity~4

SEL
OUT0

MUX21

Equal6
B[3..0]

PRE

ENA

A[3..0]

A[3..0]

PRE
D

parity~2
tsr~[7..0]

parity~0

SEL

<

MUX21

B[3..0]

CLR

4' hA --

4' hF --

0
1

parity~1

1
B[3..0]

OUT0

DATAB

parity

sdo~1

EQUAL

SEL
DATAA
4' h0 --

0 1

sdo~0

tsr~[15..8]

EQUAL

ENA

1 1

PRE
OUT0

<

A[3..0]

wr

LessThan0

LESS_THAN
MUX21

cnt_byte[3..0]

SEL

Equal3
A[3..0]

MUX21

B[3..0]

cnt_byte~[15..12]

SEL
DATAA

ADDER

4' h1 --

CIN

A[3..0]

4' h1 --

4' hF --

cnt_byte~[7..4]

Add1

ENA
CLR

rst

parity_def

Figure 3.1 RTL Schematic of the Transmitter

In this schematic the registers for holding the data tsr, and registers for
storage of count, parity and serial data can be easily seen, rest circuitry
acts as the assist for the generation of start, party and stop bit, also it

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increases the time between each transmission and keeps the track of it so
that receiver can sample the data in between that duration.

3.2 RTL Schematic of the Receiver.


cnt_clk~[7. 4]
cnt_byte~[7. 4]

Add1
4' h1 --

cnt_byte~[15..12]
CIN

A[3..0]

SEL

SEL

B[3..0]

cnt_byte~[11..8]

DATAA
4' hF --

DATAB

DATAA
OUT0

OUT0

DATAB

DATAA
DATAB

A[3..0]

OUT0

4' h1 --

B[3..0]

MUX21

always2~0

CLR

4' h8 --

rst

LessThan1

B[3..0]

4' h0 --

DATAB

DATAA
DATAB

OUT0

DATAA
DATAB

MUX21

parity_error~0

B[3..0]

0
1

always3~0

DATAA
DATAB

<

parity_error~1

EQUAL

Equal1

OUT0

always0~0

A[3..0]

4' hA --

B[3..0]

1 1

MUX21

dat_rdy~0

EQUAL

parity~0

parity~1

parity

0
0 1

dat_rdy~1

PRE

rbr[7. 0]

SEL
OUT0

DATAA
DATAB

PRE
OUT0

MUX21

dout[7. 0]~reg0

SEL
DATAA
DATAB

PRE
OUT0

dout[7. 0]

ENA

ENA

MUX21

CLR

dout~[7. 0]

rbr~[23..16]

SEL

SEL

EQUAL
Equal
6

OUT0

A[3..0]

4' h7 --

SEL
DATAA

PRE

ENA

rsr~[7. 0]

A[3..0]

4' h0 --

ADDER

PRE
OUT0

MUX21

Equal5

cnt_byte~[3. 0]

rxd[2. 1]
D

B[3..0]

MUX21

DATAB

CLR

LESS_THAN

A[3..0]

DATAA

rbr~[15..8]

SEL

Equal4

A[3..0]

EQUAL
Add0

4' h1 --

B[3..0]

CIN

OUT0

DATAB

MUX21

EQUAL

SEL
DATAA
4' h0 --

A[3..0]

cnt_clk~[3..0]

Equal3

B[3..0]

DATAB

PRE
OUT0

rsr[7. 0]

SEL

ENA

A[3..0]
B[3..0]

<
Equal2

4' hF --

EQUAL

4' hF --

DATAA

ENA

MUX21

MUX21

B[3..0]

PRE

A[3..0]

cnt_clk[3. 0]

SEL

LESS_THAN

Equal
ADDER 0
4' hA --

cnt_byte[3. 0]

SEL

LessThan0

rbr~[7. 0]

rsr~[15..8]

MUX21

CLR

CLR

parity_error~reg0

parity_error~2
dat_rdy~reg0
PRE

parity_error~3

PRE
D Q

parity_error

ENA
CLR

D Q

ENA
CLR

D Q

ENA

dat_rdy

CLR

A[3..0]

rxd
clk16x

0
ENA
CLR

framing_error~0

MUX21

4' h9 --

B[3..0]

=
EQUAL

0
1

framing_error~1

0
1

framing_error~2

framing_error~reg0
0
1

framing_error~3

PRE
D Q

framing_error

ENA
CLR

rd
parity_def

Figure 3.2 RTL Schematic of the Receiver

In the receiver also the registers for storing data can be easily seen and it
can be observed that at rsr register used for storing data the enable pin is
connected to the cnt_byte output which is designed in such a way to
sample the data in the midway of the duration of a single bit. Rest
circuitry is there to sample and check the different error conditions. The
reisters and circuitry for that can be easily seen.

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3.3 RTL Schematic of the UART.


clkdiv_cnt~[8..0]

Add0
A[8..0]

9' h001 --

B[8..0]

DATAB

ADDER

Equal5
B[1..0]

PRE
OUT0

Equal0

23' h000000 -A[31..0]

Q
32' h00000008 --

B[31..0]

=
EQUAL

Equal4

ENA
MUX21

0
EQUAL

CLR

Equal1

23' h000000 --

A[1..0]

2' h3 --

clkdiv_cnt[8..0]

SEL
DATAA
9' h000 --

A[31..0]

32' h00000004 --

B[31..0]

0 1

clk16x~0

clk16x
0
1 1

clk16x~1

uart_tx:U_TX

PRE
D

clk16x_b1
ENA

PRE
D

clk16x_nege

wr_pls~[4. 3]
wr_pls ~[2 . 1]

DATAA
SEL

CLR

always4~0 2' h0 --

DATAA

wr_pls ~[6. 5]

2' h3 --

DATAA
2' h1 --

OUT0

DATAB

SEL
OUT0

DATAB

wr_pls [1..0]
PRE

SEL

CLR
ENA

EQUAL

clk16x

always4~1

OUT0

DATAB

B[1..0]

=
always3~1

2' h3 --

B[1..0]

DATAB

SEL
DATAA

EQUAL

always3~0 2' h0 --

DATAB

A[1..0]

2' h1 --

B[1..0]

din[7..0]

OUT0

MUX21

OUT0

DATAA
2' h1 --

DATAB

rd_pls[1..0]
D

OUT0

clk16x
parity_def
rd
rst

ENA

int_uart_tr

CLR

PRE

SEL

int_uart_tr~0

ENA

uart_rx:U_RX

rd_pls~[6..5]

SEL
DATAA
2' h3 --

Equal2

PRE

tbre

wr

MUX21

rd_pls~[4..3]

MUX21

rd_pls~[2..1]

A[1..0]

tbre_b1

sdo

rst

CLR
MUX21

Equal3
EQUAL

parity_def

ENA

A[1..0]

2' h1 --

rxd

dat_rdy_b1
PRE
dat_rdy

int_uart_re~0

int_uart_re

framing_error
parity_error
dout[7..0]

ENA
CLR

CLR

tbre
dat_rdy
data_out[7..0]
parity_error
framing_error
txd

MUX21

MUX21

EQUAL

rxd
rst
rd
parity_def
wr
clk
data_in[7..0]

Figure 3.3 RTL Schematic of the UART

In this schematic both transmitter and receiver blocks can be easily seen in the freen coloured
box, rest circuitry is to generate the baud clock and to synchronize the wr , and rd signal
according to the incoming data rate.

3.4 RTL Schematic of the Tranceiver.

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uart:Receiver
clk2
parity_def2
rd2
rst2

clk
parity_def
rd
rst
rxd

wr2
data_in2[7..0]

wr
data_in[7..0]

uart:transmitter
dat_rdy
framing_error
int_uart_re
int_uart_tr
parity_error
tbre
txd
data_out[7..0]

clk
parity_def
rd
rst
rxd
wr
data_in[7..0]

dat_rdy
framing_error
int_uart_re
int_uart_tr
parity_error
tbre

dat_rdy1
framing_error1
int_uart_re1
int_uart_tr1
parity_error1
tbre1

txd
data_out[7..0]

data_out1[7..0]

tbre2
parity_error2
data_out2[7..0]
int_uart_tr2
int_uart_re2
framing_error2
dat_rdy2
wr1
rst1
clk1
rd1
data_in1[7..0]
parity_def1

Figure 3.4 RTL Schematic of the Tranceiver

Two UART block connected in such a way that one acts as a transmitter and another as a
receiver showing duplex operation.

3.4 Simulation Results.

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Figure 3.5 Simulation Results of the Tranceiver

The highlighted part in the results describes the serial data transmission of the Din, wr
synchronization, clk16x and the data out on the reception of the data an data ready getting
high to flag it. Here the data is synchronized so parity error and framing error signals are low.

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Figure 3.6 Simulation Results of the Tranceiver with error

Here we differ the clocks of the transmitter and the receiver and this resulted in the framing
error flag being high on the reception of the corrupted data.

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CHAPTER 4

Future Scope and Tools Used.


1. The design could be made power efficient by clock gating, that is
whenever there is a transmission or reception request the clock
should get on otherwise not.
2. A FIFO could be used for the incoherent data rates.
3. Asynchronous hand shaking signals can be implemented using LC
controllers.
4. Tools used were QUARTUS II and XILINX ISE.

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