Sequential Circuits

Introduction
A sequential circuit consists of a feedback p q f path, and employs some memory elements.
Combinational outputs Memory outputs

Combinational logic

Memory y elements

External inputs

Sequential circuit = Combinational logic + Memory Elements

Introduction
There are two types of sequential circuits:
synchronous: outputs change only at specific ti h t t h l t ifi time asynchronous: outputs change at any time

Multivibrator: l M lti ib t a class of sequential circuits. Th can b f ti l i it They be:
bistable (2 stable states) monostable or one-shot (1 stable state) one shot astable (no stable state)

Bistable logic devices: latches and flip-flops flip flops. Latches and flip-flops differ in the method used for changing their state state.

Memory Elements
Memory element a device which can remember value element: indefinitely, or change value on command from its inputs.

command d

Memory element l t

Q stored value d l

Characteristic table:
Command (at time t) Set Reset Memorise / No Change Q(t) X X 0 1 Q(t+1) 1 0 0 1
Q(t): current state Q(t+1) or Q+: next state

Memory Elements
Memory element with clock Flip flops are memory clock. Flip-flops elements that change state on clock signals.
command d Memory element Q stored value t d l

Clock Cl k is usually a square wave. ll

clock

Positive pulses

Positive edges

Negative edges

S-R Latch
Characteristics table for active high input S R latch: active-high S-R
S R 0 1 0 1 Q Q' No change. Latch remained in present state. Latch SET. Latch RESET. Invalid condition. Invalidcondition
S R Q Q'

0 NC NC 0 1 1 1 0 0 0 1 0

Characteristics table for active-low input S'-R' latch:

S' R' 1 0 1 0 1 1 0 0

Q

Q'
S R Q Q'

No change Latch change. NC NC remained in present state. 1 0 Latch SET. 0 1 Latch RESET. 1 1 Invalid condition.

S-R Latch
Active-HIGH i t S R latch A ti HIGH input S-R l t h

10 100 R

Q 11000 Q' 0 0 1 1 0

10 001 S

Active-LOW input S’-R’ latch

S 1 0 0 0 1

R 0 0 1 0 1

Q Q Q' 1 0 initial 1 0 (afer S=1, R=0) 0 1 0 1 (after S=0, R=1) 0 0 invalid!

S'

Q Q'

R R'

S S'

Q Q Q'

R'

S' R' 1 0 1 1 0 1 1 1 0 0

Q Q' 0 1 initial 0 1 (afer S'=1, R'=0) 1 0 1 0 (after S'=0, R'=1) 1 1 invalid! i lid!

Gated S-R Latch
S-R latch + enable input (EN) and 2 NAND p ( ) gates → gated S-R latch.

S Q EN Q Q' R
S EN R Q' Q

Gated D Latch
Make R input equal to S' → gated D latch. D latch eliminates the undesirable condition of invalid state in the S-R latch.

D Q EN Q Q'
D EN Q' Q

Gated D Latch
When EN is HIGH HIGH,
D=HIGH → latch is SET D=LOW → latch is RESET

Hence when EN is HIGH, Q ‘follows’ the D (data) input. Characteristic table:
EN 1 1 0 D 0 1 X Q(t 1) Q(t+1) 0 1 Q(t) Reset Set No change

When EN=1, Q(t+1) = D

Edge-Triggered Flip-flops
Flip-flops: synchronous bistable devices Output changes state at a specified point on a triggering input called the clock. Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock signal.

Clock signal
Positive edges Negative edges

Edge-Triggered Flip-flops
S-R, D and J-K edge-triggered flip-flops. Note the “>” symbol at the clock input.

S C R

Q Q'

D C

Q Q'

J C K

Q Q'

Positive edge-triggered flip-flops
S C R Q' D C Q' J C K Q'

Q

Q

Q

Negative edge-triggered flip-flops g g gg p p

J-K Flip-flop
J K flip flop: J-K flip-flop: Q and Q are fed back to the pulse steering Q' pulse-steering NAND gates. No invalid state. Include a toggle state.
J HIGH J=HIGH (and K=LOW) SET state K LOW) K=HIGH (and J=LOW) RESET state both inputs LOW no change both inputs HIGH toggle

J-K Flip-flop
J-K flip-flop.
J Pulse transition detector Q

CLK K

Q'

Characteristic table.
Q
J 0 0 1 1 K 0 1 0 1 CLK ↑ ↑ ↑ ↑ Q(t+1) Q(t) 0 1 Q(t)' Comments No change Reset Set Toggle

J 0 0 1 1 0 0 1 1

K 0 1 0 1 0 1 0 1

Q(t+1) 0 0 1 1 1 0 1 0

Q(t+1) = J Q' + K'.Q J.Q K Q

0 0 0 0 1 1 1 1

T Flip-flop
T flip-flop: single-input version of the J-K flip flop, formed by tying both inputs together.
T CLK Pulse transition t iti detector Q

T CLK

J C K

Q Q'

Q'

Characteristic table.
T 0 1 CLK ↑ ↑ Q(t+1) Q(t) Q(t)' Comments No change Toggle
Q T 0 0 1 1 0 1 0 1 Q(t+1) 0 1 1 0

Q(t+1) = T Q' + T'.Q T.Q T Q

T Flip-flop
Application: Frequency division.
High J CLK C K CLK Q CLK QA QB Q CLK High J C K QA High J C K QB

Divide clock frequency by 2.

Divide clock frequency by 4.

Application: Counter

Asynchronous Inputs
S-R, D and J-K inputs are synchronous inputs, as data on these inputs are transferred to the flip-flop’s output only on the triggered edge of the clock pulse pulse. Asynchronous inputs affect the state of the flip-flop independent of the clock; example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)] When PRE=HIGH, Q is immediately set to HIGH. , y When CLR=HIGH, Q is immediately cleared to LOW. Flip-flop Flip flop in normal operation mode when both PRE and CLR are LOW.

Asynchronous Inputs
A J-K flip-flop with active-LOW preset and clear inputs.
PRE J PRE Q Pulse transition t iti detector Q'

J C K

Q
CLK

Q'

K CLR

CLR CLK PRE CLR

J = K = HIGH

Q

Preset

Toggle

Clear

Introduction: Counters
Counters are circuits that cycle through a specified number of states. Two T types of counters: f
synchronous (parallel) counters asynchronous (ripple) counters

Ripple counters allow some flip-flop outputs to be used as a source of clock for other flip-flops. Synchronous counters apply the same clock to all flipflops.

Asynchronous (Ripple) Counters
Asynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse. Also known as ripple counters, as the input clock pulse pp , p p “ripples” through the counter – cumulative delay is a drawback. n n fl fl → a MOD (modulus) 2 counter. (Note: A flip-flops d l MOD-x counter cycles through x states.) Output of the last flip flop (MSB) divides the input clock flip-flop frequency by the MOD number of the counter, hence a counter is also a frequency divider.

Asynchronous (Ripple) Counters
Example: 2-bit ripple binary counter. p pp y Output of one flip-flop is connected to the clock input of the next more-significant flip-flop.
HIGH J CLK C K FF0 CLK Q0 Q0 0 Q1 0 1 0 0 1 1 1 0 0 1 2 3 4 Q0 Q0 J C K FF1 Q1

Timing diagram 00 → 01 → 10 → 11 → 00 ...

Asynchronous (Ripple) Counters
Example: 3-bit ripple binary counter.
HIGH J CLK C K FF0 Q0 Q0 J C K FF1 Q1 Q1 J C K FF2 Q2

CLK Q0 Q1 Q2 0 0 0

1 1 0 0

2 0 1 0

3 1 1 0

4 0 0 1

5 1 0 1

6 0 1 1

7 1 1 1

8 0 0 0 Recycles back to 0

Asynchronous (Ripple) Counters
Propagation delays in an asynchronous (ripple-clocked) binary counter. If the accumulated delay is greater than the clock pulse some pulse, counter states may be misrepresented!
CLK Q0 Q1 Q2 tPLH (CLK to Q0) tPHL (CLK to Q0) tPLH (Q0 to Q1) tPHL (CLK to Q0) tPHL (Q0 t Q1) to tPLH (Q1 to Q2) 1 2 3 4

Asyn. Asyn Counters with MOD no < 2 no.

n

States may be skipped resulting in a truncated sequence. Technique: force counter to recycle before g g through all q y f going g of the states in the binary sequence. Example: Given the following circuit, determine the counting sequence (and hence the modulus no.)
C
Q J

B

Q

J

A

Q

J

All J, K inputs are 1 (HIGH).

CLK K Q CLR

CLK K Q CLR

CLK K Q CLR

B C

Asyn. Asyn Counters with MOD no < 2 no.
Example (cont’d):
C
Q J

n

B

Q

J

A

Q

J

All J, K inputs are 1 (HIGH). (HIGH)

CLK K Q CLR

CLK K Q CLR

CLK K Q CLR

B C
1 2 3 4 5 6 7 8 9 10 11 12

Clock A B C NAND 1 Output 0

MOD-6 counter produced by clearing (a MOD-8 y ) binary counter) when count of six (110) occurs.

Asyn. Asyn Counters with MOD no < 2 no.
Decade counters (or BCD counters) are counters with 10 states (modulus-10) in their sequence. They are commonly used in daily life (e.g.: utility meters, y y ( g y , odometers, etc.). Design an asynchronous decade counter.

n

(A.C)' HIGH J CLK C K CLR Q D C B A

J C

Q

J C

Q

J C

Q

K CLR

K CLR

K CLR

Asyn. Asyn Counters with MOD no < 2 no.
Asynchronous decade/BCD counter (cont’d).
HIGH J CLK C K Q D J C K Q C J C K Q B J C K Q A

n

(A.C)' (A C)'

CLR

CLR

CLR

CLR

0

Clock D C B A NAND output
0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10

11

0 0 0

Cascading Asynchronous Counters
Larger asynchronous (ripple) counter can be constructed by cascading smaller ripple counters. Connect last-stage output of one counter to the clock input of next counter so as to achieve highe mod l s operation. achie e higher-modulus ope ation Example: A modulus-32 ripple counter constructed from a modulus-4 counter and a modulus-8 counter. Q Q Q Q Q
0 1 2 3 4

J CLK

Q

J

Q

J

Q

J

Q

J

Q

C Q' K

C K Q'

C Q' K

C K Q'

C K Q'

Modulus-4 counter

Modulus-8 counter

Cascading Asynchronous Counters
If counter is a not a binary counter, requires additional output. Example: A modulus-100 counter using two decade counters.
1 CLK freq CTEN Decade C freq/10 counter TC Q3 Q2 Q1 Q0 CTEN Decade C freq/100 counter TC Q3 Q2 Q1 Q0

TC = 1 when counter recycles to 0000 y

Synchronous (Parallel) Counters
Synchronous (parallel) counters: the flip flops are flip-flops clocked at the same time by a common clock pulse. We can design these counters using the sequential logic design process d i Example: 2-bit synchronous binary counter (using T flipflops, or JK flip-flops with identical J,K inputs).
Present state
00 01

Next state

Flip-flop inputs

11

10

A1 A0 0 0 0 1 1 0 1 1

A1+ A0+ 0 1 1 0 1 1 0 0

TA1 TA0 0 1 1 1 0 1 1 1

Synchronous (Parallel) Counters
Example: 2-bit synchronous binary counter (using T flipflops, or JK flip-flops with identical J,K inputs).
Present state Next state Flip-flop inputs

TA1 = A0 TA0 = 1

A1 A0 0 0 0 1 1 0 1 1

A1+ A0+ 0 1 1 0 1 1 0 0

TA1 TA0 0 1 1 1 0 1 1 1

1 J Q A0 J Q A1

C Q Q' K CLK

C Q K Q'

Synchronous (Parallel) Counters
Example: 3-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J, K inputs).
P res en t s ta te A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A 2+ 0 0 0 1 1 1 1 0 N ext s ta te A 1+ 0 1 1 0 0 1 1 0 A 0+ 1 0 1 0 1 0 1 0 TA 0 0 0 1 0 0 0 1 F lip - f lo p in p u t s TA1 TA 2 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
0

A1
1 1 1 1

A1
1 1 1 1 1

A1
1 1

A2 A0

1

A2

1

A2

1

A0

A0

TA2 = A1.A0

TA1 = A0

TA0 = 1

Synchronous (Parallel) Counters
Example: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1
A2 A1 A0

Q J K J

Q K J

Q K

CP 1

Synchronous (Parallel) Counters
Example: 4-bit synchronous binary counter.
TA3 = A2 . A1 . A0 TA2 = A1 . A0 TA1 = A0 TA0 = 1

1 J Q A0 J Q A1

A1.A0 J Q A2

A2.A1.A0 J Q A3

C Q' K CLK

C K Q'

C K Q'

C K Q'

Synchronous (Parallel) Counters
Example: Synchronous decade/BCD counter.
Clock pulse Initially 1 2 3 4 5 6 7 8 9 10 (recycle) Q3 0 0 0 0 0 0 0 0 1 1 0 Q2 0 0 0 0 1 1 1 1 0 0 0 Q1 0 0 1 1 0 0 1 1 0 0 0 Q0 0 1 0 1 0 1 0 1 0 1 0

T0 = 1 T1 = Q3'.Q0 T2 = Q1.Q0 T3 = Q2.Q1.Q0 + Q3.Q0

Synchronous (Parallel) Counters
Example: Synchronous decade/BCD counter (cont’d).
T0 = 1 T1 = Q3'.Q0 T2 = Q1.Q0 T3 = Q2.Q1.Q0 + Q3.Q0 Q Q Q
Q0 1 T C Q Q' T C Q Q' Q1 T C Q Q' Q2 T C Q Q' Q3

CLK

Up/Down Synchronous Counters
Example: A 3-bit up/down synchronous binary counter (cont’d).
TQ0 = 1 TQ1 = (Q0.Up) + (Q0'.Up' ) TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Q0 1 Up T C Q Q' T C Q Q'

Q1 T C Q Q' Q2

CLK

Introduction: Registers
An n-bit register has a group of n flip-flops and some logic gates and is capable of storing n bits of information. The flip-flops Th fli fl store the i f h information while the gates i hil h control when and how new information is transferred into the register. Some functions of register:
retrieve data from register store/load new d t i t register ( i l or parallel) t /l d data into i t (serial ll l) shift the data within register (left or right)

Simple Registers
No external gates. Example: A 4-bit register. A new 4-bit data is loaded every c oc cyc e. clock cycle.
A3 A2 A1 A0

Q D

Q D

Q D

Q D

CP I3 I2 I1 I0

Registers With Parallel Load
Instead of loading the register at every clock pulse, we may want to control when to l d l h load. Loading a register: transfer new information into the register. Requires a load control input. Parallel loading: all bits are loaded simultaneously.

Registers With Parallel Load
Load I0 Load A Load'.A0 + Load I0 Load.
D Q

A0

D Q

A1

I1

D Q

A2

I2

D Q

A3

I3 CLK CLEAR

Using Registers to implement Sequential Ci it S ti l Circuits
A sequential circuit may consist of a register (memory) and a combinational circuit.
Next-state value Register Clock Inputs Combinational circuit Outputs

The external inputs and present states of the register determine the next states of the register and the external outputs, through the combinational circuit. y p y y The combinational circuit may be implemented by any of the methods covered in MSI components and Programmable Logic Devices.

Shift Registers
Another function of a register, besides storage, is to provide for data movements. Each E h stage (fli fl ) in a shift register represents one bi (flip-flop) i hif i bit of storage, and the shifting capability of a register permits the movement of data from stage to stage within the register, or into or out of the register upon application of clock pulses.

Shift Registers
Basic data movement in shift registers (four bits are used for illustration).
Data in Data out Data out Data in

(a) Serial in/shift right/serial out
Data in Data out Data in

(b) Serial in/shift left/serial out

Data in Data out

(c) Parallel in/serial out

(d) Serial in/parallel out
Data out

(f) Rotate right

(g) Rotate left

(e) Parallel in / parallel out

Serial In/Serial Out Shift Registers
Accepts data serially – one bit at a time – and also produces output serially.

Serial d t S i l data input

D Q C

Q0

D Q C

Q1

D Q C

Q2

D Q C

Q3

Serial d t S i l data output

CLK

Serial In/Serial Out Shift Registers
Application: Serial transfer of data from one register to another.
SI Clock Shift control Clock Shift control CP T1 Wordtime Shift register A CP SO SI Shift register B SO

T2

T3

T4

Parallel I /S i l O t P ll l In/Serial Out Shift R gi t Registers
Bits are entered simultaneously, but output is serial.
Data input D0 SHIFT/LOAD D1 D2 D3

D Q C

Q0

D Q C

Q1

D Q C

Q2

Serial data D Q Q3 out C

CLK SHIFT.Q0 + SHIFT'.D1

Parallel I /S i l O t P ll l In/Serial Out Shift R gi t Registers
Bits are entered simultaneously, but output is serial.

Data in D0 D1 D2 D3

SHIFT/LOAD CLK C

SRG 4

Serial data out

Logic symbol g y

Parallel I /P ll l O t P ll l In/Parallel Out Shift R gi t Registers
Simultaneous input and output of all data bits.
Parallel data inputs D0 D Q C D1 D Q C D2 D Q C D3 D Q C

CLK Q0 Q1 Q2 Q3

Parallel data outputs