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Universidade Federal de Minas Gerais

Escola de Engenharia

Test and Verification of
Microelectronic Circuits
Laboratory
Version 1.1

Revision
Date

Author(s)

Version

Commentary

02/11/15

Frank

1.0

Initial Version

16/11/15

Frank

1.1

Assignment 2 added, corrections

1

Contents
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Contents............................................................................................................................... 2
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Introduction ......................................................................................................................... 3
2.1 Lab goals ....................................................................................................................... 3
2.2 Lab materials ................................................................................................................. 4
2.3 Assignments .................................................................................................................. 4
3
Tool Setup environment and access ..................................................................................... 6
3.1 Basics ............................................................................................................................ 6
3.2 EDA/Cadence tools ....................................................................................................... 6
3.2.1 Cadence tool set ........................................................................................................ 6
3.2.2 Confidentiality........................................................................................................... 8
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Assignment 1: Combinational Circuit Testing .................................................................... 9
4.1 Homework assignment .................................................................................................. 9
4.1.1 Required knowledge .................................................................................................. 9
4.1.2 Learning Goals .......................................................................................................... 9
4.1.3 Assignment description ............................................................................................. 9
4.2 Lab assignment............................................................................................................ 10
4.3 Required knowledge: .................................................................................................. 10
4.3.1 Learning Goals ........................................................................................................ 10
4.3.2 Assignment description ........................................................................................... 10
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Assignment 2: Sequential Circuit Testing......................................................................... 19
5.1 Homework assignment ................................................................................................ 19
5.1.1 Required knowledge ................................................................................................ 19
5.1.2 Learning Goals ........................................................................................................ 19
5.1.3 Assignment description ........................................................................................... 19
5.2 Lab assignment............................................................................................................ 20
5.2.1 Required knowledge ................................................................................................ 20
5.2.2 Learning Goals ........................................................................................................ 20
5.2.3 Assignment description ........................................................................................... 20
5.2.4 Automatic Test Pattern Generation for Scan-enabled designs ................................ 25
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Assignment X (eXtra): Board Testing and Boundary Scan ............................................... 27
6.1 Homework assignment ................................................................................................ 27
6.1.1 Required Knowledge ............................................................................................... 27
6.1.2 Learning Goals ........................................................................................................ 27
6.1.3 Assignment description ........................................................................................... 27
6.2 Lab assignment............................................................................................................ 28

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S. No matter how perfectly clean the clean room is there will always be variation between production batches and even neighboring chips. we will be using Cadence software. synthesis. This is due to the fact that the manufacturing process is very complex and highly sensitive to environmental conditions. DfT makes it possible to perform individual chip testing within a reasonable amount of time per unit while achieving high test coverage. Hamdioui.1 Lab goals The lectures of the course “Test and Verification of Microelectronic Circuits” provide a solid background in basic aspects of IC testing including fault modeling. Every manufactured chip has to be (extensively) tested to make sure that no faulty chip will be shipped to customers. the transistors are continuously becoming smaller and increasingly sensitive for these defects. The choice for Cadence software as opposed to other software providers stems not only from the advanced state of the software but also of the high penetration of Cadence software in the field of chip design. A circuit with poor testability may cause time and/or cost losses during post-fabrication testing and testing for reliability. power. The course shows that testability is one of the most important requirements which should be considered along with other essential constraints such as performance or cost when designing a circuit. design-for-testability. DfT is integrated in Electronic Design Automation (EDA) software. EDA software helps creating a chip in various facets of the design and production process. area-. floor planning. specifically targeting digital integrated circuits. test pattern generation. and Mentor Graphics. from the basic requirements through designing. DfT can help diagnose which components are failing in order to target those areas in a subsequent redesign or manufacturing of the chip.. This lab course gives an introduction to some practical aspects of testing integrated circuits and systems. the importance of individual chip testing is paramount. Delft University. Ir. Furthermore. scan design.2 Introduction This material is based on the lab course “VLSI Test Technology and Reliability” of Dr. Encounter Test (ET) and NC-Sim. etc. and therefore the likelihood for you as future chip designers to use Cadence Software in your work. in particular the tools RTL Compiler (RC). this is because chips may suffer from design errors and/or defects due to manufacturing process. the base materials from which the chip is produced are slightly polluted and even the silicon wafers themselves will have some defects. The Netherlands. The latter aspect might be very important because testing of some operation-critical components is done during the 3 . 2. All three of these tools are part of the Cadence Encounter toolset. Synopsys. Furthermore. The manufacturing process for computer chips is not perfect. Design-for-Test or DfT is the process of modifying and adding additional hardware to a chip’s design in order to aid the testing process. optimization. speed-analysis and testing. There are three major players in this field: Cadence. For this lab. Furthermore.

• Cadence product manuals and reference guides. Board Testing and Boundary Scan: In this assignment. etc. After finishing the lab.g. The purpose of the lab is to familiarize the student with design-for-testability and with the use of EDA software tools. i. balancing Scan Chains and ATPG for sequential circuits. The concepts learned during the lectures will be used to solve the assignments and afterwards EDA tools will be used to experimentally evaluate the proposed solutions and changes needed to designs to make them better testable.e.e. the focus will be mainly on scan design. • Able to perform test pattern generation for combinational and sequential circuits. In addition. slides and book). Combinational Circuit Testing: In this assignment.whole lifetime of such a device. Sequential Circuit Testing: In this assignment. 2. students will be: • Familiar with EDA test-related software. 1. the following material has to be available: • This lab course manual. scan chain insertion). This lab course will thus provide students with insight on the fundamentals of DfT software tools and first-hand experience on the usage of these tools. Each assignment has two parts: one theoretical part that has to be worked out at home and one practical part that has to be performed using Cadence tools.3 Assignments There are in total three assignments. 2. fault coverage. • VLSI Test Technology and Reliability course materials (i. source files needed to perform the lab assignments are zipped together and can be found in the public directory of the user ‘said’. • Able to use JTAG for board-level testing. • Able to modify circuits to make them better testable (e. you will learn and practice concepts such as stuck-at fault models. you will learn and practice to add Boundary Scan to a design to aid board testing.2 Lab materials To perform the activities of the lab properly and efficiently.. 3. how to test both interconnects and chips on a board. Table 1 summarizes the required knowledge for each of the assignments together with the targeted objectives. 4 . ATPG for combinational circuits. • Evaluate the impact of testability on circuit design. 2.

fault models. fault equivalence and fault collapsing • Functional versus structural testing • Fault simulation • ATPG for combinational circuits and D algorithm • Movement through the file system • Opening files and starting applications • Editing files (we recommend to use a graphical interface) • Moving files • Please read the first 2 chapters from this Linux handbook: http://tldp.pdf 2 • • • • • eXtra • • • • • • Objectives • Define fault lists of combinational circuits and optimize them • Develop test patterns for stuck-at faults • Use SCOAP for testability measures and analysis • Understand the theory better and have good background for Lab assignment 1 • Become familiar with the Cadence tool environment • Learn to use RC to get a visual representation of the design and of the changes that have been made to it • Learn to use ET to perform ATPG • Compare and analyze the obtained results with those from the software and explain the possible differences • Insert scan chains into a sequential circuit Defects. fault equivalence and fault collapsing ATPG for combinational circuits and D algorithms Automatic Test Pattern Generation for sequential circuits Scan Design Boundary Scan Basic knowledge of LINUX and the Cadence tools: RTL compiler (RC). functionality and physical impact on chip design Apply Boundary Scan to aid board-level testing Develop test patterns for JTAG-enabled chips. fault models. 5 . Encounter Test (ET) and NC-Sim • • • Understand Boundary Scan/JTAG usage.org/LDP/intro-linux/intro-linux. Encounter Test circuits (ET) and NC-Sim Defects. fault equivalence and fault collapsing • Understand the impact of Scan Design on a circuit ATPG for combinational circuits and D algorithms • Develop test patterns for scan-based sequential circuits Automatic Test Pattern Generation for sequential circuits • Put Scan Design into practice Scan Design • Adapt ATPG to Scan Design Basic knowledge of LINUX and the Cadence • Use Scan Design as DfT to test sequential tools: RTL compiler (RC). fault models.Table 1: Overview over the assignments # 1 Required knowledge • Defects.

The three tools are briefly explained next.gz. Test and Verification of Microelectronic Circuits lab 3. Next.1 Cadence tool set In order to be able to change the designs and insert DFT features during this Lab.tar.2.gz Where X is the number of the current assignment.cpdee. They are part of the Encounter software package.gz In order to see all the extracted files. three software tools will be used. The commands are: $> mkdir ~/testing $> cd ~/testing $> wget www. 6 .ufmg.3 Tool Setup environment and access 3.br/~frank/test/assignmentX. Figure 1: Directory structure. Use the command: $> tar -xzvf assignmentX.tar. type again the following command: $> ls Now. After successful login open a console and download the activities as zip file of the current laboratory class. which specifically targets digital circuits.tar. you should see several files that have been extracted from the original compressed file. the files will be extracted from assignmentX. 3. again it is assumed here that you are in the working directory “testing”. The contents of your working directory should have the structure depicted in Figure 1.1 Basics This laboratory will be based on a Virtual Machine.2 EDA/Cadence tools This section first describes the tools to be used and then discusses how to start/run them.

it therefore maintains lists of all possible fault sites and whether a fault has already been covered by a test or not. the design itself. ET uses the logical functions of the design components to generate appropriate test patterns. the tool will be used to view. and provides test patterns for their detection together with a test bench that can be used for fault simulation. setup requirements (if any) to put the design in the desired state to receive the test patterns. Ultimately these statistics also provide the so-called test-coverage. NC-Sim is a simulation tool which is similar to Modelsim from Mentor Graphics (with which you may be familiar with). It is worth noting that this tool will be primarily used for scan design and JTAG. Our cell library for instance contains many variants of AND-gates. voltage requirements. DFT infrastructure is inserted in the design resulting in a new file “DFT_Design. the impact of added DFT features to the design in terms of area. latency and power consumption. Once the design is modified to support DFT infrastructure. drive-strength and so on. but also in size. modify and optimize the different components of the design. This software tool also provides visual feedback of what is actually happing inside the DUT (Device Under Test). we start width a HDL design description (e. The latter is used with “DFT_Design. hence. ET is trying to use the least amount of test vectors to cover as many faults as possible.• RTL Compiler (RC): This is a general tool able to read a description of a digital circuit given in a vhdl or verilog format. it can be saved as a verilog netlist and used as input for Encounter Test. In this lab course. The tool is able to automatically optimize the design and provide the most efficient solutions to meet the design requirements. verilog and/or vhdl) such as “Design. and the fault-free expected responses. Then. they have to be mapped to a pre-defined library. The tool provides the ability to review.v” in the figure. Next. In order to perform an accurate simulation.g. The faults are stored in a fault list which may contain static faults (such as stuck-at faults) as well as non-static faults (such as delay faults). ET is then used to generate the test patterns and test bench. energy consumption.g. varying not just in the number of inputs. This library contains the logical and physical properties of the standard cells that are being used in the netlist(s). delay. the tool needs the specification of all design components. • Encounter Test (ET): This is an Automated Test Pattern Generation (ATPG) tool. It identifies all possible faults within the design. 7 . and the test bench created by ET. RTL compiler requires a full specification of all components within the design. Figure 2 will be used to explain the overall flow of these tools. heat tolerance.v”. RTL compiler provides feedback on each performed step. Initially. e. • NC-Sim: This tool is used to perform circuit/fault simulation. the percentage of faults covered by a particular test set or Testbench..v” and the required libraries to perform fault injection and circuit simulation using NC-Sim in order to identify the fault coverage. the file will be compiled using RC to check the correctness of the input file. insert DFT features (such as scan insertion) and compile the designs. NC-Sim runs the test bench and compares the produced outputs with the expected values. Note that the test bench consists of the test patterns.

8 . It should be seen as confidential material that should not be further distributed and/or copied.2 Confidentiality It is worth noting that for this course the UMC cell library for 90nm technology is made available to students (UMC is a Taiwanese foundry). It is therefore strictly forbidden to copy this library for personal use.2. VLSI Test Technology and Reliability lab course 3.Figure 2: Tool Flow.

What is the collapsed ratio? (optional: you may also use dominant fault collapsing) 5. 2.1 Homework assignment Before providing the description of the homework. the required knowledge and the learning goals of the assignment will be given. you need the following knowledge: • Defects. 6.3 Assignment description Given the circuit of Figure 3. it is a combinational circuit consisting of eight logic gates.1. fault equivalence.1 Required knowledge In order to complete the homework. Figure 3: Combinational circuit 1. and practical part that is to be performed in the Cadence environment. Answer the following questions. Derive the equivalence collapsed set. and fault collapsing • Functional versus structural testing • Fault simulation • ATPG for combinational circuits.2 Learning Goals After finishing the assignment you will be able to: • Define fault lists of combinational circuits and optimize them • Develop test patterns for stuck-at faults • Understand the theory better and have good background for Lab assignment 1. Use D algorithm to generate a test pattern for SA0 shown in the circuit. 4. fault models. What is the difference between a defect and a fault model? Give an example. 9 .1.1. D algorithms 4. one theoretical part to be prepared at home. 4. 4. Use D algorithm to generate a test pattern for SA1 shown in the circuit.4 Assignment 1: Combinational Circuit Testing Each assignment consists of two parts. What is the number of potential fault sites in the above circuit? 4. How many test vectors will be needed if functional testing will be used to test the above circuit? 3.

1. 4. it is the same as the one used for the homework. Figure 4: Logic circuit of Lab assignment 1 10 . In addition.pdf You are encouraged to use a separate directory for each of the assignments. the tools will be used to practice ATPG for the circuit of Figure 3. the required knowledge and the learning goals will be listed.2 Lab assignment This assignment will introduce you to the Cadence simulation environment and the main tools that will be used for the lab. 4. you need some basic knowledge of Linux such as the following: • • • • Movement through the file system.1 Learning Goals • Become familiar with the Cadence tools • Learn how to use RC to get a visual representation of the design and the changes that have been made to it • Learn how to use ET to perform ATPG • Perform circuit simulation using NC-Sim • Compare and analyze the obtained results and explain any possible differences 4.4. Before describing the lab assignment.3.3 Required knowledge: In addition to the required knowledge described in Section 4. the circuit of Figure 4 will be used.org/LDP/intro-linux/intro-linux.2 Assignment description In this assignment. moving files Opening files and starting applications Editing files (we recommend using a graphical interface) Read the first three chapters from this Linux manual: http://tldp.3.1. The purpose of the assignment is to use the Cadence tools in order to generate a set of test patterns for the detection of all static stuck-at faults.

Specifically./” will let you go two levels up in directory hierarchy starting from your working directory../libraries/fsd0a_a_generic_core_ss0p9v125c..v & Inspect this verilog netlist and verify that it indeed describes the circuit of Figure 4.. Reading the netlist: Make sure that your working environment is “<testing>/assignment1/rc/ “ 1. . the ATPG tool) will be used to generate the test bench (i. in order to access the directory “libraries” which contains the technology library that we are targeting (fsd0a_a_generic_core_ss0p9v125c./. Reading-in the netlist B. Finally.This lab assignment mainly consists of three parts: A. ………………………………………………………………………………………………. These library cells (such as AND/OR-gates and flip flops) are made in a certain technology. in our case 90nm technology by UMC. NC-Sim will be used to perform circuit simulation using the generated test bench and compare the obtained results with the expected ones.e. ………………………………………………………………………………………………. the netlist of Figure 4 has to be read-in by RTL Compiler in order to produce the visual schematic of the design/circuit.. ………………………………………………………………………………………………. Encounter Test (i. The library can be read-in (after RC is started) by typing the following command in the rc command prompt: &rc:/> set_attribute library . A. Then. Circuit Simulation First. 3. 11 . test setup. The next step consists of reading this file using RC.. &rc:/> rc -gui Prior to reading the HDL description of the circuit. ………………………………………………………………………………………………. RTL compiler requires a technology library.lib) 2.. that contains the description of the cells used in the circuit.pdf “in the ‘manual’ directory. ……………………………………………………………………………………………….lib The “. test patterns. open the file ‘ assignment1. Start RTL compiler. using the following command: &> kwrite assignment1. and the expected results) for stuck-at faults. Open a second Linux terminal and go to the same directory as above (i.e.e. why is “read_hdl” not suitable in our case? Hint: (see document ‘RC_user. pages 78 to 81 and 98 in particular). rc)./.. What are the different commands that can be used to read the HDL file in general? Explain the difference between them. to be read-in.v ‘ which contains the netlist of the design. ………………………………………………………………………………………………. Test Pattern Generation C.

select the appropriate file and hit OK to run the script. zoom in and out by clicking and dragging on the schematic. Use the appropriate command as found in task 3 and execute it.. After the execution. Verify again that this circuit is indeed the same as that of Figure 4. ……………………………………………………………………………………………….From the RC prompt: run the command: &rc:/> source <file_name> . ………………………………………………………………………………………………. ……………………………………………………………………………………………….tcl. .. ………………………………………………………………………………………………. Open the script file view_assignment1. ………………………………………………………………………………………………./. and generate the schematic. 4. Note that the way you drag a selected box determines the result of the action.v? Why? ………………………………………………………………………………………………. we restart RC by closing it and opening it again. You can e. You can close the Verilog file. Is RC going to produce the same netlist as that in the file assignment1. Read pages 2 to 6 from the RC User Manual ‘RC_user.g. Next we will use a TCL script file in order to automatically read-in the library and the input file. 5.Through the GUI window: Use the “source script” functionality (as depicted in Figure 5). 12 . The file has the following content: #####Assignment 1 #####Read Libraries set_attribute library . the circuit should appear in the GUI. Make sure again you are in the ‘rc’ directory of assignment 1. RC has to be closed by typing the following command at the prompt: &rc:/> exit Run the script from the RC prompt. or alternatively through the GUI window: .Assume that we have a vhdl description of the circuit of Figure 3 and we want to generate its netlist using RC../fsd0a_a_generic_core_ss0p9v125c..lib #####Read Design #<put your read_in command here to read the netlist as found in task 3> The last sentence in the above file means that you have to add a command that will perform the reading of the netlist. Create a selection box from left to right and then from bottom to top to experiment with dragging actions.pdf’ (pdf page 22 to 26) in order to gain more insight on how to use script files in the RC workflow.. Now the script has to be run. To do that.

13 . etc. e. and the “Encounter Test Command Reference Guide” (ET_cmdguide. p. It is worth noting that RC is able to predict the maximal attainable clock speed. . Area:…………………………. Power:…………………………………………………………………………………. scan. and area by using the specified technology library. Start ET ($> et –gui &) and create a new project in your working directory. Latency:……………………………………………………………………………….Figure 5: RC Screenshot of assignment 1 design 6. e.Specify the model. etc. and area [hint: explore the GUI]. (ET_models.…………………………………………………….pdf”). . i. 1.g. All these steps can be performed using the “Build Models” menu depicted in Figure 6. You can now exit RC and start ET. power consumption.23-25)..pdf) available. the following steps have to be completed in ET: . power usage. while the second one specifies the commands and their meaning. The first document gives a general view of ET and how it can be used...Specify the test mode. &rc:/> exit B. design file and test library. static faults. Test Pattern Generation It is useful to have the “Encounter Test Modeling User Guide” (filename: “ET_models. Use RC to estimate the latency. dynamic faults.g. JTAG.e.Specify the fault model. For this. We recommend creating the project in the folder <testing>/assignment1/ET/ (see menu > new) The next step is to generate ATPG for the circuit.

g. the set of targeted fault models has to be defined for fault coverage evaluation. Specifying the fault model 4. When are they useful? ………………………………………………………………………………………………. pages 77-83). Specifying the test mode 3.1. Read also the Model Guide (file: “ET_models_10.pdf”... e.Figure 6: ET Screenshot. dynamic faults. In this assignment. Scan Design. In the “Test Mode” you need to specify the targeted DFT feature that will be used. compression. pages 23-30). push the “setup” button and select the simplified cell-library “fsd0a_a_generic_core_30_tud. (ET_models_10.pdf. we will target only static faults. In this step.. we will use FULLSCAN. In this assignment. Set the ‘test mode name’ to FULLSCAN and hit run. ………………………………………………………………………………………………. Since ET does not provide a special mode for combinational circuit testing. JTAG etc. you have to use the ‘FULLSCAN’ test mode. etc. however.v”. Name some of the other modes. browse to select the desired netlist. Use the “Verification > Build Models > Model” menu (see Figure 6) to specify the synthesized netlist and cell-library. Verification 7 Build Models Specifying the model 2. ……………………………………………………………………………………………….1. static faults (i.e.lib. Before hitting “run”. ………………………………………………………………………………………………. ET supports other modes. We have used the FULLSCAN test mode. For example. FULLSCAN is normally used for sequential circuit testing.. 14 . Stuck-at faults).

.......... .................... This assignment targets Static Tests.... only static faults are considered.. Check the session log file to answer the following questions: • How many total statistic faults were found? • How many collapsed static faults were found? ………………………………………………………………………………………………............. • Targeting both static and dynamic faults (Verification > Build Models > Fault Model) 15 ................ make sure to disable dynamic faults............................ this can be performed using the Verify option under Verification menu: Verification > Verify > Test Structures Make sure to select the correct Test Mode........ Delay Tests. The ATPG process is next........ Before generating the test bench / test vectors... ……………………………………………………………………………………………….. ……………………………………………………………………………………………….... see Figure 7.......... ATPG It is useful to play with the tool by e................... etc..... (see ATPG > Create Tests).............................. ET has to verify the correctness of the chosen DFT features....................................................................................................................................... ....................... 5.............. Select FULLSCAN..... ……………………………………………………………………………………………….. Test benches can be created for different types of tests such as Static Tests....... Figure 7: ET screenshot......... .. For now....... Scan Chain................g...... 6...... Run ATPG for static Test for Logic ATPG > Create Tests > Specific Static Faults > logic and report about the following: • How many patterns are generated? • Are there any undetectable faults? • How many simulated patterns and how many patterns are needed to realize the maximum fault coverage? Explain the difference........Select via the menu: “Verification > Build Models > Fault Model”.......

................. ..... copy the design file and the two test bench files into the NC-Sim directory.. you will be requested to provide many input options: • Vectors to write in test bench: you can choose the committed vectors.............• Running ATPG for delay tests......................................... The test patterns file contains mainly three items: (a) the setup instructions to put the chip in the desired test state............. The test patterns file (........................................ but also the uncommitted ones if you already gave them specific names • Provide the output file name and the directory where it will be stored • Language: this specifies the language in which the test bench has to be created. (b) the test patterns and (c) the expected results....................... 9.......................... You have to choose Verilog...................................................... Close ET now................................ 10.......... This is done using the function “Write Vectors” under the ATPG menu..... Given the two stuck-at faults given in Figure 3........................ You are now ready for the next step which is circuit simulation using the generated test bench......................... by File->Exit Tool....................... the function “Commit Tests” under ATPG menu has to be used to select the tests to be put in the test bench........... • Scan format: for this assignment.... To make navigation a bit easier............................. .................................. and Verilog........... 8.............................................. .................................... the test bench has to be created.................................................... C.......... Add the generated test set for static faults (created for logic in task 6) to the test bench using “Commit Tests”............ How many test vectors are there? What are they? And what are the expected responses of each pattern? ......... NC-Sim will simulate the test bench applying the test patterns to the circuit and compare the produced results with the expected 16 ..................... ................................... examples are STIL.... which of the test patterns generated in the previous steps can detect them? ......... Create the test bench for the selected test set..... Circuit simulation The final step for this assignment is to simulate the test bench using NC-Sim. Open the test patterns file with Kwrite to review its content............. While doing this.............v file) are now created.verilog file) and the test bench file (mainsim.. After the test sets to be included in the test bench are selected............ 7............... We will simulate the application of the test patterns to the design using the test bench.................. The ATPG can be run many times with many options till the minimum set of tests/vectors to realize the targeted fault coverage is created....... WGL.................................. this input is optional as we are not using scan........... Once this is done...........................

Figure 8: NC-Sim screenshot. you have to read the manual “Sim_Encounter_TVPA. Right click on the selected signals.. signal selection Browse to select the design under test in order to select the inputs and the outputs that will be visualized. Run the simulation: “simulation” menu > run. It is worth noting that the optional and recommended arguments of the command are not needed.verilog file). • Add the argument “–gui” to activate the GUI environment./. and page 5 in particular. you will then see how the executing command is structured.. the invoked window is shown in Figure 8.v <mainsim_file>.v “. • Add the argument “–timescale 1ns/1ps” to force the time unit/simulation precision.v file) which was created with ET.pdf”. 17 .v \ <our_design_netlist>. ncverilog -v . • Add the correct name for the test bench file (mainsim. Use your compiled command to start NC-Sim.v + TESTFILE1 = <Test_Bench_file>. That is the netlist that will be simulated. 1./libraries/fsd0a_a_generic_core_30. To start NC-Sim.ones (which are also part of the test patterns).lib_tud. • Add an “–access rwc” argument to allow NC-Sim to access the external pins directly. • Add the correct name for the file containing the test patterns (. and hit “send to waveforms window”. Complete the ncverilog command below to start NC-Sim: • Check that the provided path to the library file is correct • Add the correct file name for “<our_design_netlist>.verilog \ …… 2.

........... Do they match your expected results? ………………………………………………………………………………………………. ............................. ................... 18 ...................................................................... Figure 9: NC-Sim screenshot........................................................... write down the required simulation time and the number of good comparing vectors........The results will look like Figure 9...................... Inspect the Console window for a log of the simulation run........................ :………………………………………………………………………………………………............................................ Can you explain why this number is different from the number of generated vectors? ................................. You can zoom out along the x-axis...................... Inspect the waveforms and report about the test patterns and the produced outputs...……………………………………………………………………...................... 4................. :………………………………………………………………………………………………............ ………………………….............. waveform after simulation 3........

fault models.1. Redraw the circuit with scan design and show all the signals and modifications done to the original circuit.1. 3. • Understand the impact of Scan Design on a circuit. 5. 2. The homework will provide you with an opportunity to analytically exercise the concepts. 5. the required knowledge and the learning goals of the assignment will be given.3 Assignment description The sequential circuit of Figure 10 consists of two combinational blocks and three D flip-flops. Assume that we want to test SAF in combinational circuit 2. fault equivalence and fault collapsing • ATPG for combinational circuits and D algorithm • Automatic Test Pattern Generation for sequential circuits • Scan Design 5.5 Assignment 2: Sequential Circuit Testing This assignment deals with sequential circuit testing and Scan Design. Describe how you can do this. Explain how you can test the original circuit using the developed scan design. What is the benefit of Scan design? What are the associated costs? How much is the area overhead? 19 .1. In the lab assignment you will be using Cadence tools for scan insertion and compatible test vector generation. • Develop test patterns for scan-based sequential circuits. Convert the circuit above to a full scan circuit. Describe clearly the steps you followed to realize the scan design.1 Homework assignment Before providing the description of the homework. 5. Combinational circuit 1 consists of 150 gates while combinational circuit 2 consists of 200 gates. you need the following knowledge: • Defects. 4.2 Learning Goals After finishing the assignment you will be able to: • Insert scan chains into a sequential circuit. Figure 10: Sequential circuit 1.1 Required knowledge In order to complete the homework.

Circuit Simulation 20 .2 Learning Goals After finishing the lab you will be able to: • Put Scan Design into practice • Adapt ATPG to Scan Design • Use scan design as DFT to test sequential circuits 5.3 Assignment description The purpose of the assignment is to use Cadence tools to add scan design to the given circuit and generate test patterns for the modified circuit utilizing the scan chains to detect the static stuck-at faults. 5. This lab assignment consists of three main parts: A.2. Test Pattern Generation C. Encounter Test (ET) and NC-Sim.2. Before describing the assignment further. Figure 11: Logic circuit of Assignment2 5.2. how the test is performed and the impact of scan design on the original circuit • Impact of scan design on area and latency • Basic knowledge of Linux and the Cadence tools: RTL Compiler (RC).1 Required knowledge In addition to the required knowledge described in Section 5.2 Lab assignment In this lab assignment Cadence tools will be used to make the sequential circuit of Figure 11 (which is a counter) scan testable. the required knowledge and learning goals are given.1. you need the following in order to perform the assignment in an efficient way: • Understanding the concept of scan design. Scan chain insertion B.1.5.

.....gz $> tar -xzvf assignment2......................... we will replace the existing Flip-Flops (FFs) with scan cells................................................................. Scan chain insertion: Enter the folder testing.............. .............. 21 ............... open the Verilog netlist of the counter in Kwrite and inspect the file.................................................... download the 2nd assignment...... As with the previous lab assignment................................................... 1............ This time RC will not only be used to view the design............................................. you will have to load the design and library into RC... you can include them in a script (e. extract it and enter the path rc by using following commands (the folder testing should be the same as from assignment1): $> cd ~/testing $> wget www... The generalized flow is depicted in Figure 12........... Start ‘RC’ and read in the Verilog netlist of the counter.............. which offer the same functionality plus the ability to scan values in and out of the circuit..............g.......................................... What is the module/entity name of assignment2? What is the number of inputs and outputs of the circuit? .... for us 7 additional steps are required...... use the script created in assignment 1 as a starting template............ Before doing that........................ Each of the above steps requires a command as will be shown next.............................................. “view_assignment2..................................tar......................................tcl script).......... scan_insert_assignment2..... ................................... However.................gz $> cd assignment2/rc In this part of the assignment your task is to add DfT hardware to the design.................................................................. Once they work correctly. Remember to first setup the library prior to reading the HDL file............. .. Make sure that the script file is stored in “<work_dir>/assignment2/rc” folder........................ In particular... but will be also used to make changes to the design and implement Scan Design..................A............tar....tcl”) like the one created in the first assignment and sourcing it.......... 2..g..................................... this requires several additional steps.......... .....cpdee.... You have to run each of the commands in the RC prompt.............................. • • • • • • • Add a test pin Select Muxed-Scan design Check DFT rules Replace Flip flops with Scan Cells Define Scan chains Put Scan Cells into scan chains Write out the new augmented netlist......... What are the area and latency of this circuit? ...........br/~frank/test/assignment2...ufmg.......... You can do that by running a command or creating a script file (e...........

Figure 12: Top-down test synthesis flow 22 .

............................. check_dft_rules...... 6....pdf.. This command and its effects are explained in the RC_cmdref.................................................... What is the full ‘define_dft shift_enable’ command you have to use? define_dft shift_enable……………………………………………………..... search for “muxed_scan”........................................ This is known to RC as the ‘muxed_scan’ style of scan design................................. .................... page 493....................................................................... the MUX will have two inputs: the original FF functional input and the Scan-in test input....................pdf manual................................................. To maximize the fault coverage................................................ 5........ Each FF will then get a MUX at its input. ............ 23 ................ The test pin is called scan_enable (SE)................................................................3.................pdf manual........... check dft rules will be applied to the circuit in order to check whether the FFs can be converted into SFFs....................................................................................... What is the command to be used in order to set up this style? It is a “set_attribute” command.................................. 575)........................... p............................ see the RC_attref...... .......................... The command we are going to use is: ‘check_dft_rules’....... Now the FFs can be replaced with SFFs..................... A new test pin must be added.. Select Muxed-Scan design...... Add a test pin..................... you can use the ‘define_dft shift_enable’ command (see RC_com.............................................................. this pin is used to switch between the functional and the test mode (for scan-in and scan-out)........................................................... 4.................................... This command selects the MUX to be used with scan design..... Next....................... …............ (see RC_comref......... ................ page 651) What is the command we are going to use? .pdf................. set_attribute............... In order to add this pin.............. the MUX will be controlled by the scan-enable signal (SE).......... all FFs should be converted.....

................. Define the name of the chain........... a scan chain and additional pins (scan_enable.......... This script must start with the 2 commands from the “view_assignment2................ and verify that you have a new netlist with all FFs replaced with scan cells. Name: chainx (replace the “x” with the scan chain’s number) sdi : sdix sdo: sdox What is the command that we are going to use? ....... RC_cmdref........................... ................................... “scan_insertion” script................. With the 7 commands you can now write your own script file...... 10..................................................................... and create the ports as non-shared ports.......... Next the Scan chains can be defined.....................v‘ in the current directory................................................................................................................. RC_cmdref................ 8................................. 24 ............pdf).................................................. the sdi..... Concatenate the DFFs into the newly defined chain......................................... (HINT: See p.............................. ........7...............tcl” script.......... sdi0 and sdo0)...............................v”...515...... Write out the new scan enabled netlist to the file ‘assignment2_scn......................................................... ................................................... 563......................................and sdo-ports........ and writes out a scan-enabled netlist..................... i...................... (HINT: See p...................................... Run all 7 commands you have compiled from tasks 3 to 9.........................pdf).......................................... 9... What is the full command that you are going to use? write_hdl ...................... Use the command write_hdl for this.................... ......................................e... are there any attributes required in our case? ........ . Create a “scan_insertion” script that automatically reads in a cell library and the netlist “assignment2..........................

.................................. the design contains a scan chain....... as you can take the same steps here....... Instead of creating a logic test... In case you forgot the precise steps you took........... ....................................................................... The full syntax of a pin assignment file is given in ET_models............4 Automatic Test Pattern Generation for Scan-enabled designs In the <work dir>/assignment2/et directory you will find a pin assignment file... and comment on the coverage.... and write out the test patterns and test bench in Verilog format.................... Test Pattern Generation: 5.. Why are there now 2 test files with test vectors? ................................... in order to test the functionality of the scan chain(s)......... The first test to prepare is the “Scan Chain flush” test.......e... You will have to modify this file to match the pin names you used in “assignment2_scn....................................... once more “FULLSCAN” and under “Additional Options” specify the “input pin assignment file”... Why is the coverage obtained by the logic test so high even when the faults inside the Scan Chains are not targeted? ................................... 1............. 25 .......pdf pages 77 to 80........................................2................ The ATPG procedure is similar to the procedure in the first exercise...... It makes sense to perform this test on a chip first..... it is pointless to try any other tests...................... We start in exactly the same way: • Go to the “<work dir>/assignment2/et” directory • Start ET • Create a new project • Build the model • Build the test mode....... It specifies to ET which pins to use to control the scan chain that was inserted with RC.................................................. ............... Prepare a “Scan Chain flush” test........... Commit both tests sets....... Now do the same for the “Logic” test.................... ............... 2.................................................................... as a broken scan chain will fail all of those tests as well...... and includes helpful examples..... we will make several tests and combine them to make a comprehensive test...............v”.......... i........................... ................. If the Scan Chain fails this test...................... we request that you revisit the steps in lab assignment 1................................................................B............... • Build the fault model • Verify the test structures The major difference between generating test patterns for assignment 1 and this one is the fact that assignment2 (counter) is a scan-enabled design....

...... .................................................................................. Inspect the Console window for a log of the simulation run..................................................................... write down the required simulation time and the number of good comparing vectors........................................................................ ................ .................................. Circuit Simulation: Circuit simulation of this assignment is almost identical to the simulation of assignment 1............. 26 .................................................. ................................... with only a minor tweak in the ncverilog execute command to account for the second test pattern file generated by Encounter Test.................... 1............... Write down this new ncverilog command.............................................................................................................................. Execute the command compiled in task 1....................................................... The generated test patterns can now be simulated as before................. ........... .................................C..................................................... 2...................................... Do note that there are now two test pattern files that should both be included in the ncverilog command.............................

e. you need the following knowledge: • Defects. fault models. and test vector generation.1.1 Homework assignment Before providing the description of the homework.1. functionality and physical impact on chip design • Develop test patterns for JTAG-enabled chips. and 4) • Testability measures and SCOAP (Chapter 6) • ATPG for combinational circuits. 6. The homework will provide you with an opportunity to analytically exercise the concepts. 6. testing both interconnects and chips mounted onto a printed circuit board (PCB).1. 2.1 Required Knowledge In order to complete the homework.2 Learning Goals After finishing the assignment you will be able to: • Estimate the impact of multiple scan design on area and latency • Understand Boundary Scan/JTAG usage. fault equivalence and fault collapsing (Chapters 1. the required knowledge and the learning goals of the assignment will be given.6 Assignment X (eXtra): Board Testing and Boundary Scan This assignment deals with Boundary Scan for the facilitation of board-level testing. 6.3 Assignment description Figure 13: Board with 4 chips and one serial boundary scan chain 27 . D and PODEM algorithms (Chapter 7) • Automatic Test Pattern Generation for sequential circuits (Chapter 8) • Scan Design (Chapter 14) • Boundary Scan (Chapter 16) 6. i. In the lab assignment you will be using Cadence tools for Boundary Scan insertion.

000 vectors for the chip. 3.5cents/s. 2.000 1024 Chip 2 1. and calculate the test time at a 100 MHz clock rate. The test patterns are applied by an external tester.000 1024 Chip 4 500. given that the tester cost is 4.000 512 Chip # Test Patterns # Flip-Flops Chip 3 1. assuming that half the chip pins are outputs and half are inputs. 5.000. Each interconnect requires two test patterns. What is the gate overhead if these 40 test pins are multiplexed onto existing functional pins. one logic gate uses 4 transistors. (Interconnect test time) Assume the board described in question 5. (Boundary Scan test time) The printed circuit board in Figure 13 has four chips with the following characteristics: Chip # Test Patterns # Flip-Flops Chip 1 500. 6. 6. thus we have 40 pins available for testing purposes? 4. (Boundary Scan economics) Estimate the cost of the Boundary Scan hardware for a chip with 256 pins. How many clock cycles would be required to test the logic when the design contains one scan chain? Check Section 14. estimate the costs of testing this chip using JTAG. recompute the time needed for testing Chips 1-4 with the usage of the BYPASS instruction. (Balance scan chains) How does this differ when 40 test pins are made available for scan chains (and 1 for the Scan_Enable signal)? Specify the scan chain length and the total test time in clock cycles. Assume that one transistor costs 525 µcents. Suppose that your chip has 100. Now.2 of the book “Essentials of Electronic Testing”.2 Lab assignment There are no lab exercises for this assignment. and a test clock rate of 200 MHz. Describe the JTAG instruction sequence needed to test the interconnect. one flip-flop uses 24 transistors.000 512 Compute the time needed for the consecutive testing of Chips 1-4.1. Compute the time needed for testing the interconnects of Chips 1-4. and without using the JTAG BYPASS instructions of the chips.000 gates and 2. through the JTAG boundary scan chain. Now. An ATPG program produced 500 vectors to fully test the logic. The time needed to test the interconnects does not need to be calculated.000 flip-flops. one mux uses 14 transistors and the JTAG TAP controller is implemented using 262 transistors. assuming a board clock rate of 512 MHz. one for a sa0 and one for a sa1 test. 28 .000.2. given a test vector set of 512.