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# Mailam Engineering College

(Approved by AICTE, New Delhi, Affiliated to Anna University, Chennai & Accredited by
National Board of Accreditation (NBA), New Delhi)

Mailam (Po), Villupuram (Dt). Pin: 604 304

DEPARTMENT OF COMPUTER APPLICATIONS

Unit–II [2 & 16 Marks]

Subject Name: Computer Organization
Subject Code: MC9211
Year

: 2012 – 2013

Semester: I
Prepared By: Ms. A. Subathra Devi, MCA, M.Phil.,

Subject Incharge

HOD

Mailam Engineering College

Principal

(Approved by AICTE, New Delhi, Affiliated to Anna University, Chennai
& Accredited by National Board of Accreditation (NBA), New Delhi)

Mailam (Po), Villupuram (Dt). Pin: 604 304

DEPARTMENT OF COMPUTER APPLICATIONS
Computer Organization – MC9211

UNIT II

COMBINATIONAL AND SEQUENTIAL CIRCUITS

Design of Combinational Circuits – Adder / Subtracter – Encoder – Decoder – MUX /
DEMUX – Comparators, Flip Flops – Triggering – Master – Slave Flip Flop – State Diagram
and Minimization – Counters – Registers.

Part – A
1.

Unit- II
Digital system consists of arithmetic and logic circuit (Gates & Flip-flops). It is
divided into two types of circuit.

Combinational logic circuit
Sequential logic circuit

Combinational logic circuit
The Combinational logic circuit consists of logic gates whose output at any time depends
only on the input values at that time.
Types of Combinational logic circuit:
Subtractor
Half Subtractor
Full Subtractor
Decoder
Encoder
Multiplexer
De-multiplexer
Magnitude Comparators
Sequential logic circuit:
In Sequential logic circuit output at any time depends on the present input values as well as
past output values.
Type of Sequential logic circuit
Flip-Flops
Register
Counters
Triggers
State diagram of minimization
Block diagram of Combinational logic circuit:

Combinational

n–
Input
variabl
es

.
.
.

Logic
Circuit

m–
Output
variables

.
.
.

The Combinational logic circuit whose output at any time depends only on the input values
at that time. The Output of the Combinational logic circuit does not depend on the any past
output values. It accepts ‘n’ input binary variables, and generate ‘m’ output binary variable.
Procedures or Rules for design the Combinational logic circuit:
From the given word descriptions of the problem identify the number of input variables and
required output.
The input and output variables are assigned letter symbols.
Draw truth table that describes the operation of the circuit for different Combinational of
input.
Write down the switching expression for the output.
Simplify the switching expression using K-map or algebraic.
Implement the simplified expression using logic gates.
The Combinational circuit which performs the arithmetic addition of two binary digits and
produce Sum and Carry.
It has 2 inputs and 2 outputs.
The Input variables are A & B.
The Output variables are Sum (S) and Carry (C).
Step: 1

A
Input
variabl
es

Half
B

SUM(
S)
CARRY
(C)

Output
variables

Step: 2 Truth Table 0 SUM (S) 0 CARRY (C) 0 0 1 1 0 1 0 1 0 1 1 0 1 A B 0 Step: 3 K-Map for Sum & Carry: A’ A B ’ Rules: B 0 1 1 0 Sum = AB’ + A’B = A (+) B K-Map for Carry: A’ A B ’ B 0 0 0 1 Carry = AB Step: 4 Logical diagram of half adder AB’ + A’B = A (+) B A’B’ + AB = A (+) B .

B & C The Output variables are Sum (S) and Carry (C). It has 3 inputs and 2 outputs. The Input variables are A.Full Adder: The Combinational circuit which performs the arithmetic addition of three binary digits and produce Sum and Carry. Step: 1 Block diagram of Half Adder: A Input variabl es Full B Adder C Step: 2 Truth Table 0 SUM (S) 0 CARRY (C) 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 A B C 0 0 0 SUM( S) CARRY (C) Output variables .

. Subtractor (Subtraction): Half Subtractor: The Combinational circuit which performs the arithmetic subtraction of two binary digits and produce Difference and Borrow.1 1 0 0 1 1 1 1 1 1 Step: 3 K-Map for Sum & Carry Sum = AB’C’ + A’B’C + ABC + A’BC’ Carry = AC + AB + BC Step: 4 Logical diagram of Sum & Carry.

It has 2 inputs and 2 outputs. The Input variables are A & B. Step: 1 Block diagram of Half Subtractor: Half A Inpu t Step: 2 vari Truth Table able s B Subtractor Dif Bow A B Diff Borrow 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 Step: 3 K-Map for Difference: A’ A B ’ Rules: B 0 1 1 0 Sum = AB’ + A’B = A (+) B K-Map for Borrow: A’ A B ’ B 0 1 0 0 AB’ + A’B = A (+) B A’B’ + AB = A (+) B Outpu t variabl es . The Output variables are Difference (Diff) and Borrow (Bow).

Step: 1 Block diagram of Full Subtractor: A Input variabl es B Dif Full Subtractor C Output variables Bow . The Input variables are A. B & C The Output variables are Difference (Diff) and Borrow (Bow).Carry = A’B Step: 4 Logical diagram of half Subtactor Dif = AB Bow = A’B’ Full Adder: The Combinational circuit which performs the arithmetic addition of three binary digits and produce Difference and Borrow. It has 3 inputs and 2 outputs.

Step: 2 Truth Table A B C Diff Borrow 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 Step: 3 K-Map for Difference & Borrow: Step: 4 Logical diagram of Difference & Borrow: .

the binary code corresponding to the input values. Encoder n Output variables . so inputs = 23 and output = 3 D D A 0 3 2 Input variabl es D 1 D 23 : 3 2 D 3 D 4 D 5 D 6 7 B Encoder C 3 Output variables . . . . In encoder the output lines generates. . For example take n=3. Block diagram of Encoder: 2n Input variabl es .Encoder: An Encoder is a digital circuit that performs the inverse operation of a decoder.

Equation: A = D 4 + D5 + D 6 + D7 B = D 2 + D 3 + D6 + D 7 C = D 1 + D 3 + D5 + D 7 Implementation of Encoder circuit: .

. . so inputs = 3 and output = 23 D A D 0 23 Input variabl es B 3 : 23 Decoder C D 1 D 2 D 3 D D 4 5 D 6 Truth table for Decoder 7 3 Output variables . Decoder 2n Output variables For example take n=3. Block diagram of decoder: n Input variabl es . . . such that each output line will be activated for only one of the possible combination of inputs.Decoder: A Decoder is a logic circuit that converts an n-bit binary input code into 2n output lines. .

Multiplexing is the process of transmitting a large number of information over a single line. A digital Multiplexer (MUX) is a combinational circuit that select one digital information from several sources and transmits the selected .Equation of Decoder: Implementation of Decoder circuit: Multiplexers The Term ‘Multiplexer’ means many into one.

data communications and data bus control. They can also be used to switch either analogue. When used with a de-multiplexer. It selects one of many inputs and steer the information to the output. there are 2n inputs and n selected lines whose bit combine and determine which input is selected. Normally. It is otherwise called as data selector. parallel data can be transmitted in serial form via a single data link such as a fiber-optic cable or telephone line. with the switching current in analogue power circuits limited to below 10mA to 20mA per channel in order to reduce heat dissipation. digital or video signals.information on a single output line. Function Table: S (Selected Input) 0 1 Input I0 I1 = I0S’ + I1S Logical Diagram: . 0 I0 MUX Y 1 I1 S The Multiplexer is a very useful combinational device that has its uses in many different applications such as signal routing.

Block Diagram: I0 0 I1 Y 4: 1 1 MUX I2 I3 S1 S0 Function Table: S1 S0 Input 0 0 I0 0 1 1 0 1 1 I1 I2 I3 Y = I0S1’S0’ + I0S1’S0 + I1S1S0’ + I0S1S0 Logical Diagram: .Four : 1 MUX It has four inputs I0 I1 I2 I3 It has two selected inputs S0 S1 It has one output Y.

S0 Block Diagram: S1 Y0 1:4 DEMUX D Y1 Y2 Y3 Function Table: D S1 S0 Y0 Y1 Y2 Y3 D 0 0 D 0 0 0 D 0 1 0 D 0 0 D 1 0 0 0 D 0 D 1 1 0 0 0 D . It is the process of taking information from one output and transmitting several outputs.De-multiplexer: The term De-multiplexer means one into many.

or A < B . Comparators are used in a central processing units (CPU) and microcontrollers. less than or equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers A & B to determine whether: Type of Magnitude Comparator: Two Bit Magnitude Comparator A > B.Y0 = DS1’S0’ Y1 = DS1’S0 Y2 = DS1S0’ Y3 = DS1S0 Logical Diagram: Magnitude comparator: A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers as input in binary form and determines whether one number is greater than. or A = B.

B ⇒ 4-bits) A and B are two 4-bit numbers Let A = A3. LT). B1. where: 1.Block Diagram: 3 output signals (GT. EQ. EQ = 1 IFF A = B 3. B0 Inputs have 28 (256) possible combinations Not easy to design using conventional techniques . A1. GT = 1 IFF A > B 2. while the other 2 outputs are 0`s Four Bit Magnitude Comparator       Inputs: 8-bits (A ⇒ 4-bits . LT = 1 IFF A < B Note: Exactly One of these 3 outputs equals 1. B2. A2. A0 and Let B = B3.

Thus. EQ=1 IFF X3 X2 X1 X0 = 1. and A2=B2 (X2 = 1). A=B) IFF A3=B3 (X3 = 1).e. In a real computer. the clock is implemented by an oscillator. In other words. 1. whose output depends not only the present input and also on the past output. and A1=B1 (X1 = 1). the clock cycles determine when the states are “committed”.. Clock signal or pulses are determining the storage values. Sequential devices are clock-based. and A0=B0 (X0 = 1).Design of the EQ output (A = B) in 4-bit magnitude comparator          Thus Xi = 1 IFF Ai = Bi ∀ i =0. 2 and 3 Xi = 0 IFF Ai ≠ Bi Condition for A= B EQ=1 (i. followed by a tock-phase (high). Block Diagram: The sequential logical circuit requires memory to store intermediate data and use a periodical signal to determine when to store values. . EQ = X3 X2 X1 X0 Sequential logical circuit: The sequential logical circuit. Diagram for clock pulse: a clock cycle = tick-phase (low).

and many other types of systems. “A Flip-Flop circuit has two outputs. Applications of Sequential logical circuit: Flip-Flop Registers Counters Triggers State diagram Flip-Flop: The memory elements used in sequential circuit are called Flip-Flop.Difference between combinational and sequential logical circuit. Difficult to design. Flip-flops and latches are used as data storage elements. the output and next state depend not only on its current input. Memory unit are not required. Block diagram: . It is otherwise called as Multi-Vibrators. It depends on the present input values and past output values. one for the normal value (1) and another for complement value (0) of the bit store in it. and such a circuit is described as sequential logic. Such data storage can be used for storage of state. When used in a finitestate machine. Speed is low. It can also be used for counting of pulses. but also on its current state. Combinational logical circuit Sequential logical circuit. Cost is high. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers. Speed is high. communications. and for synchronizing variablytimed input signals to some reference timing signal. It depends on the present input values. And input are depends upon the types of Flip-Flop”. Cost is low. Memory unit are required. Easy to design.

Types of Flip-Flop: It has four types in it. It has two outputs are Q (Normal) Q’ (Invertor). Block Diagram: Logical Diagram: . SR Flip-Flop JK Flip-Flop D Flip-Flop T Flip-Flop SR Flip-Flop: The SR Flip-Flop has two inputs S (Set) and R (Reset). They are.

both the Qn+1 and Qn must be ‘indeterminate’ .Rules: When S = 0 and R = 0. Put Don’t care symbol ‘X’. When S = 0 and R = 1. the Flip-Flop ‘Reset’ to 0. Characteristic Table: Clock S R Present State Qn Next State Qn+1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 X 1 1 1 1 X Implementation of Qn+1 into K-Map: Extension Table: State No Change Reset Set Indeterminate . the output Qn+1 in its Present State Qn ‘No Change‘. When S = 1 and R = 1. When S = 1 and R = 0. the Flip-Flop ‘Set’ to 1.

This simple JK flip-Flop is the most widely used of all the flip-flop designs and is considered to be a universal flip-flop circuit. Block diagram of JK Flip-Flop: Logical Diagram: .Qn Qn+1 S R 0 0 0 X 0 1 1 0 1 0 0 1 1 1 X 0 State diagram of SR Flip-Flop: JK Flip-Flop: JK means Jack Kilby. It has four actions in it. It has two inputs J (Set) and K (Reset). who is invented JK Flip-Flop is similar to SR Flip-Flop.

When J= 1 and K = 0.Rules: When J= 0 and K = 0. means ‘Toggle’. Characteristic Table: Clock J K 1 0 0 Present State Qn 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 Implementation of Qn+1 into K-Map: Next State Qn+1 0 State No Change Reset Set Toggle . means ‘Set’ to 1. means ‘No Change‘. When J= 1 and K = 1. means ‘Reset’ to 0. When J= 0 and K = 1.

Eight possible combinations are achieved from the external inputs S. the values of Qn+1 and D are considered as “don’t cares”. The logic diagram showing the conversion from D to SR. Block diagram: . The D flip-flop has only one input called D. But. D is the actual input of the flip flop and S and R are the external inputs.Extension Table: Qn Qn+1 S R 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 State diagram of JK Flip-Flop: D Flip-Flop: D means delay. since the combination of S=1 and R=1 are invalid. and the K-map for D in terms of S. R and Qn are shown below. It is constructed from SR flip-flop by inserting invertors between S and R. R and Qn. It has two outputs Q and Q’.

When D = 1. means Reset.Logical Diagram: Rules: When D = 0. Characteristic Table: Clock D 1 0 Present State Qn 0 1 0 1 0 1 1 0 1 1 1 1 1 Implementation of Qn+1 into K-Map: Next State Qn+1 0 State Reset Set . means Set.

It has two outputs are Q (Normal) Q’ (Invertor). Block diagram: Logical Diagram: . It has only one input T.Extension Table: Qn Qn+1 D 0 0 0 0 1 1 1 0 0 1 1 0 State diagram of D Flip-Flop: T Flip-Flop: T Flip-Flop is otherwise called as Trigger or Toggle Tuple Flip-Flop. It is a modification of JK Flip-Flop.

Characteristic Table: Clock t 1 0 Present State Qn 0 1 0 1 0 1 1 0 1 1 1 1 1 Implementation of Qn+1 into K-Map: Extension Table: Next State Qn+1 0 State No change Toggle . means ‘Toggle’ (Complement). When T = 1. means ‘No change’.Rules: When T = 0.

The outputs from Q and Q from the "Slave" flip-flop are fed back to the inputs of the "Master" with the outputs of the "Master" flip-flop being connected to the two inputs of the "Slave" flip-flop. Block diagram: Logical diagram Master-Slave Flip-Flop .Qn Qn+1 T 0 0 0 0 1 1 1 0 1 1 1 0 State diagram of D Flip-Flop: The Master-Slave Flip-flop The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse. This feedback configuration from the slave's output to the master's input gives the characteristic toggle of the JK flip-flop as shown below.

Level triggering Edge triggering Pulse triggering . Types of triggers: There are three types. Then on the "Low-to-High" transition of the clock pulse the inputs of the "master" flip-flop are fed through to the gated inputs of the "slave" flip-flop and on the "High-to-Low" transition the same inputs are reflected on the output of the "slave" making this type of flip-flop edge or pulse-triggered. the "slave" SR flip-flop does not toggle. As the clock input of the "slave" flip-flop is the inverse (complement) of the "master" clock input. the Master-Slave JK Flipflop is a "Synchronous" device as it only passes data with the timing of the clock signal. When trigger appears it will goes to 1 and vice-versa. the circuit accepts input data when the clock signal is "HIGH". Trigger: A flip-flop changes from one state to another and comes back to its original state. The outputs from the "master" flip-flop are only "seen" by the gated "slave" flip-flop when the clock input goes "LOW" to logic level "0". This momentary change is called triggering of a flip-flop. There are clocked flip-flops which are triggered by the pulse generated by clocking signal. In other words. The transactions are set by the triggers. and passes the data to the output on the falling-edge of the clock signal. The clock pulse starts from initialize value 0. The state of the flip-flop can be changed by applying a momentary change to the Input signal. When the clock is "LOW". Then. The gated "slave" flip-flop now responds to the state of its inputs passed over by the "master" section. the outputs from the "master" flip-flop are latched and any additional changes to its inputs are ignored.The input signals J and K are connected to the gated "master" SR flip-flop which "locks" the input condition while the clock (Clk) input is "HIGH" at logic level "1".

i. Level Triggering: Level triggered flip-flops are dependent on the period of the pulse applied to it. +ve triggering: If the Flip-Flop changes it states when the clock is Positive.e.e.Each trigger has two types in it. The Shift Register The Shift Register is another type of sequential logic circuit that is used for the storage or transfer of data in the form of binary numbers and then "shifts" the data out once every clock cycle. The number of individual data latches required to make up a single Shift Register is determined by the number of bits to be stored with the most common being 8-bits (one byte) wide. or in parallel. If the flip-flop changes its state when the clock pulse applied is negative then it is called negative level triggering. all together. but the output does not reflect the input state until the falling edge of the clock pulse. Pulse Triggering: The term pulse-triggered means that data are entered into the flip-flop on the rising edge of the clock pulse. . one after the other from either the left or the right direction. Edge Triggering The edge triggered flip flops changes state either at positive edges or negative edges of the clock pulse applied and accordingly they are classified into Positive edge triggered Flip flops and Negative edge triggered flip flops. A positive or rising transition is achieved from positive edge flip flops and negative or falling transition is achieved from negative edge flip flops. They are. If a flip-flop changes its state when the clock pulse applied is positive then it is called as positive level triggering. As this kind of flip-flops are sensitive to any change of the input levels during the clock pulse is still HIGH. i. –ve triggering: If the Flip-Flop changes it states when the clock is Negative. The data bits may be fed in or out of the register serially. It basically consists of several single bit "D-Type Data Latches". hence the name "shift register". the inputs must be set up prior to the clock pulse's rising edge and must not be changed before the falling edge. i.e. one for each bit (0 or 1) connected together in a serial or daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on. eight individual data latches.

the directional movement of the data through a shift register can be either to the left.the parallel data is loaded simultaneously into the register. shift registers operate in one of four different modes with the basic movement of data through a shift register being:   Serial-in to Parallel-out (SIPO) . one bit at a time in either a left or right direction under clock control. one bit at a time. (right shifting) left-in but right-out. The individual data latches that make up a single shift register are all driven by a common clock ( Clk ) signal making them synchronous devices. (right shifting). or to convert the data from either a serial to parallel or parallel to serial format. The effect of data movement from left to right through a shift register can be presented graphically as: Also. Serial-in to Parallel-out (SIPO) 4-bit Serial-in to Parallel-out Shift Register .  Parallel-in to Serial-out (PISO) . Serial-in to Serial-out (SISO) . (left shifting) to the right.the register is loaded with serial data. Shift register IC's are generally provided with a clear or reset connection so that they can be "SET" or "RESET" as required. Generally.the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control.The Shift Register is used for data storage or data movement and are used in calculators or computers to store data such as two binary numbers before they are added together.the data is shifted serially "IN" and "OUT" of the register. In this tutorial it is assumed that all the data shifts to the right.  Parallel-in to Parallel-out (PIPO) . and transferred together to their respective outputs by the same clock pulse. (rotation) or both left and right shifting within the same register thereby making it bidirectional. with the stored data being available in parallel form.

and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the register. Basic Movement of Data through a Shift Register Clock Pulse No QA QB QC QD 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 0 0 1 0 4 0 0 0 1 . The truth table and following waveforms show the propagation of the logic "1" through the register from left to right as follows. Assume now that the DATA input pin of FFA has returned LOW again to logic "0" giving us one data pulse or 0-1-0. If a logic "1" is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic "1" with all the other outputs still remaining LOW at logic "0". This data value can now be read directly from the outputs of QA to QD. When the third clock pulse arrives this logic "1" value moves to the output of FFC ( QC ) and so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level "0" because the input to FFA has remained constant at logic level "0". The logic "1" has now moved or been "shifted" one place along the register to the right as it is now at QA. Lets assume that all the flip-flops ( FFA to FFD ) have just been RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level "0" i. Then the data has been converted from a serial data input signal to a parallel data output. The second clock pulse will change the output of FFA to logic "0" and the output of FFB and QB HIGH to logic "1" as its input D has the logic "1" level on it from QA.The operation is as follows.e. no parallel data output. The effect of each clock pulse is to shift the data contents of each stage one place to the right.

4-bit Serial-in to Serial-out Shift Register . Commonly available SIPO IC's include the standard 8-bit 74LS164 or the 74LS594. Serial-in to Serial-out (SISO) This shift register is very similar to the SIPO above. except were before the data was read directly in a parallel form from the outputs QA to QD. In practice the input data to the register may consist of various combinations of logic "1" and "0". this time the data is allowed to flow straight through the register and out of the other end. The SISO shift register is one of the simplest of the four configurations as it has only three connections. the DATA leaves the shift register one bit at a time in a serial pattern. the serial input (SI) which determines what enters the left hand flip-flop. the serial output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift register. hence the name Serial-in to Serial-Out Shift Register or SISO. Since there is only one output.5 0 0 0 0 Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the register and will remain there provided clocking of the register has stopped.

The data is then read out sequentially in the normal shift-right mode from the register at Q representing the data present at PA to PD. Commonly available IC's include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers. It is important to note that with this system a clock pulse is not required to parallel load the register as it is already present. 8.e. but four clock pulses are required to unload the data. all the data bits enter their inputs simultaneously. with the amount of time delay being controlled by the number of stages in the register. This data is outputted one bit at a time on each clock cycle in a serial format. Parallel-in to Serial-out (PISO) The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallelout one above. such as an 8-bit data word into serial format. . 4. it can be used to multiplex many different input lines into a single serial DATA stream which can be sent directly to a computer or transmitted over a communications line. Well this type of Shift Register also acts as a temporary storage device or as a time delay device for the data. to the parallel input pins PA to PD of the register.You may think what's the point of a SISO shift register if the output data is exactly the same as the input data. 16 etc or by varying the application of the clock pulses. Commonly available IC's include the 74HC595 8-bit Serial-in/Serial-out Shift Register all with 3-state outputs. 4-bit Parallel-in to Serial-out Shift Register As this type of shift register converts parallel data. The data is loaded into the register in a parallel format i.

this type of register also acts as a temporary storage device or as a time delay device. parallel-to-serial. in this type of register there are no interconnections between the individual flip-flops since no serial shifting of the data is required. high speed bi-directional "universal" type Shift Registers such as the TTL 74LS194. 74LS195 or the CMOS 4035 are available as a 4-bit multi-function devices that can be used in either serial-to-serial. 4-bit Parallel-in to Parallel-out Shift Register The PIPO shift register is the simplest of the four configurations as it has only three connections. the parallel input (PI) which determines what enters the flip-flop. right shifting. Similar to the Serial-in to Serial-out shift register. with the amount of time delay being varied by the frequency of the clock pulses. 4-bit Universal Shift Register 74LS194 . Universal Shift Register Today. and as a parallel-to-parallel multifunction data register. These devices can perform any combination of parallel and serial input to output operations but require additional inputs to specify desired function and to pre-load and reset the device. Then one clock pulse loads and unloads the register. the parallel output (PO) and the sequencing clock signal (Clk). The data is presented in a parallel format to the parallel input pins PA to PD and then transferred together directly to their respective output pins QA to QA by the same clock pulse. This type of register also acts as a temporary storage device or as a time delay device similar to the SISO configuration above. left shifting. hence the name "Universal".Parallel-in to Parallel-out (PIPO) The final mode of operation is the Parallel-in to Parallel-out Shift Register. This arrangement for parallel loading and unloading is shown below. Also. serial-to-parallel.

The Ring Counter In the previous Shift Register tutorial we saw that if we apply a serial data signal to the input of a serial-in to serial-out shift register. the same sequence of data will exit from the last flip-flip in the register chain after a preset number of clock cycles thereby acting as a sort of time delay circuit to the original signal. They can be configured to respond to operations that require some form of temporary memory. we can convert a standard shift register into a ring counter. delay information such as the SISO or PIPO configuration modes or transfer data from one point to another in either a serial or parallel format. Universal shift registers are frequently used in arithmetic operations to shift data to the left or right for multiplication or division. Then by looping the output back to the input. Consider the circuit below. and this is the principal operation of a Ring Counter. QD becomes the input of the first flip-flop. But what if we were to connect the output of this shift register back to its input so that the output from the last flip-flop. We would then have a closed loop circuit that "recirculates" the DATA around a continuous loop for every state of its sequence. DA.Universal shift registers are very useful digital devices. 4-bit Ring Counter .

the effect of the movement of the data bit from left to right through a ring counter can be presented graphically as follows along with its timing diagram: Rotational Movement of a Ring Counter . and like the previous shift register. the counter circulates the same data bit between the four flipflops over and over again around the "ring" every fourth clock cycle. is preset so that exactly one data bit in the register is set to logic "1" with all the other bits reset to "0". a "CLEAR" signal is firstly applied to all the flip-flops together in order to "RESET" their outputs to a logic "0" level and then a "PRESET" pulse is applied to the input of the first flip-flop ( FFA ) before the clock pulses are applied. But in order to cycle the data correctly around the counter we must first "load" the counter with a suitable data pattern as all logic "0's" or all logic "1's" outputted at each clock cycle would make the ring counter invalid.The synchronous Ring Counter example above. This then places a single logic "1" value into the circuit of the ring counter. This type of data movement is called "rotation". To achieve this. So on each successive clock pulse.

The main advantage of this type of ring counter is that it only needs half the number of flip-flops compared to the standard ring counter then its modulo number is halved. A "mod-n" ring counter will require "n" number of flip-flops connected together to circulate a single data bit providing "n" different output states. only four of the possible sixteen states are used. However. making ring counters very inefficient in terms of their output state usage. Johnson Ring Counter The Johnson Ring Counter or "Twisted Ring Counters". is another shift register with feedback exactly the same as the standard Ring Counter above. The "MODULO" or "MODULUS" of a counter is the number of states the counter counts or sequences through before repeating itself and a ring counter can be made to output any modulo number.Since the ring counter example shown above has four distinct states. 4-bit Johnson Ring Counter . So a "n-stage" Johnson counter will circulate a single data bit giving sequence of 2n different states and can therefore be considered as a "mod-2n counter". except that this time the inverted output Q of the last flip-flop is now connected back to the input D of the first flip-flop as shown below. it is also known as a "modulo-4" or "mod-4" counter with each flip-flop output having a frequency value equal to one-fourth or a quarter (1/4) that of the main clock frequency. as in our example above. For example. a mod-8 ring counter requires eight flip-flops and a mod-16 ring counter would require sixteen flip-flops.

As the inverted output Q is connected to the input D this 8-bit pattern continually repeats. "1000"(8) and repeat. the Johnson counter counts up and then down as the initial logic "1" passes through it to the right replacing the preceding logic "0". "0100"(4). "1110". For example. "0111". "1100". Truth Table for a 4-bit Johnson Ring Counter Clock FF FFA FFB FFD Pulse No C 0 0 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1 . A 4-bit Johnson ring counter passes blocks of four logic "0" and then four logic "1" thereby producing an 8-bit pattern. "0010"(2). "0011". "1111". "1000". "0001"(1).This inversion of Q before it is fed back to input D causes the counter to "count" in a different way. Instead of counting through a fixed set of patterns like the normal ring counter such as for a 4-bit counter. "0001". "0000" and this is demonstrated in the following table below.

The standard 5-stage Johnson counter such as the commonly available CD4017 is generally used as a synchronous decade counter/divider circuit. Standard 2. B and NOT-B. By connecting simple logic gates such as the AND or the OR gates to the outputs of the flip-flops the circuit can be made to detect a set number or value. ring counters can also be used to detect or recognise various patterns or number values within a set of data. The smaller 2-stage circuit is also called a "Quadrature" (sine/cosine) Oscillator/Generator and is used to produce four individual outputs that are each "phase shifted" by 90 degrees with respect to each other. 120 degree phase shift square wave generator by connecting to the data outputs at A. and this is shown below. A 3-stage Johnson Ring Counter can also be used as a 3-phase. 3 or 4-stage Johnson ring counters can also be used to divide the frequency of the clock signal by varying their feedback connections and divide-by-3 or divide-by-5 outputs are also available. 2-bit Quadrature Generator Output A B C D .As well as counting or rotating data around a continuous loop.

to drive a 2-phase full-step stepper motor for position control or the ability to rotate a motor to a particular location as shown below.QA+QB 1 0 0 0 QA+QB 0 1 0 0 QA+QB 0 0 1 0 QA+QB 0 0 0 1 2-bit Quadrature Oscillator. Count Sequence As the four outputs. As this section is only intended to give the reader a basic understanding of Johnson Ring Counters and its applications. they can be used with additional circuitry. A to D are phase shifted by 90 degrees with regards to each other. . Stepper Motor Control 2-phase (unipolar) Full-Step Stepper Motor Circuit The speed of rotation of the Stepper Motor will depend mainly upon the clock frequency and additional circuitry would be require to drive the "power" requirements of the motor. other good websites explain in more detail the types and drive requirements of stepper motors.

. decade Johnson ring counter with 10 active HIGH decoded outputs or the CD4022 4stage. divide-by-8 Johnson counter with 8 active HIGH decoded outputs.Johnson Ring Counters are available in standard TTL or CMOS IC form. such as the CD4017 5-Stage.