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D. Radhakrishnan

Indexing t m : Circuit theory and design, Digital circuits, CMOS circuits

Abstract: The paper presents a formal approach to the design of optimal CMOS networks by means of pass logic design techniques. Two approaches are given: one for CMOS pass networks and the other for CMOS gate networks. First, the paper gives an overview of pass networks, and then presents methods for the design of optimal CMOS pass networks. Different approaches are then presented for the design of CMOS gate networks. The designer is thus provided with a number of choices. The design of CMOS complementary logic, pseudo-nMOS logic, dynamic logic and domino CMOS uses the minterms and maxterms separately to form the network function, whereas cascode voltage switch logic (CVSL) uses them together. Finally, it is shown that optimal CVSL networks may not always be the best choice in terms of switching speed.

been found to offer a performance advantage of up to four times compared to CMOS/nMOS primitive NAND/ NOR logic families. The design of CMOS gate networks is treated differently by many authors. In many cases, they use intuition and cleverness to come up with optimal designs. This paper instead presents a formal approach to the design of optimal CMOS gate networks that uses pass logic design principles [4, 51. In fact, these networks belong to a special class of pass networks, where the pass variable is restricted to the set (0,1).

2

Pass networks

1

Introduction

Classical logic design is based on a set of basic logic gates: AND, OR, NAND, NOR, NOT etc. and their interconnection to obtain the desired switching function. These design techniques, when applied to MOS designs prove to be very inefficient. With regard to this, many different types of CMOS designs evolved. New approaches to the design of combinational circuits using MOS complex gates are discussed in Reference 1. Design types can be characterised into two major classes: CMOS pass networks and CMOS gate networks. CMOS gate networks pass either V,, or V,, to the output, depending on the state of input signals. CMOS pass networks, on the other hand, can, in addition, pass a variable to the output. CMOS gate networks include CMOS complementary logic, pseudo-nMOS logic, dynamic CMOS, domino CMOS and cascode voltage switch logic (CVSL). CMOS complementary logic is intrinsically slow and area inefficient. Pseudo-nMOS logic uses less area, but consumes static power. Dynamic CMOS has low capacitance and high current capability, but at the cost of circuit stability and operational complexity. Domino CMOS, on the other hand, combines the advantages of dynamic CMOS with the stability and simplicity of static circuits [l, 21. Limitations of this circuit technique are that all of the gates are noninverting and that each gate must be buffered. The CVSL family proposed by Heller et al. [3] has

Paper 75156 (ElO), first received 13th February 1989 and in revised form 14th March 1989 The author is with the NETECH Corporation, 60 Bethpage Drive, Hicksville, NY 11801, USA

I E E PROCEEDINGS-G, Vol. 138, No. I , F E B R U A R Y 1991

A pass network is an interconnection of a number of pass transistors to achieve a particular switching function. A detailed analysis and design procedure for pass networks is given in References 4 and 5. An overview of pass networks is given here to provide enough background for the reader to follow the rest of the material. A pass transistor is an nMOS (pMOS) transistor with the signal input fed to the drain (source) and the signal output taken from source (drain). The propagation of the signal through the transistor is controlled by a signal applied to its gate. In the case of an nMOS transistor, a logic 1 at the gate passes the input from source to drain and a logic 0 opens the source to drain circuit. A PMOS transistor exhibits similar behaviour, except for a change in the control signal logic level. If signals X and Y are connected to the gate and drain of an nMOS transistor, respectively, then this is represented as X ( Y ) and read as 'X passing Y ' . When both an nMOS and a PMOS transistor are used to pass the signal Y , the circuit is referred to as a CMOS transmission gate. The logic symbols for the above three types of pass gate are shown in Fig. 1.

v +

a

X

" I "

b

C

Logic representations for MOS transistors ( nMOS transistor for X(Y) I b PMOS transistor for X ( Y ) c CMOS transmission gate for X(YJ

Fig. 1

A series connection of a number of nMOS (pMOS) transistors passes the input to the output when all control signals are high (low). For an nMOS chain, this is represented by the expression X , X , . . . X,(V), where X , ,

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,

X , , . . . , X, are the control variables applied to the gates of the transistors and V is the pass variable. A product term P = X I X , . . . X,, passing an input signal V, is defined as a pass implicant and is denoted by P( V). A pass function is formed by the sum of a number of pass implicants. In a minimal pass function, all pass implicants belong to the set of pass prime implicants. A pass prime implicant is a pass implicant that cannot subsume any other pass implicant with a smaller number of literals in it that implies the same function. The major difference in the design of a pass network, as compared to a gate network, is that both Os and 1s of the function must be included. The pass network design procedures given in Reference 4, which make use of a K-map and modified Quine-McCluskey algorithmic approach, first select all essential pass prime implicants from the function and then a minimal set of pass prime implicants to cover the whole function. The K-map minimisation procedure is based on the following: (a) Each and every entry in the map must be covered at least once. (b) Pass implicants are identified in accordance with the following rules: (i) Each implicant PAC) consists of 2' adjacent cells in the K-map and the product term P i is formed in an identical manner to traditional implicants. in the implicant must be (ii) The pass variable equal to one of the elements from the set {O, 1, X i , Xi} throughout the implicant. A pass function obtained from a K-map may be factorised to reduce the transistor count in the implementation. The following example illustrates the design of an nMOS pass function by the use of a K-map. Example I: The K-map for a four-variable function is shown in Fig. 2. The nMOS pass function is given by

f = AD(1)

network is a special type of pass network where the number of branches from each node is limited to two [6]. The control variables for the two branches are always complements of each other. Hence, in the design of a BTS pass network the K-map is always divided into two equal halves at each step of the minimisation process. The

Fig. 3 nMOS pass network f o r Fig. 2 f = o(A(1) + C(A))+ d(S)+ 6C(B)

nMOS BTS pass function and its pass network for the K-map in Fig. 2 are given in Fig. 4. BTS pass networks, if designed properly, provide optimal realisations in most cases because of their inherent factorising nature. The only nonoptimal networks found so far correspond to XOR functions. The following

1

;I

f

+ CD(A)+ D ( B ) + A'C'(B)

Fig. 4 f=

"ca

nMOS BTS puss network for the K-map in Fig. 2

+ RO)) A(1))+ LxB) +

definition is useful for the minimisation of BTS pass functions.

Fig. 2

Four-ouriable K-map

**Factorisation of the above yields
**

f = D(A(1)

+ C(A))+ D ( B ) + A'C'(B)

Its implementation as an nMOS pass network is shown in Fig. 3. The nMOS pass function obtained from the above procedure may not always be minimal in its transistor count when implemented as a series-parallel network. This happens because in the K-map cells are shared by more than one pass prime implicant. To overcome this, a modified pass network structure is defined, called a binary tree structured pass network (BTS). A BTS pass

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Definition I: A complementary sum (CS) is defined as Si = PAX,) + PAX,), where X , and X , are either pass variables or are complementary sums themselves. From the above definition, a BTS pass function is a special case of a complementary sum Si, where Si denotes the switching functionfC71. For XOR functions, it is seen that factorisation of the function by taking the largest complementary sum Si gives minimum literals in its expression. These functions, when implemented, use the minimum number of transistors. BTS pass networks are also claimed to exhibit good fault detection properties [8]. However, the delays in BTS networks may be worse compared to a non-BTS pass network. Two problems that we face in the implementation of an nMOS pass function are: (a) The delay of the network depends on the number of transistors in the series chain. The behaviour of this chain is similar to that of an electrical transmission line and, hence, the delay increases as a quadratic power of the number of transistors in the chain. For short chains of pass transistors this poses no problem. (b) An nMOS transistor passes a good 0, but a poor 1, thus causing the deterioration of the logic level of a 1 input through the chain. On the other hand, a PMOS transistor passes a good 1, but a poor 0.

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The first problem can be overcome if we break longer chains of pass transistors into smaller ones by interposing buffer stages. The second has two solutions: (i) U e CMOS pass networks. s (ii) Design an nMOS pass network for the complementary pass functionf’ and then invert it to getf by means of a CMOS inverter. The inverter threshold may be adjusted to take into account the worst case logic levels on f‘. In addition to restoring the logic levels on the output, this solution gives some drive capability to the output signal.

3

CMOS networks

implicant is augmented with the 1 cells 0, 2, 8 and 10. The same is true of other pass implicants inf(N). The two pass prime implicants D’(B’) and CD(A) together

A

D

I

CMOS networks can be classified into two types, CMOS pass networks and CMOS gate networks. CMOS pass networks behave similarly to nMOS pass networks. They use fewer transistors compared to CMOS gate networks and can be used to advantage in the design of complex CMOS networks.

3.1 Notation The following notation is used in the remainder of this paper to represent the different switching functions: f: represents the switching function of a network. f(1): partial pass function obtained by combining the 1s of the function. f ( 0 ) :partial pass function obtained by combining the O of the function. s f(P): partial pass function for a PMOS pass network. f(N): partial pass function for an nMOS pass network. f”: Dual of functionf:

Fig. 5

E

n

I

CMOS pass networkfrom Fig. 3

cover all the 0 cells except cell 5. This 0 cell can be covered in three different ways. They are A’B(O), A’C‘(B’) or BD(A). If BD(A) is chosen instead of A’B(O), then f ( N ) = D’(B’) + D(C(A) + B(A)). This complementation needs 4 nMOS transistors. Similarly, the PMOS network, to cover the 1s of the function, is given by

f(P) D’(B’) + AD(1) + B’C‘(1). =

A second choice is possible where B’C‘(1) is replaced with A’C‘(B’).In both cases, the PMOS transistor count is five. The complete CMOS pass network is shown in Fig. 6.

The following relationship is valid for switching functions:

f = f ( l ) +f@)

3.2 CMOS pass networks CMOS pass networks use both nMOS and PMOS transistors in their implementation. An nMOS pass network can be easily converted to a CMOS pass network by the following two steps: (a) Replace all nMOS transistors with PMOS transistors if the pass variable is a 1 and with transmission gates if the pass variable is not constant (i.e. variable). (b) Complement all variables applied to the gates of PMOS transistors.

“--f

The modified pass network implementation for the nMOS pass network in Fig. 3, where a CMOS pass network has been formed by means of the above steps, is given in Fig. 5. A CMOS pass network designed in this manner may not always be optimal in its transistor count [SI. A minimal transistor design for a CMOS pass network must minimise the nMOS and PMOS transistors separately. A primary objective in the design of the nMOS network in a CMOS pass network is to pass all O s of the switching function, but it may also be used to pass some of the 1s if the transistor count can thereby be reduced. The same applies to PMOS networks also, with the logic values interchanged. The design of a minimal transistor CMOS pass network is illustrated by the following example. Example 2: Consider the K-map in Fig. 2. The nMOS pass network to cover the Os of the function is given by: f ( N ) = D’(B’) + CD(A) + A’B(0). The first pass prime implicant D’(B’) covers the 0 cells 4, 6, 12 and 14. To reduce the transistor count, this pass

IEE PROCEEDINGS-G, Vol. 138, N o . I , FEBRUARY 1991

1-B

1

Fig. 6

Optimal CMOS pass network for Fig. 3

3.3 CMOS gate networks CMOS gate networks consist of two separate networks, one to pull up the output to logic 1 and the other to pull down the output to logic 0 as shown in Fig. 7 [9].The pull up network is connected between the output node and VDo, and is purely a PMOS network @-net), so as to pass good 1s to the output. The pull down network, on the other hand, is connected between the output node and V,,, and is purely an nMOS network (n-net) so as to pass good Os to the output. By the nature of the interconnections in the two networks, it is guaranteed that only one of the networks (either p-net or n-net) will be activated by the inputs at any instant of time. Thus, any closed paths between the two supply rails are eliminated. The design of these structures simplifies the design of the p-net and n-net. Since these two structures basically pass a 1 and a 0, respectively, to the output, they belong

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to the special class of pass networks where the pass variables belong to the set {0, I}. Some additional notation is introduced here to simplify the presentation in the remainder of this paper:

r-7

'DD

7p-net

r-l

n-net

V554

4

f

I

CMOS gate network

Fig. 7

fp: Boolean expression for the p-net. This is obtained from f(1) by dropping the pass variable 1 and complementing all literals. f N : Boolean expression for the n-net. This is same as f(0) with its pass variable 0 removed.

From the above,f=yN. Five different realisations of CMOS complex gates are presented below. All of these realisations are derived by means of the pass network techniques mentioned in Section 2.

3.3.1 CMOS complementary logic

This structure consists of two complete networks, i.e. a p-net and an n-net. Each of these networks can be obtained from the K-map. For the K-map in Fig. 8 , f ( O ) andf(1) are given by:

+ BC'(1) + AB'C(1) = C(A'(1) + B(1)) + ABC(1) f ( 0 ) = A'C(0) + BC(0) + AB'C'(0) = C(A'(0) + B(0)) + AB'C(0)

f(1) = A'C(1)

\AE

Fig. 8

Three-variable K-mop

From f(1) and f ( O ) , four different realisations are possible for CMOS complementary gates: (i) Design the n-net and p-net separately, fromf(0) and f(l), respectively, (ii) design the n-net fromf(0) and form its dual for the p-net, (iii) design the p-net fromf(1) and form its dual for the n-net. (iv) Design the n-net and p-net separately, from f(1) andf(O), respectively. The CMOS complementary gate implementation produced by (i) above, for the K-map in Fig. 8, is given in Fig. 9.

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will be incurred because of the finite pull down time. Thus, the precharged node can discharge the output node of the following gate before the first gate is correctly evaluated. The n-net design is exactly the same as in the pseudonMOS gate. Thus, the two possible implementations of a dynamic CMOS gate for the K-map in Fig. 8 are as shown in Fig. 10.

In a cascaded set of logic blocks, each stage evaluates and causes the next stage to evaluate. Any number of logic stages may be cascaded, provided the sequence can evaluate within the evaluate clock phase. A single clock can be used to precharge and evaluate all logic gates within a block. The limitations of this structure include the charge redistribution problem and the buffering of each gate. Furthermore, only noninverting structures are possible. The two possible implementations for this gate, corresponding to the K-map in Fig. 8, are shown in Fig. 11.

3.3.5 Cascode voltage switch logic (CVSL) CVSL gates are formed by cascoding differential pairs of MOS transistors into powerful combinational logic tree networks to provide both true and false outputs. This is achieved at the expense of the extra routing, active area and complexity associated with double rail logic. However, the ability to generate any logic function is advantageous where automated logic synthesis is required. Two different forms of static CVSL gates exist: one is the fully differential type and the other is a simplified version of this. In fully differential CVSL, two complementary nMOS networks are connected to a pair of crosscoupled PMOS pullup transistors, as shown in Fig. 12. When the input switches, the nodesfandf’ switch in opposite directions, each node being either pulled high or low. Positive feedback, applied to the PMOS pull up transistors, causes the gate to switch. The n-nets may be further minimised from the fully differential form by means of logic minimisation algorithms to form the simplified static gate.

T”DD

c-l

-$

Fig. 10

0vss

-$

vss

Dynamic C M O S implementations of the K-map in Fig. 8

3.3.4 CMOS domino logic This is a modification to the clocked CMOS logic that allows a single clock to precharge and evaluate a cascaded set of dynamic logic blocks. A static CMOS buffer is included in each logic gate, as shown in Fig. 11. Owing

d

vss

Fig. 11

d-

C M O S domino implementations of the K-map in Fig. 8

to the presence of the inverter at the output, the n-net is designed according to the function. During the precharge phase (4 = 0), the output node of the dynamic gate is precharged high and, hence, the output of the buffer is kept low. As subsequent logic stages are fed from this buffer, transistors in subsequent logic blocks will be turned off during the precharge phase. When the gate is evaluated, the output will conditionally discharge, causing the output of the buffer, conditionally, to go high. Thus, each gate in sequence can make, at most, one transition 1 -+ 0. Hence, the buffer can only make a transition from 0 + 1.

IEE PROCEEDINGS-G, Vol. 138, No. I , FEBRUARY 1991

A K-map minimisation procedure and a tabular approach to the design of the n-nets is given in Reference 10. This procedure is based on the generation of four different lists: 10, 01, 1 and 0. For a function of n variables XI, . . . ,X, the transistor trees formed by the use of X,, 10 and 01 lists are always connected to the outputsfand f’ by transistors controlled by X, and X,. In addition, the control variables X iin each of the tree branches are arranged from top to bottom in ascending order, with magnitudes of i. This procedure does not always guarantee minimal transistor implementations, as shown later , in this paper. Furthermore, the four lists, 1401, 1 and 0,

87

.

. .-. . .

correspond to the pass implicants with pass variables Xi, X i , 1 and 0, respectively, where X i is an input variable for the Function. Hence, Chu’s procedure [lo] for the

The following example illustrates the design of a CVSL gate by means of procedure 1.

-Mf

f Fig. 12

Fully diflmential C V S L gate

Example 3: Consider the K-map shown in Fig. 14a. A minimal nMOS pass function for this K-map is given by f = DA(1) DA’B’(C) D(B’) B(D).

+

+

+

vss

ti

C

VSS C

design of CVSL gates can be described by the following procedure based on pass logic design. To apply this procedure, a minimal nMOS pass function is first derived from a K-map or by the modified Q-M technique presented in Reference 4. This pass function can always be represented by a sum of m pass prime implicants as

;i

I!“

/= A B C ( C )

Fig. 13

CVSL gatesfiom passfunctions

Procedure 1 : (a) Set i = 1. (b) (i) If = 0,then form a series nMOS network for Pi betweenf and V,, . (ii) If = 1, then form a series nMOS network for Pi betweenf’ and V,, . (iii) If 4 = X, then form a series nMOS network for Pi from V,, and connect it tofandf’ through transistors controlled by X and X, respectively. (iv) If = X , then form a series nMOS network for Pi from V, and connect it t o f a n d f ’ through transistors controlled by X and X , respectively. (c) If i = m, then stop. Else i = i + 1 and go to (b).

While procedure 1 is being applied to generate the n-nets, care must be taken to share the maximum number of transistors between the different transistor trees. Fig. 13 shows the n-nets for the functionsf= P(l),f= P ( O ) , f = P(Xi) a n d f = P ( X & where P = ABC.fandf’ correspond to the outputs of the gate. The PMOS transistors are not shown in Fig. 13.

a /= ABC(1) b / = ABC(0) c /= A B C ( X J d

The first term can be replaced by AB’(1) to give an alternative expression. To use procedure 1, the four pass implicants in f are selected one at a time. The first one, DA(l), satisfies condition (b) (ii) above and, hence, a series nMOS circuit with two transistors, controlled by the variables D and A, is connected betweenf’ and V,. This forms the leftmost branch in Fig. 14b. The second term DA’B’(C) satisfies condition (b) (iii) and, hence, a series nMOS circuit with three transistors, controlled by the variables D, A‘ and B, is first formed starting from Vss. This is then connected to f and f ’ through transistors controlled by C‘ and C, respectively. The transistor controlled by D in this branch is shared with the first pass implicant DA(1). In a similar manner, nMOS circuits for the other two pass implicants are also formed. The completed CVSL gate is shown in Fig. 146. A total of 12 nMOS transistors is used in this implementation. It should be noted at this point that the minimum number of transistors required for the implementation of

T v O O

\AB

0

b

Fig. 1 4 C V S L gate implementationdesigned according to Chu’s approach ( Four-variable K-map./= DA(1) + DA’B’(C) + D’(B‘) I B(D) b CVSL implementation

+

88

IEE PROCEEDINGS-G, Vol. 138, No. I , FEBRUARY 1991

the CVSL gate in example 3 is ten. This justifies our earlier statement regarding the nonoptimality of Chu’s procedure [IO] for the design of CVSL gates. One way to find a minimal transistor implementation is by trying all possible choices for the n-nets, N o and NI in Fig. 12, with maximum sharing of transistors between them. This can be done in the following manner. First, assume that the two n-nets are labelled N I and N o , as shown in Fig. 12. Their corresponding logic expressions are denoted by f N 1 and f N o , respectively. f N o can be obtained either from f(O), by simply dropping the pass variables, or from f ( l ) , by dropping the pass variables and complementing the expression. In a similar manner, f N , can be obtained either fromf(1) or fromf(0).fN, and f N o can then be factorised in different ways, which gives many choices for the implementation of the CVSL gate. This is illustrated by the following example. Example 4 : Consider again the K-map shown in Fig. 14a. From this K-map,

f ( 1 ) = B’D’(1)

(b) Connect the output node to V,. (c) Connect each input node of the pass network to eitherforf’ according to the following criteria: (i) If the pass variable is 0, then connect the input node to$ (ii) If the pass variable is 1, then connect the input node tof‘. (iii) If the pass variable is X, then connect the input node tof through a transistor controlled by X’ and tof’ through a transistor controlled by X. (iv) If the pass variable is X , then connect the input node to f ‘ through a transistor controlled by X and to f through a transistor controlled by X.

The following example illustrates the design of a static CVSL gate by means of procedure 2. Example 5 : Consider again the four variable K-map shown in Fig. 14a. This is redrawn in Fig. 16a. The BTS pass function for this K-map is given by f = D’(B’) D(A(1) A’(B(1) B’(C))). The BTS pass network is shown in Fig. 16b. This network can easily be converted to a CVSL gate by procedure 2 and the result is shown in Fig. 16c. As can be seen in Fig. 16c, it uses only ten nMOS transistors. It has been verified by an exhaustive search that ten is the minimum transistor count for this gate (example 4). BTS pass networks are shown to use the minimum number of transistors to realise a switching function [ S I . Hence, CVSL gates implemented by means of BTS pass networks also use the minimum number of transistors. The only exception to this is the XOR function. For XOR functions, however, as mentioned earlier, factorisation by taking the largest complementary sum Sigives minimum literals in the expression, thereby minimising the transistor count. These functions can then be used to implement minimum transistor CVSL gates. However, a search for an example that uses fewer transistors than the above design has been unsuccessful. Hence, the following conjecture.

+ BD(1) + CD(1) + AB’(1)

**Other choices exist for CD(1) and AB’(1).They are:
**

fN,

+

+

+

= B’(A

+ D’) + D(B + C )

+ D(A + B + C ) + C + D’)+ BD

fN, = fN, =

B’D‘

B’(A

or

f N , = B’(C + D ) + D(A + B)

Similarly, f(O), from the K-map, is given by f(0) = BD’(0) A’B’C‘D(0) and, hence, f N o= B D A’B’C‘D. If we take all possible combinations, this gives a total of 21 different implementations for the CVSL gate. One of the minimal transistor implementations is found by using f N , = B’(A + C + D‘)+ BD and f N o= B D + A‘B‘C‘D. This is shown in Fig. 15. Transistors B and B’

+

+

T“DD

1

Conjecture I : CVSL design by means of a modified version of a BTS pass network that uses variable sharing gives a minimal transistor realisation. The following example illustrates the design of an XOR function as a CVSL gate with a minimum number of transistors.

1

I

I

Fig. 15

/*,

= ED

+ B(A + C + D ) , f * , = E D + BDC‘A’

Optimal CVSL gate for the K-map in Fig. 14a

Example 6 : Consider the XOR function f(A, B, C, D)= A 8 B 0 C 0 D. A minimal transistor implementation of this function uses 14nMOS transistors and is given in Reference 9. An nMOS BTS pass function forf can be written as

are shared between the two n-nets. Thus, the total nMOS transistor count is ten. The method used in example 4 for optimal design of a CVSL gate is very laborious and time-consuming. Hence, a modified procedure for the design of an optimal CVSL gate is given below. This procedure is based on the optimality property of BTS pass networks. Procedure 2: ( a ) Form the BTS pass network for the function.

IEE PROCEEDINGS-G, Vol. 138, N o . I, FEBRUARY 1991

f = A’(B’(C‘(D) C(D’)) B(C‘(D)

+ + + C(D))) + A(B’(C‘(D’) + C(D))+ B(C‘(D) + C ( D ) ) )

+ AB}(C‘(D)+ C ( D ) )

**If we use the two complementary sums C ( D ) + C ( D ) and C‘(D’)+ C(D)inJ this can be factorised and rewritten as
**

f = {A’B’

+ {A’B + AB}(C‘(D’)+ C(D))

This function gives the same minimal transistor implementation as in Reference 9.

89

Even though CVSL gates designed by means of BTS pass networks give minimum transistor implementations, they may not always be the best choice in terms of switching speed. In many implementations, the stack

4

Conclusions

CD

00

E€dl

Different methods for the design of complex CMOS networks are given in this paper. All of these designs are shown to follow directly from the design of pass networks. These methods always provide a means for the design of optimal networks. It is also shown that CVSL designs based on BTS pass networks always use the minimum number of transistors.

5

Acknowledgment

This work was supported in part by the Idaho State Board of Education, USA under grant 696-XOO8. I also thank Dr. Gary K. Maki for many valuable discussions and for his unfailing support.

6

References

1 KRAMBECK, R.H., LEE, C.M., and LAW, H.S.: ‘High speed compact circuits with CMOS, IEEE J., 1982, SC-17, pp. 614619

2 MURPHY, B.T., EDWARDS, R., THOMAS, L.C., and MOLINELLI, J.J.: ‘A CMOS 32-bit single chip microprocessor’. Proceedings of IEEE International Solid-state Circuits Conference, Feb. 1981 3 HELLER, L.G., GRIFFIN, W.R., DAVIS, J.W., and THOMA, N.G.: ‘Cascode voltage switch logic: a differential CMOS logic family’. Proceedingsof IEEE International Solid-state Circuits Conference, 1984, pp. 1617 4 RADHAKRISHNAN, D., WHITAKER, S.R., and MAKI, G.K.: ‘Formal design procedures for pass transistor switching circuits’, IEEE J., 1985, SC-U), pp. 531-536 5 PEDRON, C., and STAUFFER, A.: ‘Analysis and synthesis of combinational pass transistor circuits’, IEEE Trans., 1988, 7 , (7). pp.

775-786 6 PETERSON, G.E., and MAKI, G.K.: ‘Binary tree structured logic

7

8

I

Fig. 16

PP I

Optimal C V S L gate realisation from BTS pass network

9 10

circuits: design and fault detection’. Proceedings of International Conference on Computer Design, Port Chester, NY, USA, Oct. 1984, pp. 671476 FEIZI, A.. and RADHAKRISHNAN, D.: ‘Multiple output pass networks: design and testing’. Proceedings of IEEE International Test Conference, Nov. 1985, pp. 907-911 JACKSHA, I., RADHAKRISHNAN, D., and MAKI, G.K.: ‘Reverse testing of NMOS binary tree structured networks’. Proceedings of 21st Annual Asilomar Conference on Signals, Systems and Computers, Nov. 1987, pp. 52S-530 WESTE, N., and ESHRAGHIAN, K.: ‘Principles of CMOS VLSI design’ (Addison-Wesley, Massachusetts, USA, 1985) CHU, K.M., and PULFREY, D.1.: ‘Design procedures for differential cascode voltage switch circuits’, IEEE J., 1986, SC-21, pp. 10821087

Biographical details

n Four-variable K-map of Fig. 140

b BTS pass network e CVSL network

height increases because of the BTS nature, which increases the switching delay. This can be seen by comparing the CVSL gates in Figs. 14b and 16c. For minterms m 5 and m, off, the switching network in Fig. 146 consists of the series circuit controlled by the two transistors B and D connectingf’ to Vss. On the other hand, in Fig. 16b, the switching network consists of the series circuit controlled by the three transistors D, A’ and B. This introduces an extra delay in switching, which slows the gate. Hence, in high performance designs, there is a tradeoff between speed and transistor count.

Damu Rndhakrishono received the BSc degree in Electronics and Communication Engineering from the University of Kerala, India in 1968 and the MTech and P h D degrees from the Indian Institute of Technology, Kanpur, India and the University of Idaho, Moscow, Idaho, USA, both in Electrical Engineering, in 1975 and 1983, respectively. From 1983 to 1985 he was a n Assistant Professor in the Department of Electrical Engineering, Old Dominion University, Norfolk, Virginia. Since 1985 he has been with the Department of Electrical Engineering, University of Idaho, Moscow, Idaho. At present he is the Vice President of the NETECH Corporation, New York. His current research interests include VLSI design, fault tolerant digital systems, computer architecture and switching theory.

90

IEE PROCEEDINGS-G, Vol. 138, No. I , FEBRUARY 1991

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