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REVIEW

Oxide Semiconductor Thin-Film Transistors: A Review
of Recent Advances
E. Fortunato,* P. Barquinha, and R. Martins

time,[1] challenging silicon not only in conventional applications but opening doors
Transparent electronics is today one of the most advanced topics for a wide
to completely new and disruptive areas
range of device applications. The key components are wide bandgap semiconlike paper electronics.[2,3] The key issues
ductors, where oxides of different origins play an important role, not only as
here are the ability to produce such semipassive component but also as active component, similar to what is observed
conductors at low process temperatures
in conventional semiconductors like silicon. Transparent electronics has gained
and to have highly smooth surfaces, charspecial attention during the last few years and is today established as one of
acteristic of amorphous structures, whose
electronic performances do not depend on
the most promising technologies for leading the next generation of flat panel
the degree of films disorder.[4] This new
display due to its excellent electronic performance. In this paper the recent
class of semiconductor materials, amorprogress in n- and p-type oxide based thin-film transistors (TFT) is reviewed,
phous oxides semiconductors (AOS) repwith special emphasis on solution-processed and p-type, and the major mileresent a revolutionary idea and exhibit a
stones already achieved with this emerging and very promising technology
stimulating combination of high optical
transparency, high electron mobility and
are summarizeed. After a short introduction where the main advantages of
amorphous microstructure.[5,6] Besides
these semiconductors are presented, as well as the industry expectations, the
that, AOSs do not have grain boundaries,
beautiful history of TFTs is revisited, including the main landmarks in the last
thereby obviating the primary limitation
80 years, finishing by referring to some papers that have played an important
of mobility in polycrystalline semiconducrole in shaping transparent electronics. Then, an overview is presented of state
tors, which is a huge advantage for process
of the art n-type TFTs processed by physical vapour deposition methods, and
integration. Other advantages include low
temperature deposition routes and ultrafinally one of the most exciting, promising, and low cost but powerful technolosmooth surfaces for suppressing intergies is discussed: solution-processed oxide TFTs. Moreover, a more detailed
face traps and scattering centres. Besides
focus analysis will be given concerning p-type oxide TFTs, mainly centred on
the advantages of this new technology
two of the most promising semiconductor candidates: copper oxide and tin
like the capability for providing real soluoxide. The most recent data related to the production of complementary metal
tions and overcoming many obstacles and
limitations of the conventional silicon
oxide semiconductor (CMOS) devices based on n- and p-type oxide TFT is also
technology, the used materials as well as
be presented. The last topic of this review is devoted to some emerging applicathe technology itself are environmental
tions, finalizing with the main conclusions. Related work that originated at
friendly and much less expensive.[7]
CENIMAT|I3N during the last six years is included in more detail, which has led
Although some initial attempts during
to the fabrication of high performance n- and p-type oxide transistors as well as
the 60s were done for SnO2[8] and ZnO[9]
the fabrication of CMOS devices with and on paper.
TFT channel layers, only forty years later,
with the work of Hosono,[10] Wager,[11]
Carcia[12] and Fortunato[13] a significant
1. Introduction
worldwide interest appeared, especially for active matrix for
organic light emitting diodes (AMOLED) technology, both in
Oxide semiconductors, especially the amorphous ones, are a
academia and industry. Besides the demonstration of display
promising class of TFT materials that have made an impressive
prototypes since 2005 by several companies (Toppan Printing,
progress particularly in display applications in a relatively short
Samsung Electronics, LG Electronics, AU Optronics, among
others), Samsung has released at the end of 2010 what they
boast proudly as one of the world’s finest and largest 3D Ultra
Prof. E. Fortunato, Dr. P. Barquinha, Prof. R. Martins
Definition (UD) TV with 70” diagonal and a sports resolution
CENIMAT/I3N, Departamento de Ciência dos Materiais
Faculdade de Ciências e Tecnologia
of 240 Hz that will meet the demands of 3D capability. SamFCT, Universidade Nova de Lisboa and CEMOP-UNINOVA
sung has claimed that the making of this device is the first of
2829-516 Caparica, Portugal
the kind on oxide semiconductor TFT technology that supports
E-mail: elvira.fortunato@fct.unl.pt
high pixel density, with a resolution of 3840 × 2160, which is
equivalent to 8 MP. Although the first transparent display has
DOI: 10.1002/adma.201103228

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been done using the conventional a-Si:H technology in 2005
by J. Jang et al.[14] only very recently Samsung announced the
mass production of transparent liquid crystal display (LCD)
panels, which enables a person to look right through the panel
like glass, and it consumes 90% less electricity when compared
to a conventional LCD panel using back light unit. This can
be achieved because a transparent LCD panel utilizes ambient
light such as sunlight, which consequently reduces the dependency on electricity for generating power.
As expected from the already obtained results, the future of
transparent electronics seems very promising, since from the
last available display market forecast by Displaybank,[15] transparent display would debut the market for the first time in 2012
and sharply grow to create $87.2 billion market by year 2025 as
can been seen in the semi-logarithmic plot in Figure 1.
Table 1 presents a summary and comparison of some of the
most important device properties for the different available
technologies: oxide semiconductors; amorphous Si; low temperature polycrystalline Si and organic semiconductors.

Elvira Fortunato received her
PhD degree in Physics and
Materials Science in 1995 at
Universidade Nova de Lisboa.
She has been a Full Professor
since 2012 in the Materials
Science Department of the
same University and has
been director of the Materials
Research Centre (CENIMAT)
since 1998. Fortunato pioneered European research
on transparent electronics, namely thin-film transistors
based on oxide semiconductors, demonstrating that oxide
materials may be used as true semiconductors.
Pedro Barquinha received
the PhD degree from
Universidade Nova de Lisboa
in 2010, in Nanotechnologies
and Nanosciences, with the
dissertation “Transparent
Oxide Thin-Film Transistors”.
His current research topics
are the study of materials
for transparent/flexible TFTs
and integration in circuits, as
well as the nanofabrication of

2. History of Oxide TFTs
The history of TFTs is the oldest one concerning electronic
devices and has more than 80 years. The invention of the TFT
occurred in 1925 and was patented in 1930 by J.E. Lilienfeld[21–23]
and O. Heil,[24] but at that time little was known about semiconductor materials and vacuum techniques to produce thin
films. Therefore, these first reports are actually concept patents
and no evidence exists about the production of devices. Still, in
these patents, the idea of controlling the current flow in a material by the influence of a transversal electrical field was already
present. One of Lilienfeld first patents, published in 1930,
describes the basic principle of what is known today as the
metal-semiconductor field-effect transistor (MESFET, Figure 2a),
while other, published three years later, already shows the concept of a device where an insulating material (aluminium oxide)
is introduced between the semiconductor (cooper sulfide) and

Figure 1. Transparent display technology evolution and global display
market (from Displaybank[15]).

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devices using FIB/EBL.
Rodrigo Martins received his
MSc degree in Amorphous
Semiconductor Technologies
in 1977, supervised by
W. Spear of Dundee
University/Scotland. He
got the PhD degree in
Semiconductors (1982)
and in 1988 the Aggregation
in Microelectronics, by
Universidade Nova de
Lisboa. He is Full Professor
in Microelectronics and Optoelectronics since 2001
in the Materials Science Department of the same
University and the head of department since 1996. In
1989 found the Centre of Excellence in Microelectronics
and Optoelectronics (CEMOP/Uninova) and in 1993 the
research material’s center, CENIMAT. Since 2004 he is
a member of the executive committees of the European
Materials Research Society (EMRS) and of the European
Materials Forum (EMF) and, since May 2011 the running
president of E-MRS. He is one of the inventors of the paper
and memory transistor and of the electrochromic transistor.

the field-effect electrode (aluminium), anticipating the so-called
metal-insulator-semiconductor field-effect transistor (MISFET,
Figure 2b).[25] It is also noteworthy that in the MISFET patent,

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REVIEW

semiconductor and a silicon monoxide insulator, using shadow
masks to define the patterns of these layers. He used thin films
of polycrystalline CdS semiconductor, similar to those develTFT properties
Oxide semi- Amorphous
Low-T
Organic
oped for photodetectors, deposited onto glass substrates. In one
conductors
Si
poly-Si
semiconpump down of his vacuum system, he would deposit a gold
ductors
source and drain, then deposit polycrystalline semiconductor
1 to 100
1 max
50 to 100
0.1-10
Carrier mobility
material over that and, finally, place a gate on top. This was a
[cm2 V−1 s−1]
coplanar process that was similar to what he used in the tricolor
0.1 to 0.6
0.4 to 0.5
0.2 to 0.3
0.1-1.0
Switching [V dec−1]a)
vidicon. It should be noted that Weimer’s work depended on
Leakage current [A]a)
depositions, not photoresists, which were used in developing
10−13
∼10−12
∼10−12
∼10−12
integrated circuits, just then getting under way. At first, these
Manufacturing cost
Low
Low
High
Low
deposited transistors weren’t very good. But then he placed an
Long term TFT reliability
High
Low
High
Low in air
insulator between the gate and the semiconductor material and
(forecast)
got what he called “beautiful characteristics”. His 1962 paper,
Yield
High
High
Medium
High
“The TFT — A New Thin-Film Transistor”, in the Proceedings of
RT
Process temperature [ °C] RT to 350
∼250
<500
the IEEE drew worldwide attention.[27]
Weimer used cadmium sulfide as the semiconductor matea)Highly dependent on dielectric.
rial because it was a high-resistivity semiconductor with which
he was somewhat familiar. Moreover, this was
a pre-requirement to allow the conductance
modulation via induced charges through the
insulator layer. He later used cadmium selenide. This made for an even better field-effect
transistor, not as good as silicon, Weimer
recalls, but quite respectable.
Figure 3 shows the cross sectional and top
views, output characteristics and a picture of
a 1-in square glass plate (mounted on a lucite
block) upon which three transistors have
been evaporated.
[
21
]
Figure 2. Initial patents of field-effect devices submitted by Lilienfeld: a) MESFET;
Although the birth of transparent elecb) MISFET.[23]
tronics is normally associated with reports on
ZnO TFTs presented in 2001-2003, there were
some tentative applications of oxide semiconductors as channel
the thickness specified for the insulating layer was 100 nm,
layers in TFTs forty years before, almost coincident with the
which is very similar to the one used nowadays in TFTs.[26] As
initial CdS TFTs reported by Weimer in 1961. In fact, back in
it is normal with many innovations at that time, its practical
1964, Klasens and Koelmans[8] proposed a TFT comprising
realization was delayed until adequate materials and technoloan evaporated SnO2 semiconductor on glass, with aluminium
gies were available for its fabrication. We can even say (and for
source-drain and gate electrodes and an anodized Al2O3 gate
most of us it could be surprising) that the TFT was the first
dielectric. Few details regarding electrical performance are prosolid-state amplifier ever patented.
vided and the transparent semiconductor is essentially used to
It took one more decade for the first TFT to be produced. This
demonstrate a new self-aligned lift-off process, where the SnO2
was achieved by Weimer at the RCA Laboratories in 1962.[27–29]
layer allows to expose the photoresist to UV light penetrating
Weimer used a vacuum technique (evaporation) to deposit
from the bottom of the structure in all the areas expect the one
gold electrodes, a polycrystalline cadmium sulfide (CdS) n-type
Table 1. Comparison between oxide semiconductor TFTs and the other
available technologies.[16–20]

Figure 3. a) Cross-sectional view and top view, b) A 1-in square glass plate (mounted on a lucite block) upon which 3 TFTs have been deposited and
c) Output characteristics of CdS TFTs reported by Weimer (adapted from [27]).

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showed that using r.f. magnetron sputtering
to deposit ZnO, similar electrical properties
could be achieved with room-temperature
processing of the semiconductor layer, even
if on this case fully transparent structures
were not demonstrated. After 2004 several
reports continued to appear on oxide semiconductor-based TFTs, bringing different
innovations to this emerging area. Some
of the most important achievements were:
ZnO TFTs exhibiting improved device performance (mainly regarding mobility) while
keeping low or even room temperature ZnO
processing;[35–37] non-vacuum processes to
produce the ZnO layers;[38] first simulations
of ZnO TFTs assuming that their properties are largely dictated by the polycrystalline
nature of ZnO;[39] new methods for extraction
of mobility in ZnO TFTs;[40] fully transparent
ZnO TFTs produced at room temperature;[13]
application of ZnO TFTs as UV photodetec[41,42]
exploration of SnO2 TFTs[43] and
Figure 4. Initial TFTs employing oxide semiconductors as channel layers: a) Schematic of tors;
the SnO2 TFT reported by Klasens and Koelmans in 1964, to show a new self-aligned lift-off use of In2O3 or ZnO nanowires as channel
process;[30]] b) Source-drain voltage-current characteristic of a single crystal ZnO FET, c) Picture layers.[25,44–46]
and layout of the ferroelectric Sb:SnO2 TFT proposed by Prins et al. in 1996.[31]
While most of the research work was being
devoted to binary oxides such as ZnO, In2O3
or SnO2, Nomura et al. suggested in 2003 to use a complex
shielded by the aluminium gate electrode, defining this way
InGaO3(ZnO)5 (or GIZO) single-crystalline semiconductor layer
the pattern of the source-drain electrodes (Figure 4a). In 1968,
in a TFT.[47] This layer was epitaxially grown on an yttria-staBoesen and Jacobs[9] reported a TFT with a lithium-doped ZnO
bilized zirconia substrate and allowed to obtain an impressive
single crystal semiconductor, with evaporated SiOx dielectric
effective mobility of 80 cm2 V−1 s−1, turn-on voltage of −0.5 V
and aluminium electrodes, but a very small drain current (ID)
and on/off ratio of 106. Even if a very high temperature of
modulation by applying a gate voltage (VG) and no ID saturation
1400 °C was necessary to attain this level of performance, this
were observed on these devices (Figure 4b).
paper made history, since it proves that high-performance oxide
Aoki and Sasakura[32] obtained similar poor electrical persemiconductor-based TFTs are a reality. And in fact, in the folformance in SnO2 TFTs in 1970. Only in 1996 oxide semiconlowing year Nomura et al. presented a work that definitely eviductors reappeared as channel layers, with two reports on ferdenced the enormous potential of oxide semiconductors (and
roelectric field-effect devices employing SnO2:Sb and In2O3, by
multicomponent oxides in particular) for TFT applications, by
Prins et al. and Seager, respectively.[31,33] Given that the main
demonstrating a transparent TFT on a flexible substrate using
intent of the authors was to demonstrate hysteresis associated
near-room temperature processing (Figure 5).[10] For this end,
with the ferroelectric behaviour, little information is provided
they used a PLD deposited amorphous GIZO layer as the semon these papers about device performance, but Prins and coiconductor. Even if the performance was far from the singleworkers, for instance, report a low on/off ratio of 60. Still, it
crystalline TFTs presented by the same authors, a saturation
is noteworthy to observe that full transparency is for the first
mobility of 9 cm2 V−1 s−1, threshold voltage of 1–2 V and on/off
time persuaded in a TFT and it is only severely affected by the
ratio of 103 could still be achieved, mostly because the low senSrRuO3 gate electrode (Figure 4c), although the authors mensitivity of these multicomponent oxides to structural disorder.
tion that they also fabricated a fully transparent TFT by using a
Nomura’s work opened the door for an impressively growing
heavily doped SnO2 gate electrode.
number of publications in the next years (see Figure 10 related
But good performing devices showing that oxide semiconto the evolution of papers published per year in this topic)
ductor-based TFTs could be a viable technology only started to
regarding the application of amorphous multicomponent oxides
appear in 2003, with the reports on ZnO TFTs by Hoffman et
as channel layers in TFTs. Several combinations of cations with
al, Carcia et al.and Masuda et al.[11,12,34] Hoffman and Carcia
(n-1)d10ns0 (n≥4) electronic configuration[4] started to be used
reported fully transparent devices (comprising TCO-based
for this end, being ZTO,[48–51] IZO,[52–55] and GIZO[6,56–60] the
electrodes), already allowing to obtain respectable performmost widely explored ones. With the continuous improvements
ance, comparable and even surpassing in some aspects the
verified on these devices, it is now common to obtain remarkone typically exhibited by a-Si:H and organic TFTs, mostly in
able electrical properties, considerably superior to a-Si:H[61] or
terms of mobility, which could be as high as 2.5 cm2 V−1 s−1.
organic TFTs, such as mobilities above 10 cm2 V−1 s−1, turn-on
However, the processing or post-processing temperatures of
voltages close to 0 V, on/off ratio exceeding 107 and subthreshold
the semiconductor necessary to obtain good devices were still
swing of 0.20 V dec−1, with the indium-based semiconductors
quite high, between 450-600 °C. But the work from Carcia et al.

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Adv. Mater. 2012, 24, 2945–2986

2945–2986 © 2012 WILEY-VCH Verlag GmbH & Co. which limits a detailed analysis. known as field effect. A dielectric layer is inserted between the semiconductor and a transversal electrode (gate).advmat. the fact that in bottom-gate strucrent. at least. being a very attractive technology that allows for transparent. as well as within the dielectric itself their interfaces) previously deposited. and photo-stability under electrical stress.[66. among others. used for the fabrication of a-Si:H TFTs. it seems that oxide semiconductors provide a solid and viable alternative for the present and future of TFTs. Furthermore. This second plane. low cost. low temperature and high performance devices. the photoreliability is affected by a large number to use highly doped semiconductor layers at the source-drain of parameters such as device structure/layout. top. Weinheim wileyonlinelibrary. semiconductor/ dielectric material composition. but rather by the dielectric. On the other hand. room temperature for application as source. Mater. passivation. depending on whether the gate having the added advantage of allowing for very low or even electrode is on top or bottom of the structure.[69] purposes. despite being as important as the channel layer on is mostly attributed to the fact that the crystallization process a TFT as its properties determines the charge accumulation at of the semiconductor material generally requires high temperathe dielectric/semiconductor interface. due to easier processing the optimization of highly conducting TCOs deposited near and enhanced electrical properties. the existence tures that could degrade the properties of other materials (and of defects at the interface.MaterialsViews. on parameters such as mobility. This last topic is tures (both staggered and coplanar) the semiconductor surface critical. In fact. shields the semiconductor material from the effect of the backBesides the huge development made on oxide semiconductors light present on these displays. It can also be explored as a way to easily modify its properties. being favoured if the limits to a large extent the device’s static and dynamic performsemiconductor is a flat and continuous film without any layers ance and reliability. Depending if the source-drain Figure 5. radation models have been proposed. A dedicated review on photo-stability should be taken into consideration in the future. Main landmarks achieved with TFTs. Figure 6. 24. temperature of these TFTs is dictated not by the semiconductor largely dictated by the materials used to fabricate the TFTs. it is important instance. Device Structure and Operation 2949 . Several degannealing or plasma treatments in a suitable atmosphere. For layer. left on a top-gate structure is normally preferred for poly-Si TFTs.com REVIEW 3. as is exposed to air can bring undesirable instability effects but there is not yet a consensus about the origin of this instability. Based on all this.www. KGaA. being the current modulation achieved by the capacitive injection of carriers close to the dielectric/semiconductor interface. nevertheless it is not explored in detail in this review. covering important drawbacks of the existing technologies. in silicon technology it is common In addition.[70] Inside these.com TFTs are three terminal field-effect devices. Adv. leakage curbeneath it. VD characteristics of a flexible substrate with transparent a-GIZO TFTs.67] the creation of ionized oxygen of a TFT. the structures are identigraph of the flexible TFT sheet bent at R = 30 mm presented by Nomura et al. As a-Si:H is light sensitive. Figure 6 shows a schematic of the main landmarks achieved with either generic TFTs or oxide based TFTs. room temperature processing. Furthermore.[26] Figure 7 shows the most common TFT structures. whose working principle relies on the modulation of the current flowing in a semiconductor placed between two electrodes (source and drain). As an example. a) ID.[62–65] cation of these TFTs in LCDs. nowadays the processing Each of these structures presents advantages/disadvantages. since the metal gate electrode Another important aspect deals with dielectric materials. Photo. fied as staggered and coplanar according to Weimer’s definition. the staggered bottom-gate configuration is widely to note that if flexible and fully transparent TFTs are envisaged. However. drain and gate the usage of this configuration is advantageous for the applielectrodes is also a crucial requirement. a coplanar the dielectric has been somehow forgotten or. is known that the photoreliability of oxide TFTs is mostly deteriofor instance by the facilitated adsorption of impurities during rated by negative rather than by positive bias stress. but other layers can also be introduced for different vacancies[68] and the photodesorption of oxygen molecules. including the trapping of The schematics in Figure 7 only show the fundamental layers photogenerated hole carriers. 2012.de www. in 2004 (adapted from [10]).and bottom-gate structures exist.are on opposite sides or on the same side of the semiconductor.

simply corresponding to the VG at which ID starts to increase as seen in a log Figure 8.[73] VT/VON: VT corresponds to the VG for which an accumulaTFTs are quite similar to other field-effect devices in terms of tion layer or conductive channel is formed close to the dielecoperation and composing layers. in staggered bottom-gate structures. i. while the maximum ID depends used in TFTs. in MOSFETs the silicon mode is preferable. KGaA. but generally enhancement insulating substrate. in TFTs semiconductor. rather than in a polycrystalline or amorphous one. Also. the temperatures involved in the fabrication of both devices are quite different: while processing temperatures exceeding 1000 °C are common for MOSFETs. turn-on This insulating layer can also have interesting effects on semivoltage (VON) and subthreshold swing (S).[74] tion with liquid crystal cells. such as the well-known MOStric/semiconductor interface.e.. respectively and are: mobility (μ). large ambiguity can arise on the determination of VT (for instance. 2012. which are absent in TFTs. However. Mater.www. higher performance naturally arises for MOSFETs. 24. the devices are designated between these devices. by using different parameters in the linear fittings). The minimum ID is generally ations of the electrical properties exhibited by the TFTs. conductor films that strongly interact with environmental speOn/off ratio: This is simply defined as the ratio of the maxcies such as oxygen or moisture. important differences exist whether VT is positive or negative.com 2950 wafer acts both as the substrate and the semiconductor.[11] VT can be determined using different methodologies.e.com © 2012 WILEY-VCH Verlag GmbH & Co.MaterialsViews. depending upon processors or memories. in order to form low-resistance contacts. in TFTs they are limited by parameters such as the softening point of the substrate. some of them readily seen by inspecting as enhancement or depletion mode. on the semiconductor material itself and on the effectiveness Additionally. between the source and drain FETs used in high performance applications such as microelectrodes (channel region). the insulating layer on top of the TFT structure of capacitive injection by the field effect. i. and also for oxide semiconductors. respectively. This can allow for more The most important TFT static characteristics are extracted accurate etching of the source-drain electrodes. For an n-type TFT. The concept of VON is largely used in literature. normally glass. this is achieved by an accumulation layer. given that the electrons flow in a single crystalline semiconductor. for instance to create the dielectric layer. First. act as an etch-stopper. ratio of conductance and transconductance. MOSFETs have p-n junctions at the sourcedrain regions. which is reflected in large variimum to the minimum ID. such as linear extrapolation of the ID-VG plot (for low VD) or of the ID1/2-VG plot (for high VD). Schematics showing some of the most conventional TFT structures. 2945–2986 . wileyonlinelibrary. This is related with another important difference in device operation: even if both TFTs and MOSFETs rely on the field effect to modulate Figure 7. among others. On/off above 106 are can work as an effective mechanical and chemical protection of typically obtained in TFTs and a large value is required for their the devices from subsequent processes. which for most common glass substrates does not exceed 600–650 °C. an insube formed close to that interface.72] and b.[75] Even if considering only one methodology.advmat.[71. while in MOSFETs an inversion region has to regions. Both types their typical structures (Figure 8). a n-type conductive layer lating film is often deposited on top of the semiconductor layer is created in a p-type silicon substrate. without damfrom the output and transfer characteristics shown in Figure 9a aging the semiconductor surface. according to the conductance of the semiconductor close the position of the gate electrode and to the distribution of the electrodes relatively to the to its interface with the dielectric.[71] In addition. Also. Comparison between the typical structures of MOSFETs and TFTs. Thus. Weinheim Adv. on/off ratio. because no VG is required to turn off the transistor. such as their integrasuccessful usage as electronic switches.de REVIEW www. such as CdSe. while TFTs use an are useful for circuit fabrication. This given by the noise level of the measurement equipment or by is particularly relevant for some of the first semiconductors the gate leakage current (IG). simplifying the circuit design and minimizing power dissipation. VG corresponding to a specific ID.

it indicates the necessary VG to increase ID by one decade:  S=  −1 dl og (ID )  d VG max √ d ID d VG 2 (4) 1 C W 2 i L Each methodology has its advantages and drawbacks. Finally.10–0.advmat.[77] Still. IGO and IHZO. Recent Progress of n-Type Oxide TFTs −1 Typically. μFE or μsat is presented. In order to have an idea about the scientific output in terms of papers produced. grain boundaries and other structural defects. Following Schroder’s nomenclature. 2945–2986 4. providing valuable insights into carrier transport.MaterialsViews. or in other words.[74] Mobility (μ): This is related with the efficiency of carrier transport in a material. it describes a situation where the channel is pinched-off. in the graphic of Figure 10 we show the evolution of published papers between 2001 and 2010 only related to n-type oxide based TFTs.[76] In a material.30 V dec and small values result in higher speeds and lower power consumption. reaching a total of 161 in 2009. consequently it is a widely used parameter. clearly showing effects such as mobility degradation due to contact resistance or increased interface scattering as VG increases. its effective length is smaller than L. 2012. note that in a TFT μ is modulated by VG. ID–VG plot. IZO. the latter probes the mobility of carriers as they are incrementally added to the channel. Weinheim wileyonlinelibrary. which limits a precise and detailed analysis of the work. it requires the determination of VT and is more sensitive to contact resistance (low VD). by plotting Equations 2. the VG necessary to fully turn-off the transistor. additional sources of scattering should be considered. Mobility of a TFT can be extracted using different methodologies. 24. Even if μeff includes the important effect of VG. μSAT does not require VT and is less sensitive to contact resistance.com µe f f = gd W Ci L (VG (2) − VT ) REVIEW Effective mobility (μeff): Obtained by the conductance (gd) with low VD: Field-effect mobility (μFE): Obtained by the transconductance (gm) with low VD: µE F = gm Ci W V L D (3) Saturation mobility (μsat): Obtained by the transconductance with high VD:  µs at = Figure 9.[40] While the former provides an average value of all the carriers induced in the channel. IZTO.[76. This last issue is also verified for μFE. In most manuscripts only a peak value of μeff. around 0. but μFE does not require VT and is easily calculated by the derivative of transfer characteristics. GIZO and others including ZTO.[40] Subthreshold swing (S): The inverse of the maximum slope of the transfer characteristic. ionized impurities. Typical a) output and b) transfer characteristics of a n-type oxide TFT. KGaA. However. Historical Overview The large number of research groups that are now working on transparent electronics have produced more than 541 papers between 2001 and 2010. μ is affected by several scattering mechanisms.1..77] On a TFT. so scattering mechanisms become less relevant for particular bias conditions.com 2951 . S << 1. However.e. (1) 4. In 2010 it was observed a small decrease © 2012 WILEY-VCH Verlag GmbH & Co.www. which is intrinsically not assumed by the classical model.de www. From the bar chart it is interesting to point out the sharp increase of publications appearing after 2006. 3 or 4 as a function of VG allows for a more complete understanding of the device physics. Mater. one may have:[77] Adv. such as the average (μavg) and incremental (μinc) mobility proposed by Hoffman. such as Coulomb scattering from dielectric charges and from interface states or surface roughness scattering. affecting directly the maximum ID and operating frequency of devices. ITO. The bar chart is divided into three main categories function of the semiconductor channel layer: ZnO. such as lattice vibrations. since the movement of carriers is constrained to a narrow region close to the dielectric/semiconductor interface. i.[26] Other methodologies can be found in literature.

4. and secondly it is possible to grow GIZO TFTs at temperatures lower than 150 °C with acceptable electrical performance. In the legend S means “solution processed” (data compiled from refs. the dielectric material and the interface are different and depending on the specific layout used we can have the source/drain electrodes completely overlapping the channel layer. We have done an exhaustive survey at WOK from Thomson Reuters and have tried to include all the work published in this topic until the submission of this review (July 2011).com merit: channel mobility. The analysis of the data denotes significant differences and trends. The effect of decreasing ds from 40 to 10 nm for IZO 2:1 is also shown. which pushes the researchers to investigate new materials as well as new technologies. due to the EF pinning above CBM as VG is increased. since they cannot be switched off. Barquinha et al. Mater. Weinheim Adv.279]). On the other hand. being the final devices annealed at TA = 150 °C. Number of oxide TFTs related papers published per year. If there is some work not included we would like to apologise the authors in advance. but this could be associated to the fact that we have now industries starting producing displays using this technology. above 4 eV. large differences are obtained for In2O3. Effect of oxide semiconductor target composition on the transfer characteristics of TFTs annealed at 150 °C: binary and ternary compounds. with a staggered bottom gate configuration. Ga2O3 and In2O3). the leading deposition technique is sputtering (more than 90%). Figure 12. used specific GIZO target compositions. Transfer characteristics are presented in Figure 11 and Figure 12 for binary/ternary and ternary/quaternary compounds. making it impossible to deplete the semiconductor with reasonable VG values. Besides the common part associated with the channel layer material. From the analysis of roughly 200 papers published on GIZO TFTs two aspects can be highlighted: first. Starting by the TFTs comprising binary compounds. were produced on silicon substrates with 100 nm thick PECVD SiO2.com © 2012 WILEY-VCH Verlag GmbH & Co.[277] All these technological/geometry aspects will affect the electrical properties of the TFTs limiting a real comparison of devices produced in different laboratories.www. From the graphic it is also interesting to see the evolution for solution processed TFTs especially after 2009 (a detailed analysis will be given in the next section). 2952 wileyonlinelibrary.[60] and by Barquinha et al. in addition to the large bandgap. being the trends of μFE and VON with composition shown in Figure 13. Effect of Oxide Semiconductor Composition concerning the number of GIZO TFTs publications. 2945–2986 .2. Besides that and since we do not want to repeat what is already published in some recent oxide based TFT reviews ([20.278. 2012. For these deposition conditions the carrier concentration (N) is ≈1018 cm−3 for In2O3. For this particular study the semiconductor layers were produced with an oxygen percentage of 0. b and c. This results in Figure 11.78–276] only dealing with GIZO TFTs. some work was already been reported by Iwasaki et al. even if a very large μFE is achieved for the In2O3 TFTs. Figure 10. electrical stability and passivation issues. KGaA.[6] While Iwasaki used a combinatorial co-sputtering study with 3 oxide targets (ZnO. presumably due to a very low N and large density of empty traps. the type of substrate and structures used are different. This is naturally related with the different electrical properties of the respective thin films. the ones corresponding to solution process are in Tables 2a.4%. we will present in this section a summary of the main achievements concerning n-type oxide TFTs. which renders the Fermi level (EF) to be very close to the conduction band minimum (CBM). Hence. [66. 24. specially the figure of Starting with the effect of GIZO composition on the TFTs electrical properties.MaterialsViews.de REVIEW www. The devices.advmat. Ga2O3 films have very large resistivity (ρ > 108 Ω cm). it is very hard to compare the TFT characteristics since. using e-beam evaporated Ti-Au source/drain electrodes. In the following paragraphs we will refer to the effect of chemical composition. In some cases the channel layer is not patterned. the devices are not usable as transistors. ZnO and Ga2O3 devices. respectively. Effect of oxide semiconductor target composition on the transfer characteristics of TFTs annealed at 150 °C: ternary and quaternary compounds.

Still. Furthermore.. background N decreases as gallium content in GIZO increases. This is justified by the fact that the depletion region created at the back (i.and on-states. Additionally. which is indicative of low N and/or large unfilled trap densities.[283] The effect of adding different amounts of gallium to IZO is shown in Figure 12. Mater.de www. for fixed In/(In + Ga) atomic ratios (compare GIZO 2:2:1 with 2:2:2). at least considering the range of deposition conditions used herein. the relative proportion of the cations directly controls the background N within a broad range. 2012.and off-states within the VG range used here. close to 0 VON.6 cm2 V−1 s−1). air exposed) surface of the active layer due to the interaction with environmental oxygen can be extended to the semiconductor/dielectric interface when a low ds is used. For IZO TFTs with In/(In + Zn) atomic ratios between 0. resulting in a considerable shift of VON toward more positive values. The trends verified for In/(In + Zn) in Figure 11 can also be observed in Figure 12. ρ ≈ 107 Ω cm.com 2953 . associated with the structural randomness. note that the problem of high background N can be attenuated by decreasing the semiconductor thickness (ds): for instance. Intermediate properties are obtained for In/(In + Zn) = 0.MaterialsViews.4%.www. However. with μinc ≈ 0. Matsuzaki et al.90 V dec−1) and the low maximum ID is indicative of a low μFE (1. In fact. Weinheim wileyonlinelibrary. although to a smaller extend than in gallium-free REVIEW very poor device performance. Rather than having carrier transport limited by grain boundaries. for In/(In + Zn) = 0. second. giving a fast indication of how stable the transistors are). Given the stronger bonds of gallium with oxygen. This means that N and μFE get higher for increased indium content. gallium incorporation can also lead to devices with considerably lower μFE and higher VON and ΔVON. by using IZO 2:1 ds = 10 nm rather than the “standard” 40 nm used for the oxide TFTs presented throughout this paper. the transistors can be fully switchedoff for VG <−7 V.com device performance is achieved using IGO[281] instead of IZO. Still. in the gallium-indium-zinc oxide system.02 cm2 V−1 s−1 and large ΔVON. μFE ≈ 0. This is naturally advantageous for large In/ (In + Zn). Adv..50 and 0.80 it is verified that the properties tend to get closer to the predominant binary compound. Devices annealed at 150 °C. above 6 V (ΔVON is the shift of VON after measuring the transfer characteristics three consecutive times.67. Two reasons can be pointed as the main justification for the moderate performance of the ZnO TFTs: first. as mentioned in the previous point.05 cm2 V−1 s−1 and VON > 10 V for TA = 500 °C. since the ratio of In/ (In + Zn + Ga) starts to decrease. which has direct implications on transistor performance. This arises as a direct consequence of the strong bonds that gallium forms with oxygen. Considerably better Figure 13. but only the IZO 1:1 TFTs are able to present clear on.80 both ID and μFE are similar to In2O3 TFTs. in general. making the EF shifting above CBM harder. also reported similar characteristics for Ga2O3 TFTs. in amorphous oxides carrier transport is mostly dictated by the potential barriers located around the CBM. This can be seen by comparing GIZO 2:4:2 with 2:2:1 and 2:2:2 compositions and is explained by the larger fraction of empty traps that need to be filled before EF reaches CBM or above it for materials with lower background N. besides other important drawbacks of IZO such as increased light sensitivity. 24.[280] ZnO seems to be the best binary compound for oxide TFT application. the higher structural disorder close to CBM increases the potential barriers that constrain the movement of free carriers. with VON > 20 V. Multicomponent amorphous oxides. which is not improved even for TA = 500 °C. the small slope of the transfer characteristics is synonym of a relatively high S (0. the existence of grain boundaries.advmat. allow for considerably better TFT performance than binary compounds. 2945–2986 © 2012 WILEY-VCH Verlag GmbH & Co. i.e. which are associated with depletion regions with high potential barriers that greatly affect the movement of free carriers. while for In/(In + Zn) = 0.e. In fact. since it permits the production of TFTs that clearly switch between off.50 the properties start to move away from those of In2O3 TFTs toward the ones of ZnO TFTs. a) μFE and b) VON obtained for TFTs with different oxide semiconductor compositions. which can easily be surpassed in properly processed films by increasing VG. on/off exceeding 106 and ΔVON ≈ 1 V are achieved on these ZnO TFTs. KGaA. with%O2 = 0. the difficulty in controlling the background N down to low values (at least <1016 cm−3) in IZO makes researchers (and industry) move for materials such as GIZO to fabricate the active layers of TFTs.[282] suppressing the generation of free carriers and raising ρ relatively to IZO films. for smaller In/ (In + Zn).

physically similar to μFE. by using the more conventional “average mobility”. the transconductance (hence μFE) is changed in different ways. in the unbiased state. intermediate properties to those observed in Figures 14a and b are observed. all the compositional effects also depend on the remaining processing parameters and so the specific results presented here for a particular composition should not be taken as an entirely strict rule: in fact. resulting in very high ρ. most of the traps associated with grain boundaries can be compensated by the background N. as proposed by Dehuff et al. hence large density of grain boundaries. As VG gets higher than these values. on ZnO TFTs produced on thermal SiO2.[26] An electron injection barrier at the source electrode may also contribute for this drop in μFE.[39] From these models it can be seen that the barrier height associated with the depletion regions at the grain boundaries is modulated by the total N. saturation is still not obtained.[52] A considerably different μFE–VG trend is observed for the ZnO TFT (Figure 14b). also obtained a similar μFE–VG trend in ZnO TFTs.com Stress measurements are crucial to understand instability mechanisms on devices as well as to predict if the technology is suitable to be used in integrated circuits. Nishii et al. Hence. the overall trends verified here for IZO[286–288] and GIZO[58. given the larger grain size and larger N of this material.com materials. Figure 14 illustrates this for GIZO 2:4:2 (amorphous) and ZnO (polycrystalline) TFTs. Some models describe quite well the behaviour of polycrystalline TFTs.[40] In fact.284. If the devices employing this semiconductor are annealed at a higher TA to allow for complete crystallization. resulting in a decrease of μFE. Weinheim Adv.[72. given the small S. 2012. EF is raised very quickly above CBM by VG. the dependence of © 2012 WILEY-VCH Verlag GmbH & Co.www. the conductive channel is drawn closer to the GIZO/SiO2 interface. both having semiconductor layers deposited with %O2 = 0. mobility saturation is not achieved in Hoffman’s paper. for smaller grain sizes the width of the depletion regions can extend deep inside the crystallites and even overlap with adjacent depletion regions. which happens for VG ≈ 20–30 V. For the ZnO TFTs presented in Figure 14b) the modulation of these effects by VG should be dominant and overshadow ZnO/SiO2 interface scattering. specifically oriented for ZnO TFTs. Furthermore. 2945–2986 . which probes the mobility of carriers as they are incrementally added to the channel.MaterialsViews. which contributes to increased scattering effects of the large density of induced charges. since the trap density is very low and very large μFE can be achieved when the small potential barriers associated with structural disorder are surpassed. essentially due to the polycrystalline structure of ZnO with small grain sizes. Physically. rather than averaging the mobility of all the carriers present in the channel for a given VG. Hence. designated by incremental mobility.de REVIEW www. For this case the increase of μFE with VG occurs gradually.4% and subjected to TA = 150 °C. Given that the PECVD SiO2 has a high breakdown voltage.advmat. even if VG is increased up to 100 V. Despite that the increase of VG above VON leads invariably to the enhancement of μFE. for compositions around 2:2:2 and 2:2:1. In2O3. saturation (and even decreasing) of mobility is observed by Hoffman for VG > 70 V.[35] For a large VG range. their effect should be considerably smaller. which can be due to different ZnO processing conditions (plausible given the considerably higher μFE achieved by Hoffman) and also to the effect of IG that for the present PECVD SiO2 starts to increase considerably for VG > 70 V. 4. namely the one proposed by Levinson in 1982[292] and more recently the one of Hossain.285] Nevertheless. Although grain boundaries can still affect the movement of the free carriers. note that mobility is extracted by Hoffman using a different methodology. which has contributions both from the background N and from the charges induced by VG. the VG range is extended for both cases in order to see all the μFE–VG regimes. Although measured in a smaller VG range. Mater. For the GIZO TFT (Figure 14a) an almost abrupt increase of μFE is verified after VON. 2954 wileyonlinelibrary.289– 291] devices were also verified by other authors. such as TA = 300 °C. since the properties start to be essentially dominated by the gallium content when this element is present. leaving more of the VG induced charges available to increase the transconductance. 24. based on a) GIZO 2:4:2 and b) ZnO. where μFE is maximum. a large number of reports regarding stable TFTs with close to 0 VON exist in the literature. KGaA. as predicted by conventional fieldeffect theory.60. Some comments should also be made regarding the other polycrystalline binary compound.[40] Still. depending on the composition and structure of the oxide semiconductor material.3. Transfer characteristics and μFE-VG plots measured for high VG for TFTs annealed at 150 °C. Naturally. By plotting μinc–VG for the data depicted in Figure 14b. Electrical Stress Measurements Figure 14.

2012.advmat. As mentioned in 4.g.4% and TA = 150 °C (Figure 15). resulting in a shift of VT (ΔVT). and depending on the passivation material and its deposition technique. suggesting that ionic drift mechanisms can be present in the device.g. the initial properties can be recovered some hours after stress without any subsequent annealing treatment.[72.310] SU-8. Mater.4. then for e-beam SiO2 and MgF2. a subsequent annealing treatment might be required to recover the initial properties of the transistors. Stress measurements were carried out by applying a constant VG = 20 V during 5 h. 24.301. while keeping the source and drain electrodes grounded. Based on this background. Nevertheless. as would be predictable given the larger ΔVON and hysteresis verified for these compositions. 2945–2986 Figure 16. As happens with other semiconductor technologies. since some oxygen from GIZO’s back surface can be removed during pump down time.[311] provides the best device performance. The results can be understood by investigating the effects occurring at the air-exposed surface of GIZO. KGaA.296–300] The same is verified here. different authors reported both improved stability (e.[277.308] Hence.306. annealed at 150 °C. which can give rise to trap states that degrade the stability. regardless of composition. 4. which is consistent with conventional charge trapping mechanisms rather than defect state creation or ionic drift. The effect of TA = 300 °C is also shown for MgF2.[293–295] reversible charge trapping at or close to the dielectric/semiconductor interface. deposited using Adv. being possible to switch off the transistors for VG < −7. This was in fact observed by different authors when exposing a GIZO surface to reactive ion etching (RIE) or to N2 and NH3 plasma treatments.www. for GIZO layers with%O2 = 0.[298.302] Note that the devices analyzed to compose Figure 15 were fabricated by employing the oxide semiconductor deposition conditions yielding the most stable devices.[30.[107]) when using proper passivation layers on oxide TFTs. © 2012 WILEY-VCH Verlag GmbH & Co.de www. Despite the largely negative VON. If a passivation layer is placed on top of the air-exposed surface.303] Despite GIZO 2:4:1 and 2:4:2 compositions provide the best performing and more stable transistors. device stability can be greatly improved using a passivation layer on top of GIZO.306. ΔVT obtained on gate-bias stress measurements during 5h. without physical substrate bombardment.com REVIEW Figure 15.[30. this can be justified by the non-vacuum deposition technique (spin-coating). creating acceptor-like surface states that attract electrons from the semiconductor. Transfer characteristics obtained for GIZO TFTs with different passivation layers (adapted from [277]). In fact.305]) and process yield (e. vacuum deposition techniques (e-beam and sputtering) result on the largest negative shifts of VON after passivation. MgF2 passivated devices also exhibit a negative shift of VON in consecutive transfer characteristics measurements.[222.2. Additionally. an accumulation layer can even be formed at the semiconductor/passivation interface for instance. if metal cation-oxygen bonds are broken during deposition[74. an epoxy-based negative chemically amplified resist that is commonly used for the fabrication of high aspect ratio features. higher structural disorder appears close to the CBM. the biggest variations occurring after passivation are verified for sputtered SiO2. MgF2 by e-beam evaporation and SU-8 by spin-coating. is the most frequent instability mechanism. To a large extent.304. as the ratio of In/(In+Zn+Ga) starts to decrease. different techniques: SiO2 by e-beam evaporation and sputtering.301. with 2:2:2 and 2:2:1 GIZO compositions resulting in the most unstable devices.5 V. oxygen adsorption is inhibited. GIZO composition on the electrical stability of oxide TFTs under gate-bias stress measurements was also studied. as well as counter clockwise hysteresis. generating oxygen vacancies that increase N.MaterialsViews. Weinheim wileyonlinelibrary.com 2955 . Effect of Passivation Layer Figure 16 shows the transfer characteristics obtained for GIZO TFTs having different passivation layers.309. In a non-passivated oxide semiconductor oxygen is physisorbed at the back surface. for oxide TFTs with different GIZO compositions. the intense substrate bombardment occurring during sputtering can break weak metal cation-oxygen bonds. If these conditions or other device materials (such as the dielectric layer) are changed.307] or if the passivation layer has a large density of positive charges.299. giving rise to a depletion region in the semiconductor that can even extend from the air-exposed surface to the dielectric/semiconductor interface.

can probably capture some electrons from GIZO. since grain boundaries act as preferential paths for impurities diffusion and leakage current. 24. The results presented above refer to an optimized PECVD SiO2 process at 400 °C. Improvements on the stability of passivated oxide TFTs are also reported in literature.304] temperatures. inhibiting oxygen adsorption/desorption processes that are known to be potentiated when ZnObased materials are subjected to electric fields. given that the increased capacitance can compensate the higher density of interface traps. which can contribute to reduced reliability. Even if SU-8 passivated TFTs without a subsequent annealing process exhibit a large negative VON (≈ −10 V). oxygen can be adsorbed as the stress measurement progresses. 2945–2986 . Ta2O5 and co-sputtered Ta2O5-SiO2 (denoted as TSiO) dielectrics. cross-linking of the SU-8 layer is fully achieved (confirmed by FTIR analysis) and remaining H+ ions available at the passivation layer (due to the decomposition of the photoacid generator present in SU-8). where results for constant ID stress measurements for passivated and non-passivated devices are plotted. its low EG and poor band offset relatively to GIZO result in a low yield/reproducibility and large off-currents. re-establishing a depletion layer close to the back surface of GIZO. and degraded interface properties[30.5.319]) and high-EG (e.%O2 = 0. but generally their growing and/or curing process is slow and/or requires high 2956 wileyonlinelibrary. being the final devices annealed at 150 °C. high power and/or low deposition pressure) that can negatively affect the growing films and their interfaces. but if low-temperature electronics are envisaged. Transfer characteristics of GIZO TFTs using sputtered SiO2.[303] Sputtered SiO2 results in poor overall device performance. Ta2O5 and co-sputtered TSiO dielectrics. with a low μFE (≈1 cm2 V−1 s−1) and high S (≈1 V dec−1). Effect of Dielectric Material The stability and overall performance of a TFT also depend to a great extent on the dielectric layer. as shown in Figure 17. where a barrier is formed by the passivation layer. Some relevant results regarding the integration of multicomponent/stack dielectric with oxide semiconductor technology are provided in ref [81]. SU-8 passivation also provides a remarkable improvement on the stability of the devices.[317] Multicomponent and/or stack dielectrics. A small and recoverable ΔVT = 0.g. By using co-sputtered TSiO a 4. alternative dielectrics and/or processing techniques need to be used. decreasing S and the operating voltage. composed by mixtures of high-κ (e.and Hfbased dielectrics for integration with GIZO TFTs. Chemically deposited organic dielectrics are being investigated for oxide TFTs with very promising results.[314. most of the high-κ dielectrics present at least two issues that can degrade performance and stability of oxide TFTs: (i) hey exhibit a polycrystalline structure and a rough surface. and Levy et al. Figure 18 shows transfer characteristics of GIZO TFTs employing sputtered SiO2. the performance is significantly improved after TA = 200 °C. for instance by Cho et al. Ta2O5 or HfO2[318. Most of these materials can remain amorphous even at temperatures exceeding 500 °C.315] Physical routes like sputtering are another possibility for low-temperature dielectric fabrication.com Figure 18. At CENIMAT|I3N we have been studying both Ta. in non-passivated devices.g.316] and (ii) high-κ dielectrics generally have lower EG and smaller band offsets relatively to the semiconductor than conventional SiO2 or SiNx:H. © 2012 WILEY-VCH Verlag GmbH & Co. KGaA. leading to a low breakdown voltage and high leakage current (IG). Mater.[30] Still. ΔVT vs stress/recovery time obtained from constant ID stress measurements of GIZO TFTs with and without SU-8 passivation. At this stage.de REVIEW www.MaterialsViews.4% and TA = 200 °C (adapted from [312]).www.advmat. 2012. SiO2 or Al2O3) have been studied to solve these issues. materials with a high dielectric constant (high-κ) are preferable. Devices annealed at 150 °C (adapted from [303]). widening the depletion layer close to the back surface and raising VT. preserving an overall high-κ and improving the band offsets relatively to the semiconductor. Even if Ta2O5 can provide considerably improved performance. The improvement over non-passivated devices should again be related with the GIZO’s back surface. but generally the low sputtering rates of dielectrics requires the usage of highly-energetic deposition processes (for instance. close to its interface with GIZO.[298.46 V could be obtained after 24h of stress at ID = 10 μA for the SU-8 passivated GIZO TFTs. Weinheim Adv. Hence.com Figure 17.[313] On the contrary.

An improvement of performance and stability of oxide TFTs with hafnium-based multilayer dielectrics was also verified by Chang et al. The small range of usable VG and lack of reliability/reproducibility of HfO2-based TFTs might be associated with the higher bombardment effects during film growth (higher Prf than Ta2O5). For these devices. 2012. charge trapping is again the only significant instability mechanism verified. Mater. the reproducibility. c) transfer characteristics evolution during constant ID stress measurements.. These sequential processes generally involve multiple photolithography and vacuum-deposition processes. on/off = 3 × 108 and S = 0. Hence.com 2957 . 2945–2986 REVIEW good compromise between the lower off-current of SiO2 and lower S and higher μFE of Ta2O5 are obtained. KGaA.20 V dec−1 are obtained.advmat.www. Direct printing of inorganic materials offers the possibility of depositing thin films using a direct additive patterning processes that enables the fabrication of high-performance and ultralow-cost electronics. This is due to the fact that the material in contact with GIZO is now a high-EG dielectric with a large conduction band offset with GIZO and also due the existence of discontinuities or interfaces between the different layers composing the dielectric that prevent the easy flowing of charges through the overall structure.[219. Devices annealed at 150 °C.com 4.6.2 V and S = 0. b) output characteristics. This leads to the developing of new and inexpensive technologies. which can broaden the band-tails and decrease the band-offsets with GIZO.321] by showing that ZnO TFTs employing an Al2O3/HfO2/Al2O3 dielectric exhibit a considerable suppression of charge trapping.4 V. Even if hysteresis is slightly increased for the multilayer structures when compared with TSiO (mostly due to the non-optimized SiO2/GIZO interface). patterning. even if some TSiO-based TFTs can sustain repeated and severe stress tests. But similarly to what was observed for tantalum-based dielectrics. Figure 19. Solution-Based TFTs Following Moore´s law the number of transistors per microelectronic chip has doubled every 18 months. and etching of selected semiconducting. devices with large electrical properties variations. being the initial properties of the devices fully recoverable after 48h recovery time (Figure 20b). conducting. © 2012 WILEY-VCH Verlag GmbH & Co. Nevertheless the cost of a chip per unit of area has remained relatively static Adv. μFE = 12.320. namely in their off-current.MaterialsViews. resulting in a reversible ΔVT ≈ 5 V after 12 h with ID = 10 μA. a narrow band offset is obtained with GIZO. But even with TSiO. reliability and overall transistor performance are significantly improved by using the multilayer structure (Figure 19). Although the ΔVT under constant ID stress measurements is higher than for transistors with S-TS-S. like for example printing technologies.de www. and Lee et al. A multilayer approach was also used to improve the properties of Hf-based dielectrics. being frequent to find in one substrate several devices with shorted-gates or.[303] multilayer dielectrics composed by TSiO stacked between two thin layers (≈20 nm) of SiO2 (denoted by S-TS-S) are being investigated.7 cm2 V−1 s−1. The dominant instability mechanism on these devices appears to be charge trapping at or close to the dielectric/semiconductor interface. Weinheim wileyonlinelibrary. traduced in lower hysteresis and lower ΔVT than similar TFTs with HfO2. VON = 1. in less extreme cases. and also with the polycrystalline structure of sputtered HfO2 films. with a very low IG that allows obtaining on/off exceeding 109. GIZO TFTs employing HfO2 dielectric exhibit a sharp increase of IG for VG > 5 V (Figure 20a). such as constant ID = 10 μA during 24h. S-HS-S-based TFTs exhibit μFE = 17. Besides that. which contribute to their high manufacturing costs. Current methods for the production of functional inorganic electronic devices are based on the sequential deposition. a multilayer stack with a HfO2-SiO2 layer between two thin layers of SiO2 (overall stack denoted by S-HS-S) results in considerably improved electrical properties. Electrical properties obtained for GIZO TFTs with S-TS-S dielectric: a) transfer characteristics. VON = −0.0 cm2 V−1 s−1. and insulating materials. 24. for the last three decades.22 V dec−1. making the reliability and reproducibility of GIZO TFTs using this dielectric an issue.

324] (ii) the performance of polymer LEDs is surpassing that of fluorescent tubes[325] and (iii) the efficiency of printed organic solar cells is reaching levels of 5–8%.MaterialsViews. the print nozzles do not contact the substrate. dielectric based on silicate cements and electrodes based on a Hg:In paste-like. in particular for: (i) the field-effect mobility of solution-processed organic TFTs has increased to levels exceeding those of amorphous silicon TFTs (∼1 cm2 V−1 s−1). KGaA. process-dependent performance variations and reliability issues are among the critical deficiencies with these materials. Mater.[322] inspired by the recent work reported by Weimer. it is an additive process. when Sihvonen et al. this work can be considered as a landmark in the printed electronics history. To date. in addition to other process issues. no masks or screens are necessary. Comparison between printing process and conventional microelectronic technology as well as the costs (normalized) associated to each process. For example they can have intrinsic mobilities of ∼1000 cm2 V−1 s−1. 2958 wileyonlinelibrary.de REVIEW www. Weinheim Adv. turning them inappropriate for applications like for example TFTs for active matrix backplanes for displays. Figure 20. 24.www. 2012. preserving delicate surfaces. Printing of functional inorganic materials is a challenging task with respect to processability and materials performance. The first efforts to print an electronic device backs to 1967. has demonstrated the possibility to make an insulated gate field effect transistor (he call them Graphic Active Devices– GAD’s) with all the materials printed: semiconductor based on CdS:CdSe inks. b) transfer characteristics evolution for S-HS-S TFTs during constant ID stress measurements. primarily because of the difficulty in preparing ink-jet-printable precursors. only a handful of inorganic materials have been ink-jet printed.323. There are many advantages to employing ink jet printing for electronic circuits: it is a digital process. inorganic semiconductors are the basis for almost all-high performance microelectronic devices. Figure 21 compares the cost reduction between ink-jet and conventional microelectronic technologies.[19. low current density. with lifetimes over 50 years and clock speeds beyond 1 GHz. Although many soluble organic semiconductors have been explored for this purpose. 2945–2986 . On the other hand.com Figure 21. materials are applied only where desired and it is a non-contact process. Low mobility. Electrical properties obtained for GIZO TFTs with Hf-based dielectrics: a) transfer characteristics for HfO2 and S-HS-S devices. mainly due to © 2012 WILEY-VCH Verlag GmbH & Co. where a reduction of 64% is achieved by using for example direct printing. Ink-jet printing of inorganic materials for the formation of active devices is relatively new compared to the research done with respect to organic materials. Printed electronics is today an emerging disruptive technology which has made an impressive progress specially in the last 10 years. Although these preliminary results were not spectacular (see Figure 22).[326] Ink-jet of inorganic materials for making active devices was relatively rare compared to organic materials.com especially for TFTs.advmat. their functional performance generally falls short of expectation. Devices annealed at 150 °C.

Mater..[330] b) Transfer characteristic (linear VD = 0. Concerning the coating method for a solution process the most used are: spin-coating. a) Examples of the tested insulated gate field effect devices used by Sihvonen et al. Figure 22.333] these results evidence the potentialities of a very simple and low cost technology for device and circuit applications.[328] it is still challenging to obtain high mobility semiconductor layers at low temperatures. 2012. printing (ink-jet.de www.[329–331] succeed to increase the channel mobility of Li-doped ZnO TFTs processed at a temperature of 400 °C for values higher than 85 cm2 V−1 s−1 using ambient spray pyrolysis and blends of precursor solutions based on zinc and lithium acetates (Figure 24).[327] reported ZTO Figure 23. They use a bottom gate configuration and a high/κ dielectric based on ZrO2 oxide layer also deposited by spray pyrolysis.[334] and Lee et al. 2945–2986 © 2012 WILEY-VCH Verlag GmbH & Co. Adv. In 2007 Chang et al. usually the devices present some instability due to the large surface area of the nanoparticles. More recently. among others) and chemical bath deposition (see Figure 23). Concerning the nanoparticle approach.com REVIEW the difficulty in preparing ink-jet printable precursors.[327] Some efforts have been done in the last five years and basically two main routes have been followed: nanoparticles and molecular precursor approach. which in some cases over estimates the channel mobility. In their work the TFT mobility was 0. Although the possibility to deposit inorand b) Output characteristic of a device using an inorganic ink-dielectric layer (adapted from ganic semiconducting films directly from [322]). KGaA. fabricated with Li-doped ZnO films on a 126 nF cm−2 ZrO2 dielectric (adapted from [331]). top-contact TFTs with channel width W = 500 μm and channel length L = 20 μm. Solution type and coating methods used for solution-procand IZO by spin coating respectively. micro contact. Despite the fact that the semiconductor channel layer is not patterned. 24.com 2959 . at temperatures of 600 °C. a) Contour plot of the field-effect electron mobility as a function of channel length (L) and the [Li+1]/[Zn+2] molar mass ratio.5 V) and c) Output characteristics of bottom-gate.[332.2 V and saturation VD = 3. essed TFTs. Figure 24.advmat. In opposition. whose main bottleneck is still the process temperature that limits the type of substrates that can be used.2 cm2 V−1 s−1 and the on/off ratio was 107. in the order of 900 °C. but for a very high TA.www. Adamapoulos et al. Weinheim wileyonlinelibrary. The inset shows the TFT architecture used. a solution to achieve high levels of device performance was already reported in 2001 by Ohya et al. the molecular precursors approach has the advantage of mixing different metal precursors in the same solution.MaterialsViews.

Mater.53 104 [359] 2010 ZnO QD Spin coating 600 0.65 cm2 V−1 s−1 and on/off ratios of 107.28 105 [360] 2010 ZnO NP Spin coating 500 0.1 103 [354] 2009 Li-ZnO Spin coating 550 3.31 10 [362] Spray pyrolysis 370 24 - [363] 2011 - 450 8.1SC 106 [350] 2008 DC.1-IJ.5 105 [345] 2007 ZnO NR Spin coating 270 1.com Table 2a. NW–Nanowires. QD–Quantum dots Table 2b.www. KGaA.26 - [353] 2009 ZnO Spin coating 200 1.28 V dec−1 were obtained. without mediated hydrolysis. In 2011 Kim et al.jet and Spin coating 500. Weinheim Adv. 2945–2986 .e.2 × 10−5 4 ZnO NP Spin coating 200 [356] 2009 Li-ZnO Spray 400 54 107 [330] 2010 Spin coating 200 0. Bath Dep. Previous work on solution-processed ZnO oxide semiconductors.2 106 [346] 2007 ZnO NW Ink-jet 250 2-4 104 [347] 2007 7 - - 1175 10 [348] 2007 ZnO Spin coating 70 0.3 107 ZTO Spin coating 500 5 108 wileyonlinelibrary.39 106 [357] 2010 7 ZnO 10 ZnO Spin coating 500 1.4 × 10 [74] 2008 ZnO-Zr Spin coating 300 4. A μFE = 5.62 103 [365] 2007 4 IZO Spin coating 600 16 10 [327] 2007 ZTO Spin coating 500 1. which is incompatible with the use of plastic substrates and in some cases due to the different thermal expansion coefficients cracking could occur. This approach allowed demonstrating for the first time solution-processed films of InZnO and InGaZnO that have comparable electronic performance as sputtered films.[338] have recently discovered a novel precursor approach to obtain ternary and quaternary oxide semiconductors.29 10 [358] 2010 ZnO Spin coating 90 7. NR–Nanorods.4 105-106 [342] 2006 ZnO Chemical bath 100 0. Banger et al. 2012.07 107 [355] 2009 3 1..5 104 [364] 2011 Spray pyrolysis 400 85 106 [331] 2011 ZnO NR ZnO NP–Nanoparticles. i. 700 3.[339] succeed to produce In2O3. From these results we would like to highlight the work of Yang et al.6 cm2 V−1 s−1) with an on/off ratio of 5 × 107 and subthreshold swing of 0.[335. They got mobilities of 7. IZTO. in 2009 the first reports on solution-based GIZO TFTs start to appear (see Table 2c and Figure 25). More recently and due to the superior electrical properties of GIZO TFTs. So far. nitrates and halides in coordinating solvents and generally they require elevated temperatures.02 × 10−3 - [351] 2008 10−3 ZnO NW ZnO NP ZnO NP Spin coating 150 8. these methodologies have focused on the use of metal acetates.2 10 [11] ZnO NR Spin coating 230 0.1 105 [361] 2010 3 2011 Li-ZnO ZnO Spin coating 400 0.com They obtained mobilities of 16 cm2 V−1 s−1 using a bottom gate configuration and a 100 nm thick thermally grown SiO2 dielectric on top of a silicon substrate.2 × 10−3 - [352] 2008 ZnO Spray 400 15 106 [329] 2009 ZnO Spin coating 500 5. 3. 24.6 105 [341] 2005 ZnO NR Spin coating 230 1. IMO oxide semiconductors Material 2960 process Temp [ °C] Mobility [cm2 V−1 s−1] On/off Reference Year ZTO Spin coating 600 16 105 [334] 2007 SnOx Ink-jet 500 3. In the same year Nayak et al. Taking this into account. After dispersing and spin coating the solution a post-bake at 95 °C was used. SC 150 1. IZO.MaterialsViews.336] where they report NP-GIZO TFTs using the hydrothermal method (180 °C @ 10 atm) to transform a solution type metal hydroxide into an oxide nanoparticle gel.7 106 [367] 2008 [368] 2008 [369] 2009 IZO Spin coating 500 7. The main advantage of this technique is the possibility to perform the chemical reactions at a much lower temperature since the precursor is optimized © 2012 WILEY-VCH Verlag GmbH & Co. decompose only at higher temperatures.[337] present high performance a-GIZO TFTs obtained by sol-gel spin coating technique.advmat. This so called “sol-gel on chip” method allows a controlled low-temperature processing from metal alkoxide precursors that.de REVIEW www.25 105 [343] 2006 ZnO Spin coating 500 5. usually higher than 400 °C to complete precursor decomposition and avoid undesirable contamination of the semiconductor.8 cm2 V−1 s−1 (μsat = 9.56 104 [349] 2007 ZnO Spin coating 400 1.63 106 [74] 2008 ZnO Ink. Material ZnO Process Temp [ °C] Mobility [cm2 V−1 s−1] On/off Reference Year Chemical bath 900 - - [328] 2001 2003 7 ZnO Spin coating 700 0. ZTO and IZO TFTs by solution process at a temperature as low as 200 °C by using a clever and new self-energy generating combustion chemistry. mobilities ∼10 cm2 V−1 s−1 and similar threshold voltage stability with process temperatures as low as 230 °C (see Figure 26). 300 6.1 106 [366] 2008 In2O3 Spin coating 400 43. Previous work on solution-processed ZTO.25 105 [344] 2007 ZnO Chem. that is based on the use of organic-inorganic metal alkoxide precursors able to produce dense amorphous films. AIO.

24. eliminating the need for high.57 10 [378] 2010 Mg-IZO Spin coating 450 2.com Material process Temp [ °C] Mobility [cm2 V−1 s−1] On/off Reference Year ZTO Spin coating 500 14. a reaction that generates heat by its strong exothermic nature.02 107 [372] 2009 AIO Spin coating 350 19. SWNT– Single wall nanotube Process Temp ( °C) Mobility GIZO Spin coating 400 2 105 [391] 2009 GIZO Spin coating 400 1. Even if the processing temperatures are in most of the cases relatively large (>400 °C). it can be seen that multicomponent oxides such as ZTO and IGZO lead to the best overall performance.36 105 [387] 2011 ZTO Spin coating 500 2. 2012. Taking into account the increased interest associated to solution-processed TFTs. externally applied processing temperatures (see schematics in Figure 27). which leads to the complete removal of organic constituents.77 108 [384] 2011 IZO Spin coating 230 ∼10 108 [338] 2011 AIO Spin coating 250 2.3 107 [379] 2010 IZTO Spin coating 400 90 105 [380] 2010 7 Sc-IZO Spin coating 500 2. 2945–2986 for auto-combustion.98 109 [377] 2010 9 IZO Spin coating 450 6.1-0. associate. This group succeed to produce a flexible printed In2O3 TFT with a mobility of 6 cm2 V−1 s−1 for TA = 200 °C on transparent polymer substrates (Figure 28). The self-generated heat of synthesis provides a localized energy supply (similar to a laser annealing).76 10 [390] 2011 ZTO Spin coating 250 1. We have decided not to include the values for Vth and subthreshold swing due to the lack of data. Figure 29 represents the evolution in the number of papers.MaterialsViews.3 107 [376] 2010 ZTO Ink-jet 500 4.3 106 [335] 2010 GIZO Spin coating 400 0. KGaA. with some of the results obtained in TFTs already approaching the ones typically obtained when using physically deposited semiconductors.com 2961 .www. In this study they use a redox based combustion synthetic approach using as fuel acetylacetone or urea and nitrates as oxidizers.87 10 [386] 2011 IZTO Spin coating 600 4.advmat.02 106 [375] 2010 ZTO Spin coating 500 27. p-Type Metal Oxide Based TFTs: Emergent Devices The enormous success of n-type oxide semiconductors and its application to TFTs has motivated the interest in p-type oxide based semiconductors also to be applied to TFTs. In this way the oxide formation is done at low heating temperatures.de www.65 10 [336] 2010 GIZO Spin coating 95-hydrothermal 2. Mater.85 106 [396] 2010 7 GIZO Spin coating 400 5.94 106 [382] 2010 Ink-jet 300 1. Continued 4. Tables 2 summarize published work on solution-processed TFTs since 2001.02 106 [389] 2011 6 ZTO Spin coating 500 0.6 106 [369] 2009 IZTO Ink-jet 600 30 106 [371] 2009 ZTO Ink-jet 600 1. as in the case of n-type conductivity.17 104 [402] 2011 Adv.7.5 108 [388] 2011 Zr-ZTO Spin coating 500 4.5-2 10 [398] 2010 GIZO Spin coating 600 6.7 108 [360] 2010 Al-ITO Spin coating 500 13.6 - [373] 2009 IZTO Ink-jet 600 30 106 [374] 2009 ZTO-Zr Spin coating 500 4.37 106 [385] 2011 3 IGO Spin coating 400 0. potentiating the use of low cost and flexible substrates in association with printed electronics. until now there is no report about p-type oxide TFTs with performance similar to that of n-type oxide TFTs.8 10 [397] 2010 GIZO gravure printed 550 0. As a general trend.1 108 [370] 2009 ZTO Ink-jet 500 0.81 106 [379] 2010 GIZO Spin coating 600 1.96 106 [394] 2009 GIZO Ink-jet 450 0. Previous work on solution-processed GIZO oxide semiconductors.4 107 [399] 2011 GIZO Ink-jet 500 1.05 104 [392] 2009 GIZO Dip Coating 500 0.4 106 [393] 2009 GIZO Spin coating 450 0.25 106 [289] 2009 Material On/off Reference Year GIZO Spin coating 400 0.03 104 [395] 2009 7 GIZO Spin coating 95-hydrothermal 7.24 - [401] 2011 GIZO SWNT Spin coating 450 0. P-type oxide TFTs are mainly limited by the low hole mobilities since the mobility of valence band derived carriers is generally lower than that of conduction band derived carriers. where a visible increase is obtained especially for the last 2 years.3 104 [358] 2010 7 GIZO Spin coating 500 0.76 107 [339] 2011 Table 2c.4 107 [400] 2011 GIZO Spin coating - 0. there is an increasing number of works where lower temperatures are being used. Weinheim wileyonlinelibrary. In fact comparing to what happened in organic TFTs we are facing exactly the same but in an opposite © 2012 WILEY-VCH Verlag GmbH & Co.8 107 [383] 2011 ZTO ZTO Spin coating 500 6. Papers published until July 2011 are also presented. However. REVIEW Table 2b. in some cases around 100 °C.06 10 [381] 2010 Hf-IZO Spin coating 500 1.

Figure 27.com Figure 25.408] One of the main advantages of organic materials are the low temperature fabrication which allow lightweight flexible displays.[407. Organic materials have been studied for more than 50 years and the significant improvements in the semiconducting properties associated to the discovery of electroluminescence in organic diode structures make these materials as excellent candidates for low-cost electronic and optoelectronic structures. a) Photograph of a transparent.de REVIEW www. © 2012 WILEY-VCH Verlag GmbH & Co. b) Transfer and c) Output characteristics of IZO TFTs produced under hydrolysed conditions (adapted from [338]). Schematic comparison of the decomposition profile of a combustion precursor and conventional sol-gel reaction (adapted from [340]).MaterialsViews. 24.www. Weinheim Adv. 2945–2986 . and environmental stability to oxygen and moisture. 2962 wileyonlinelibrary. the overall performance parameters are still poor compared to oxide materials. KGaA. Moreover. since most of organic TFTs reported in the literature are p-type[403–406] while the oxide ones are n-type. Even though organic TFTs have been the topic of intense research for the past few decades. processability. Mater.advmat. b) Transfer and c) Output characteristics of GIZO TFTs with different compositions (adapted from [337]). Figure 26. the n-type organic semiconductors have much lower mobilities (10−2 to 10−1 cm2 V−1 s−1)[323. such as in CMOS. a) Cross sectional SEM image of GIZO (311) TFT.410–412] limiting their field of applications.com way. namely the low mobilities (< 2 cm2 V−1 s−1)[409] poor stability and device-to-device variability as well as improved performance. hydrolysed films. 2012.

nevertheless at that time and until the beginning of space explorations. the energy production from the sun by photovoltaic effect was just a curiosity. The p-type character of Cu2O is attributed to the presence of negatively charged copper vacancies (VCu). 2012. carrier conduction path (valence band) is mainly formed from the oxygen p asymmetric orbitals. a) Optical photograph of a flexible combustion-processed In2O3 device on Acrylite (30 nm Al gate electrode/41 nm a-alumina dielectric.7.[20. In the following sections the discussion will be focused on the present available data on two emergent and promising p-type TFTs based on copper oxide and tin monoxide. At present. by allowing the use of highly compact circuits with low power consumption. abundant availability. Rectifier diodes based on this semiconductor were used industrially as early as 1926[414] (Figure 30b) and most of the theory of semiconductors was developed using the data on Cu2O devices. more precisely Cu2O. In. Both the CuO (monoclinic) and Cu2O (cubic) are p-type semiconductors with a band gap of 1. So. the inset shows an optical image of an ink-jet printed Al/41 nm a-alumina dielectric. which introduce an acceptor level at about 0. and c. Cu2O was regarded as one of the most promising materials for application in solar cells[28.6 eV respectively[418] and in some experimental conditions Cu2O shows mobilities exceeding 100 cm2 V−1 s−1. Sc. almost all reported oxide TFTs are based on n-channel devices.1.1–2. and low-cost production.[415–417] Oxides of copper are known to show p-type conductivity and are attracting renewed interest as promising semiconductor materials for a wide range of optoelectronic devices. Y.[419–422] Besides that. 4. Number of solution-processed oxide TFTs related papers published per year. Solid-state devices based on Cu2O semiconductors are known for more than 90 years even before the era of germanium and silicon devices. away from silicon.b. La.com REVIEW Figure 28. The data was taken from Tables 2a. Recently much attention has been given to Cu based semiconductors. non-toxicity. Copper Oxide Figure 29. delafossite family CuMO2 (M = Al. Ga. which severely limit the carrier mobility.3 eV above the valence band © 2012 WILEY-VCH Verlag GmbH & Co. p-type oxides have very low carrier mobility compared to their n-type counterparts.1 and 2. of which the Adv. etc. KGaA. 24.278] For p-type oxides. b) output characteristics and c) transfer characteristics (adapted from [339]). cuprous oxide. Mater.de www. it will shape the electronics of tomorrow by allowing the production of complementary metal oxide semiconductors (CMOS).[413] (Figure 30a). There are two common forms of copper oxide: cuprous oxide or cuprite (Cu2O) and cupric oxide or tenorite (CuO).9–2.com 2963 . which is the main obstacle in obtaining high performance p-channel oxide TFTs. a key device to fuel the microelectronics revolution in the so-called technologies of information and communication. The simple binary oxides based on ZnO and NiO have also been studied as promising p-type semiconductors.MaterialsViews. 2945–2986 The first evidence of the semiconductor properties in a metal oxide was done on copper oxide.[425] The potential for solar cell application have been recognized since 1920.424] due to its high-absorption coefficient in the visible region. but without relevant results until now. Weinheim wileyonlinelibrary. in 1917 by Kennard et al.advmat.) is the most important. Achieving high performance p-type oxide TFTs (that have an advantage over n-type TFTs since the TFT supplies hole current for the anode of the organic light emitting device [OLED] without affecting the drain current in the saturation mode) will definitely promote a new era for electronics in rigid and flexible substrates. Figure 31 shows a comparison between these two compounds in terms of optical properties and crystal structure.www. Moreover.423.

de REVIEW www. C is the piece of lead used for contact.advmat. Despite the high quality of CuO thin films with mobilities it has been difficult to produce TFTs with high channel mobilities.[445] chemical vapour deposition[446] and thermal oxidation. the dotted line marked L showing the periods of illumination. where the simplest candidates are oxygen vacancies.[440–443] sol-gel. a) Evidence of the photo electromotive effect on Cu2O. Cu2O crystallizes in a cubic structure.447. A series of readings of the potential at intervals of a minute. a slow drift of potential followed by recovery in the dark but lagging by 2–3 minutes (adapted from[413]). It is a black solid with an ionic structure. However. mainly because of the difficulty of controlling the hole density in the channel layer.[444] plasma evaporation.com Figure 31.com molecular beam epitaxy. here the top of the VB is composed of fully occupied hybridized orbitals (Cu 3d and O 2p) with Cu d sates dominating the top of the VB.MaterialsViews.3 eV and a deep donor level at 0. High quality Cu2O thin films have been grown by several methods. Weinheim Adv. One of the first reports on p-type oxide based TFTs was proposed by the Wager’s group using as channel layer a CuZnOx © 2012 WILEY-VCH Verlag GmbH & Co. b) Example of the first rectifier assembly. Figure 32b shows a pictorial representation of the most important defects in Cu2O and Figure 32c reveals the simple electronic model proposed by Brattain.[439] electrochemical deposition. In this work the authors found that with the introduction of a buffer layer the crystallinity increases associated to an increase in the grain size and under oxygen optimum growing conditions they achieved mobilities in the order of 256 cm2 V−1 s−1 with a hole concentration of 1014 cm−3 as it is shown in Figure 33.[427] consisting of a compensated semiconductor with one acceptor level at 0. as we will present in this paper. Copper (II) oxide or cupric oxide belongs to the monoclinic crystal system. B is mica insulation. and F is terminal connected to mother copper (adapted from [414]). in which the top of VB is mainly formed from localized and anisotropic O 2p orbitals which leads to a low hole mobility due to hopping conduction. Figure 30. like sputtering. acceptor and donor levels with a ratio slightly larger than 1 and less than 10. This characteristic has impeded the application of Cu in integrated circuits.[419] that it is possible to grow high quality Cu2O thin films by reactive magnetron sputtering using a Cu target at temperatures in the order of 200 °C followed by a thermal treatment of 600 °C. Mater. KGaA. Copper (I) oxide or cuprous oxide is one of the principal oxides of copper.[426] It was also proposed by some authors a co-existence of both intrinsic. Recently it was shown by Li et al.www.[425.[431] Generally in order to achieve high quality Cu2O thin films the depositions involve high substrate temperatures. A is oxidized surface of copper strip. (VB).[432–435] pulsed laser deposition.448] Among all these methods sputtering is a relatively cost effective process that can be used for large area deposition and thermal oxidation is the simplest.[429] In contrast to the majority of metal oxides. It is well known that Cu oxidizes easily at low temperatures.428] The nature of the donor levels is not completely clear being even controversial. inexpensive and most conventional method to obtain copper oxide. Apparently illumination produces.9 eV from VB. 2012. 24. depending on the size of the particles. The compound can appear yellow or red. besides the sudden effect. 2945–2986 . TFTs prepared from Cu2O have shown very poor performance (field-effect mobilities and on/off current ratio were below 1 cm2 V−1 s−1 and 102 respectively).[436–438] 2964 wileyonlinelibrary. the high oxidation rate of Cu and high reduction rate of its oxides at low temperature can be exploited for some potential applications. which is always higher than 500 °C.[430] Figure 32a illustrates the chemical bond between an oxide ion and a cation that has a closed-shell electronic configuration.[427.

Other detrimental features of this device include requiring an extremely high post-deposition annealing temperature of 800 °C which limits the use of low cost substrates and the fact that the channel layer is not completely transparent. Two years later in 2010 Fortunato et al. Since VON is so large.01 cm2 V−1 s−1. a) Chemical bond between an oxide ion and a cation that has a closed-shell electronic configuration.advmat. they subject the films to a post-deposition annealing under various oxygen partial pressures. In order to investigate the origin of the obtained poor mobility. VON ≈ −60 V. The types of defects are mainly oxygen vacancies and the appearance of the CuO phase.26 cm2 V−1 s−1 and an on/off ratio lower than one order of magnitude.[420] reported TFT using single phase Cu2O films grown by pulsed laser deposition at Adv.[431] demonstrated the possibility to produce p-type transparent oxide semiconductors based on Cu2O by reactive magnetron sputtering at © 2012 WILEY-VCH Verlag GmbH & Co.com REVIEW Figure 32. This device shows poor performance with a very high ON voltage (≈−60 V) and a low channel mobility (≈0.[419] semiconductor[30] (Figure 34). the pinch-off condition was not achieved so that this device exhibits a “soft” saturation. This value explains consistently the small field-effect mobility observed in these Cu2O TFTs. 2012.com 2965 . the performance of the integrated TFTs were quite moderate (Figure 35).3 eV and a deep donor level at 0. ID–VD curves for a p-channel TFT employing CuZnOx as the channel layer and a thermal SiO2-silicon substrate bottom gate. Mater. and W/L = 5 (adapted from [30]).www. 24. In the same year Matsuzaki et al. Even though the hole mobility was very high (∼90 cm2 V−1 s−1). KGaA. Weinheim wileyonlinelibrary.[449] From optical measurements it was revealed that subgap states exist in all the films and their amounts were increased by post deposition annealing irrespective to the oxygen partial pressure used. For this device. They have obtained mobilities of 0. c) a simple electronic model proposed by Brattain. Figure 34. Mobility (a) and resistivity and hole density (b) of Cu2O thin films with LTB-Cu2O as a function of oxygen flow rates. μINC ≈ 0.9 eV from VB (adapted from [431]).de www.MaterialsViews. Figure 33. with a compensated semiconductor with one acceptor level at 0. These subgap states were observed even for the best film with an estimated defect density >1018 cm−3. 2945–2986 700 °C on MgO substrates.01 cm2 V−1 s−1). b) representation of the more important defects in Cu2O. The channel layer is subjected to a post-deposition furnace anneal in air at 800 °C in air.

4 cm2V−1s−1 (Figure 37).44 and 1. The films were grown on SiO2/Si substrate by pulsed laser deposition under different substrate temperatures using a top-gate structure with a high-κ HfON as gate dielectric. The Cu2O films are polycrystalline presenting a strong orientation along the (111) plane.72 nm.g. which is associated with an increase of the grain size.[450] have produced Cu2O thin films deposited at room temperature using rf magnetron sputtering. the Hall mobility was improved from 0. The obtained values for the channel mobility are much lower than that of the corresponding films. The low temperature process combined with the good electrical performance of the devices at this early research stage opens new doors for the future optimization of p-type oxide-based devices and for their integration in CMOS structures allowing their use in flexible. the deposition/annealed temperature. substrate/dielectric material. Concerning the optical properties. As it was written by Wager in his book Transparent Electronics:[30] “The development of robust p-type semiconductors for use as channel materials in TFTs remains a considerable challenge.www. The paper from Zou et al. Mater. For annealing temperatures higher than 200 °C a transformation to a CuO phase is observed. respectively. channel mobility and on/off ratio. They © 2012 WILEY-VCH Verlag GmbH & Co. by ion bombardment and/or plasma reduction during deposition of the other device layers. After annealing in air at 200 °C for 10 hours. low cost and transparent electronic circuits. Also in 2010 Sung et al. swing of 0. 2945–2986 . Bottom gate structured TFTs fabricated using CuO layers operated in a p-type enhancement mode with an on/off ratio of ≈104 and field-effect mobility of 0. indicating that a high density of traps exists in the film channel or/and the channel/gate dielectric interface. The obtained optical bandgaps of the Cu2O and CuO were 2. trap states were still formed even in the high mobility films independent of the impurity phases. which re-opens the study on this semiconductor with almost 100 years. Weinheim Adv.advmat. which is also revealed by the low subthreshold. Nevertheless. e.de REVIEW www. from 8.com Figure 35. room temperature followed by a thermal treatment at 200 °C. deposited thin films of Cu by e-beam evaporation at room temperature[425] followed by thermal oxidation at different temperatures in air. We consider that extra trap states would be formed by slight nonstoichiometry of Cu2O or induced by the device fabrication process.41 eV. a) Output characteristics (ID–VD). The inset shows the structure of the bottom gate TFT (adapted from [431]).30 to 15.com Figure 36. KGaA. Transfer characteristic ID–VG of Cu2O channel TFT at VD = −6 V (adapted from [420]).34 eV and the films have an average transmittance around 85%.[451] presented p-type TFTs based on CuO and Cu2O with improved properties and in particular a mobility and on/off ratio of 4. the p-type films present Eop ≈ 2. for a typical Cu2O TFT produced at room temperature and annealed in air at 200 °C.18 V dec−1 (Figure 38). concerning the technique. b) Transfer characteristics (|ID–VG|) at VD = −5 V (left axis) and μFE as a function of VG (right axis).0 V as indicated in Figure 36. Figueiredo et al.5 cm2 V−1 s−1. Table 3 summarizes the results achieved on p-type oxide TFTs as reported in the literature. Cu2O is a promising channel material for p-type oxide TFTs in the future. Bottom gate p-type TFTs with Cu2O channel layer present a μFE ≈ 1.” Besides the physical techniques mentioned in the description above I would like to emphasize that.65 to 18. 24. 2966 wileyonlinelibrary.. an on/off modulation ratio of 2 × 102 and a VT of −12.3 cm2 V−1 s−1 and 3 × 106 respectively. It is expected that further improvements on the electrical properties of the Cu2O TFTs can be obtained if the device structure and processing conditions are optimized. between 400 and 2000 nm for a thickness of 40 nm.2 × 10−3 cm2 V−1 s−1. The improved TFT mobility results from the decreased scattering of both the ionized defects and the grain boundary for Cu2O channel films. where considerable material development in needed before high performance devices can be realized. low cost p-type TFTs based on Cu2O can be produced. 2012.MaterialsViews. Thus.

MaterialsViews. The gate voltage.[458.6 nm to 18.2 nm (Figure 40). Transfer characteristics of p-channel Cu2O TFTs with W/L = 500/20 μm. VG varied from 0 to 40 V in steps of 10 V and b) the source-to-drain current. ID as a function of gate voltage. The inner core Cu wire and outer shell Cu2O film were used for the gate and channel respectively. SnO2 (and impurity doped SnO2) is a typical functional material with multiple applications including transparent conducting oxides. 2945–2986 © 2012 WILEY-VCH Verlag GmbH & Co. The poor electrical properties obtained for these TFTs are related to the several micro-structural defects that occur during oxidation. Channel layer CuxO +)PLD–Pulsed Technique Tdep/Tpost [ °C] Substrate . a) Drain current-drain voltage ID-VD characteristics of a thinfilm transistor based on an active layer of the postannealed CuO at 300 °C. SnO2 has a tetragonal structure and the unit cell contains two tin and four oxygen atoms.[450] 2010 4 rf sputtering RT/200 Si-SiO2 0. while each oxygen atom is surrounded by three tin atoms at the corners of an equilateral triangle. Each tin atom is at the centre of six oxygen atoms placed approximately at the corners of a regular octahedron.5 × 106 Zou et al. ∗)ATO . KGaA.Dielectric μ [cm2 V−1 s−1] On/off Reference Year PLD+ 700 MgO–Al2Ox 0.[456] This was con- firmed by atomic force microscopy (AFM) for an oxidized film and a Cu2O film grown by rf magnetron sputtering.com 2967 .455] The films with dominating Cu2O phase show p-type conductivity. Tin Monoxide Tin oxides are known to be wide band gap oxide semiconductors and are present into two well-known forms: tin monoxide SnO and tin dioxide SnO2. 2012. 24. Figure 37. The Cu ions migrate from Cu toward oxygen/Cu2O interface with the formation of a porous layer.com REVIEW Figure 38.[454.459] low emission windows coatings[460] and solid state gas sensing material.HfON 4. This particular cylindrical layout of the device can play the role of a fibber of the textile and the transistor therefore can serve as the fundamental building block for future e-textile.[453] 2011 Laser Deposition. and a Schottky barrier at Cu/Cu2O was used for gate diode in the metal semiconductor field effect transistor.[461] In contrast.superlattice of Al2O3 and TiO2. found that the cubic Cu phase of the as deposited films changes into single cubic Cu2O phase for annealing temperatures below 300 °C and changes to monoclinic CuO phase at higher temperatures. Mater.de www.[420.[457] where a Cu wire is used for making a Cu2O-Cu field effect transistor as it is indicated in Figure 41. the physical properties of SnO have not been well explored. SnO Table 3.advmat.3 3 × 106 Zou et al. VG was swept from −3 to 3 V at VD = 3 V (adapted from [451]).2.7.449] 2008 Sung et al.4 10 PLD 500 Si/SiO2 . Based on these results a p-type TFT was produced and the preliminary results are presented in Figure 39. where the surface roughness increases from 4.[431. VG at a fixed drain voltage of −10 V measured in air (adapted from [450]). 4. State of the art concerning oxide p-type TFTs based on Cu oxide for the last 3 years.[451] 2010 rf sputtering RT/200 Glass-ATO∗ 1.2 × 10−3 2 × 102 Fortunato et al.452] 2010 PLD 500 Si/SiO2–HfO2 2. which is in accordance with previous results.www. Adv.7 1. Another example using thermal oxidation of copper was presented by Han et al. Weinheim wileyonlinelibrary.26 6 Matsuzaki et al.

b) p-type TFT with Cu2O channel layer oxidized in air at 200 °C. Figure 39.[462. Schematic of Cu2O transistor on Cu wire. Weinheim Adv. 2012. which may act as donors or acceptors. a) Dependence of the resistivity of CuxO films as a function of oxidation temperature.[467] NiO[468.[471] that the p-type conductivity of SnO mainly originates from Sn vacancies. SnO2 is an intrinsic n-type semiconductor and the electrical conduction results from the existence of defects.advmat.MaterialsViews. orbital of O 2p and Sn 5s.469] and Cu2O. in a layered crystal structure.[464] catalysts for several acids[465] and precursor for the production of SnO2. 2968 wileyonlinelibrary. TFTs based on p-type SnOx are expected to fulfill these requirements due to the particular nature of band structure. due to its technological applications SnO have been used in a variety of applications like: anode materials for lithium rechargeable batteries.www.de REVIEW www. Unit cell of the crystal structure of SnO2 and SnO. without using a high processes temperature. In the case of SnO the top of the valence band consist of hybridized Figure 40. Source and drain pads are made by Pt by thermal evaporation.463] coatings. Inner core Cu wire and outer shell Cu2O film are used for the gate and channel. Surface roughness measured by AFM for a) a Cu2O thin film grown by rf magnetron sputtering and b) a Cu2O obtained by thermal oxidation of a Cu thin film. Contributions from Sn 5s states to valence band maxima (VBM) could offer appreciable hole mobility in this material. 24. Sn(II). respectively.[466] Recently. These defects are generally due to oxygen vacancies or interstitial tin atoms and are responsible for making electrons available at the conduction band. The comparison between the band structure of SnO2 and SnO is presented in Figure 43. KGaA. The unit cells of SnO2 and SnO are shown in Figure 42. particular attention because of the difficulty in obtaining stable and high quality p-type semiconductors based on ZnO. Mater. 2945–2986 . and the source and drain interconnection is made by cross-woven Cu wire.[470] It was demonstrated by Togo et al.com Figure 41. SnO has been received a Figure 42.com © 2012 WILEY-VCH Verlag GmbH & Co. adapted from [457]. In the past decades. has a specific electronic structure associated with the presence of divalent tin.

4 cm2 V−1 s−1 at room temperature. The as deposited film showed as amorphous phase.011 cm2 V−1 s−1. Figure 43. Top-gate TFTs. taxially on (001) yttria-stabilized zirconia at a substrate temperaThe threshold voltage can be tuned using different post depoture of 575 °C by pulsed laser deposition. deposited by reactive thermal evaporation at room temperature. KGaA. In the same year Liang et al. © 2012 WILEY-VCH Verlag GmbH & Co.MaterialsViews.3 cm2 V−1 s−1.de www.4 V and subthreshold swing of 2 V dec−1 (Figure 45). achieving an on/off ratio of 102 and a field effect mobility of 4 × 10−5 cm2 V−1 s−1. prising two SnO2 TFTs annealed at different temperatures was using the epitaxial SnO channels. and Dhanajay et al. The TFTs operate in the depleinverter composed with a p-SnO2 and a n-In2O3 TFTs with an tion mode. Mater. Adv. followed by a post annealing in air at 100 °C. In the case of SnO the The TFTs annealed at 100 °C present an on/off ratio of 103. The films were grown epiwhich is very high. 24. The TFTs performances are moderate. a) Output characteristics and b) field effect mobility in the linear region (μin) as a function of VG (adapted from [472]). exhibited field-effect mobilities constructed.[472] using SnO as channel layer. They used a bottom gate structure with SiO2 thermally grown on Si wafer as dielectric layer and by tuning the post deposition temperature it is possible to control the electrical performance of the TFTs. Weinheim wileyonlinelibrary. 2945–2986 REVIEW In the same year two more papers were reported by Ou[473] et al. a threshold voltage of 30. Portugal and China have been published. Comparison between the band structure of SnO2 and SnO. and a polycrystalline tin monoxide was obtained by post annealing at 310 °C for 1 h in argon environment. Drain current as a function of drain voltage at various gate voltages for the top-contact SnO2 TFTs (adapted from[473]). specially the threshold voltage. on/off current ratios of 102 and a threshold the voltage transfer curve and it was found to be around 2.advmat.[476] reported p-type TFTs using amorphous SnO thin films deposited by electron beam Figure 45. In Figure 44 we present the output and the The same authors have also reported a hybrid complementary transfer characteristics of this TFT.com Figure 44. The obtained gain was calculated by differentiating of 1. The films exhibit a Hall sition temperature annealing and an inverter structure commobility of 2. 2012. The large off current associated to the depletion mode output gain of 11. In 2010 several reports on p-type SnO TFTs from Japan.www. They have fabricated bottom gate. Korea.com 2969 .8 V.8.1 × 1011 cm−2 et al.[475] reported p-type TFTs by using a tin monoxide film deposited by vacuum thermal evaporation. The interface trap density at the semiconductor/ The first p-type oxide based TFT was made in 2008 by Ogo dielectric interface obtained for this TFT was 8. field effect mobility of top of the valence band consist of hybridized orbital of O 2p and Sn 5s.[474] operation is attributed to the large hole density (>1017 cm−3). bottom contact structure TFTs on heavily doped silicon wafers with a thermally grown silicon oxide layer. 0.[474] SnO2 was used for the channel semiconductor. explaining the low value of channel mobility. voltage of 4. Lee et al.

Another p-type SnO TFT was reported in the same year by Yabuta et al.5 V and 0.[477] Polycrystalline SnO thin films was used for the channel semiconductor by conventional rf sputtering with a subsequent annealing treatment. b) TFT SEM crosssection where it is clearly shown all the constituent layers. Fortunato et al. 2970 wileyonlinelibrary. a) Output characteristics (ID-VD) and. reported SnOx TFTs deposited on glass substrate by rf magnetron sputtering at room temperature. These films exhibit © 2012 WILEY-VCH Verlag GmbH & Co.24 cm2 V−1 s−1. Weinheim Adv. after annealing at 200 °C. for a SnOx p-type paper transistor produced at room temperature and annealed in air at 160 °C.com evaporation at room temperature followed by a rapid thermal annealing treatment in an argon atmosphere. Bottom gate TFTs were fabricated using as dielectric layer a thin film of SiNx formed by plasma enhanced chemical vapour deposition on n+-Si.87 cm2 V−1 s−1 respectively (Figure 46).www. The authors have also demonstrated in this report that oxidation of the SnO films decrease hole density and produce n-type SnO2.MaterialsViews. b) Transfer characteristics (|ID–VG|). 24. 2012. Figure 47.de REVIEW www. The SnO films present a polycrystalline structure composed with a mixture of tetragonal β–Sn and α–SnO phases. The TFTs exhibit an on/off ratio and field effect mobility of 102 and 0. respectively. −3. a) Typical output characteristic of SnO p-channel TFT (gate voltage is varied from 0 to −50 V in −10 V steps). The subthreshold swing.com Figure 46.advmat. Bottom gate TFTs using 100 nm SnO thick as channel layer have been deposited on top of SiO2/Si substrates. The characteristics of drain-source current (ID) vs drain-source (VD) for the TFT with the SnO channel annealed at 400 °C (adapted from [476]). 2945–2986 . 2 × 102. on/off ratio and field effect mobility are 11 V dec−1. Mater. KGaA. Figure 48. followed by a rapid annealing at 200 °C.

usable as head-up displays (HUDs) in automotive industry. acting as gate electrode. were obtained by integration with chipLED frontplane technology (Figure 50). Weinheim wileyonlinelibrary. KGaA. mainly related to the fact that cellulose fibbers have a typically open structure (macroporosity). and the inverter shows a maximum voltage gain of 2. while the gate dielectric was a stacked multilayer of Al2O3 and TiO2 (ATO) with 220 nm thick deposited on a glass coated with a 200 nm thick Indium Tin Oxide (ITO) film. Mater. Fortunato et al.480] where the paper sheet works simultaneously as the substrate and the dielectric layer. At CENIMAT|I3N.[483] report the first ambipolar oxidebased TFT using an SnO channel semiconductor. respectively.8 eV and average transmittance ≈85% (400 to 2000 nm).[481.482]) and d) with a higher magnification to see the detail of the good step coverage of the oxide semiconductor over the cellulose fibbers.8” LCDs were fabricated on glass. More recently by controlling the SnO oxidation state it was possible to obtain TFTs with improved performance:[478] saturation mobility of 4. optical band gap of 2. c) scanning electron microscopy cross section image of the gate electrode (IZO[481.advmat. The TFTs present a field-effect mobility above 1 cm2 V−1 s−1 and an on/off modulation ratio of 103.6 cm2 V−1 s−1 and on/off ratio above 7 × 104.5. which limits the off current. 24. 2945–2986 REVIEW a hole carrier concentration in the range of ≈1016–1018 cm−3. with each pixel having an © 2012 WILEY-VCH Verlag GmbH & Co. Soc. We can also observe the good step coverage of the IZO film along the cellulose fibbers. b) architecture of the paper transistor. More details in section 5. Figure 49a and b show a photograph and a schematic of the paper transistor. The PM backplane was produced using room temperature sputtered IZO. For the source-drain electrodes Ti/Au (8/50 nm thick) films were e-beam evaporated. 2012. The main difference is related to the on/off Given the close relation between TFTs and displays. based on a new concept “Paper Electronics .www. consisting of an array of 128 × 128 pixels. In order to prove the feasibility of producing p-type oxide TFTs at room or/and low temperature we have produced a p-type paper-transistor using as dielectric layer a flexible cellulose sheet of conventional paper.479. Bottom-gate TFTs were fabricated using 30 nm thick α-SnO films as semiconductors. it is not strange that the most significant application of oxide TFTs is on displays.com 2971 . Adv. Saturation mobilities of 0. Transparent alphanumeric displays with 7 segments. a) shows an optical photograph of a p-type paper transistor. This result is the first demonstration of a complementary-like circuit using a single oxide semiconductor channel and provides an important step toward practical oxide electronics.3. Information Display (SID) and International Meeting on Information Display (IMID) exhibitions have been the stage for the presentation of several prototypes employing oxide TFT technology. Emerging Applications 5. under the framework of Multiflexioxides FP6 project).de www. The obtained electronic performances of the p-type papertransistor do not differ significantly when the cellulose fibber is used as dielectric. oxides have been used both for passive matrix (PM) and active matrix (AM) backplanes (the integration of the PM and AM backplanes presented here with frontplane technologies was done at Centro Ricerche Fiat Italy and Hewlett Packard Ireland. Figures 48a and b show the ID–VD and |ID–VG| characteristics of a paper p-type SnO transistor after annealing in air at 160 °C. Hall mobility around 4.1. in 2008. electrical resistivity between 101–102 Ω cm.8 cm2 V−1 s−1. In 2011 Nomura et al. Table 4 lists the p-type TFTs with SnO channel layer. The devices were annealed at 250 °C in air. respectively. AM backplanes for 2. which are the highest values achieved so far in any p-channel oxide TFT (Figure 47). one order of magnitude lower. and its application to a complementary-like inverter combining two ambipolar SnO TFTs.com ratio. respectively. mostly LCDs and OLEDs. on 5 × 3 cm glass and polymeric substrates.MaterialsViews.484] patterned using conventional photolithographic processes.Paper-e” proposed by E. The SnO films have been deposited by pulsed laser deposition at room temperature and bottom gate and top contact structures were fabricated on thermally oxidised SiO2/n+Si substrates. From 2007. In Figures 49c and d we can see a scanning electron microscopy cross-section image of the gate electrode (IZO) deposited on one side of the cellulose paper.[2.8 and 5 × 10−4 cm2 V−1 s−1 are obtained for the p-channel and n-channel modes. Displays with Oxide-Based Backplanes Figure 49. 5.

GIZO channel layer.[474] 2008 Evaporation RT/310 Si–SiO2 10−5 ∼102 Lee et al. the final backplanes were annealed at 150 °C.[483] 2011 7× 104 ∼103 [477] +) PLD–Pulsed Laser Deposition. The stage is now set for a variety of displays using oxide TFT technology. Backplane production consisted on a standard 5 mask process. [473] 2008 rf sputtering RT/400 Si–SiNx 0.2. In most of the reported displays employing oxide TFTs. Finally. with a single TFT per pixel.com Table 4. are the works from Samsung SDI. ∗)ATO . with a 3. with a 4.3 ∼102 Ogo et al.7 × 10−3 ∼102 Dhananjay et al. 2945–2986 .[279. resulting in a 90% decrease in power consumption when compared with conventional LCDs. such as the 4.[489] The first demonstration with OLEDs is attributed to Samsung Electronics.. Figure 50. 2010 Evaporation RT/400 Si–SiO2 0.[478] 2011 PLD+ RT/250 Si–SiO2 0. Still. approximate area of 350 × 350 μm (Figure 51a and b). These displays exhibit a 1680 × 1050 resolution. evidences of some shorted gates were observed and attributed to the lack of reliability and reproducibility of the TSiO dielectric.6 Fortunato et al.5” 176 × 220 resolution OLED display on a 0.[452] 2010 rf sputtering RT/200 Glass–ATO∗ 4.[486] from Toppan Printing Inc. being the spin-coated IZO TFTs processed at a maximum temperature of 350 °C. TSiO dielectric and SU-8 passivation.[487] With atomic layer deposited ZnO TFTs.www. Instead of a backlight. oxide TFTs are of great interest. respectively). as pointed out in the introduction. 2012.1” LCD display. Mater.485] from LG Electronics Inc. 24. such as the 70” ultra-definition (UD) LCD 3DTV with a high scanning frequency (240 Hz) demonstrated by Samsung in 2010.24 ∼102 Yabuta et al. employing oxide semiconductors but not necessarily resulting in transparent displays.03O TFTs driving a 4. The AM backplanes were then successfully integrated with reflective LCD frontplanes (Figure 51c). 2972 wileyonlinelibrary.[303] For demonstration purposes. 5. the channel layer is produced by sputtering.97Zr0. with small area flexible OLEDs and large area rigid high-end LCD and OLED displays being probably the main targets for commercial products in the near future. with 4” 320 × 240 resolution electrophoretic display on polyethylene naphthalate (PEN) plastic substrate (Figure 52a).[490] Other works followed. a contrast ratio of 500:1 and a transparency of 15%. having a transmittance higher than 20%. KGaA. with increased panel sizes and resolution. Several companies are currently working on oxide TFTs for demonstrating flexible and/or transparent displays. ambient light is used.0 × 3 Ou et al.5” 220 × 176 resolution OLED transparent display on a glass substrate.75 Nomura et al.2 ∼103 Fortunato et al. But despite the early stage of research on solution-processed oxide TFTs. Their high mobility and large area uniformity can yield high-end displays.com also reported a 2. State of the art concerning oxide p-type TFTs. reported sol-gel Zn0. with a 2. Channel layer SnOx Technique Tdep/Tpost [ °C] Substrate-Dielectric μ [cm2 V−1 s−1] On/off Reference Year PLD+ 575/200 YSZ–Al2Ox 1. mass-production of the first transparent 22” LCD panels was already announced by Samsung in 2011.advmat..87 ∼102 Liang et al. Inverters and Ring Oscillators For any semiconductor technology.1 × 10 Evaporation RT/100 Si–SiO2 4. the architecture was the simplest possible. using either Ti/Au or IZO source-drain and gate electrodes (for opaque and transparent AMs. In fact. LCD and OLED displays were already fabricated using this lower cost processing technology.2” monochromatic display with 128 × 160 resolution (Figure 52b). should not be far from entering in our daily life. The numerous prototypes already shown by most of the greatest display companies is certainly an indication that products within the “transparent electronics” concept or. Chiang et al. Park et al.[488] But even when transparency of the overall display is not persuaded. Weinheim Adv.MaterialsViews.de REVIEW www.superlattice of Al2O3 and TiO2.[476] 2010 rf sputtering RT/200 Glass–ATO∗ 1./Oregon State University.[475] 2010 4.1” 176 × 220 resolution full-colour OLED display. Transparent PM chipLED display using IZO electrodes.[472] 2008 −2 ∼10 Evaporation RT/100 Si–SiO2 1. Some examples.1” LCD display with 320 × 240 resolution driven by spin-coated GIZO TFTs reported by Taiwan TFT LCD Association (TTLA)/Inpria Corp. In 2008. the fabrication of inverters and ring oscillators (ROs) is a basic requirement for producing © 2012 WILEY-VCH Verlag GmbH & Co. all driven by GIZO TFTs.1 mm thick stainless steel plate.

used here to facilitate device fabrication. which present a peak gain magnitude (dVOUT/dVIN) of ≈1. The evaluation of the performance of these simple circuits can provide a valuable tool to define the range of applications of a TFT technology. 2012. KGaA. Mater. 24. b) microscopy image of pixel area (350 × 350 μm).[225] to report in 2007 five-stage ROs based on GIZO TFTs with considerably improved performance. When VIN is high. These values are significantly affected by the large parasitic capacitance arising due to the large source/ gate and drain/gate overlap. Prototypes of displays with oxide TFT backplanes: a) flexible electrophoretic display.[491] The authors reported sputtered IGO TFT based inverters and five-stage ROs on glass.com 2973 .[303] a complete range of logic circuits. When the input voltage (VIN) is low the control transistor is in the off-state and Adv. 2945–2986 the load transistor pulls the output (VOUT) to a “high” level. A simple inverter is composed by two transistors (control and load). current flows through the control transistor. AM backplane with GIZO TFTs produced at CENIMAT for a LCD display: a) photograph of a transparent AM on glass.5 kHz and a propagation delay of 11 μs/stage are achieved for the RO. A RO consists of any odd number of inverters connected in series. For instance. Weinheim wileyonlinelibrary. such as an oscillation frequency of 410 kHz and a propagation delay of © 2012 WILEY-VCH Verlag GmbH & Co. A maximum oscillation frequency of 9.[487] b) OLED display driven by solution-processed IZO TFTs.advmat. c) prototype after integration with LCD front plane. Finer design rules and improved TFT performance allowed Ofuji et al.www. causing the output to be at a “low” level.[490] Figure 51.[225] To the authors’ knowledge.5.de www. the propagation delay of a RO is a widely accepted benchmark regarding how fast a TFT can operate.MaterialsViews. the first transparent circuits with oxide semiconductors were reported in 2006 by Presley et al.com REVIEW Figure 52. Figure 53a shows the voltage transfer characteristic (VTC) of the inverters.

Very low operation voltage is achieved with MESFET technology. and GIZO was already used to fabricate MESFETs with excellent electrical properties (S = 69 mV dec−1 and μFE = 15 cm2 V−1 s−1) with a maximum temperature of 150 °C. eleven-stage ROs were also fabricated on flexible substrates by Mativenga et al.www. Oxide MESFETs seem to be quite promising for fast and low power consumption transparent integrated circuits. Electrical properties of initial oxide TFT based circuits: a) VTC for a transparent inverter using IGO TFTs (adapted from [491]). Sang-Hee Ko Park and Dr. 2945–2986 . but the main focus of research is on exploring the great electrical properties and low processing temperatures of oxide TFTs that allow low cost and high performance circuit fabrication. The authors report that the propagation delay achieved in this work is half and almost one third of the ones achieved using a-Si:H and organic TFTs. In 2011.[492] ALD deposited ZnO TFTs processed at 200 °C were used to fabricate a seven-stage RO that operates at 2. an estimated lifetime of more than 10 years is announced for the gate driver. with the inverters showing high gain values up to 197 at 3 V.advmat. corresponding to a propagation delay of only 31 ns/stage.[493] in 2010.2 make use of only n-type oxide TFTs.[220] requiring maximum processing temperatures of 220 °C. using AgxO Schottky diodes as level shifters. b) Propagation delay in a RO based on GIZO TFTs (adapted from [225]). 0. Based on these initial results.. 5.com Figure 54.3 MHz.8 kHz with a propagation delay of 0. Figure 53. In 2008 the fastest oxide circuits on glass were reported by Sun et al. ZnO metal-semiconductor field-effect transistors (MESFETs) were used to fabricate integrated inverters. Mater.de REVIEW www. 24. as reported by Frenzel et al. Oxide CMOS All the circuit applications reported in 5. Based on gate bias stress measurements. However.3. For this work.MaterialsViews. respectively. Initial results on transparent CMOS inverters were already obtained at CENIMAT|I3N (this work was done in collaboration with Dr. both n. i. The additional diode as second input allows implementing the logic NOR-function in the circuits. CMOS technology offers great advantages over NMOS. These operate at a frequency of 94.com pulsed laser deposition (PLD) on sapphire substrates at 675 °C. especially regarding power dissipation and higher density of logic functions on a chip. KGaA. and b) output characteristics of the fabricated ring oscillator on plastic substrates (adapted from [220]).48 μs/stage.and p-type oxide TFTs are required if the fabrication of complementary metal oxide semiconductor (CMOS) circuits is envisaged. are based on NMOS logic. which is highly promising for flexible display applications (Figure 54). Weinheim Adv. 2012. ZnO was grown by 2974 wileyonlinelibrary.[494] but GIZO MESFET inverters were not yet demonstrated. even on flexible substrates. a similar scenario to the one depicted for displays seems to arise regarding oxide-based circuits: transparency can be an added-value property for specific applications. Chi-Sun © 2012 WILEY-VCH Verlag GmbH & Co.e. Besides TFTs.. a) Optical image of an eleven-stage RO. The authors also reported a flexible two-clock shift register (gate driver) with AC operation.24 μs/stage (Figure 53b).

caused by the low μFE of the n-type SnO TFTs.5 cm glass substrate with several transparent which allows to fine-tune the oxygen content of the SnO film CMOS inverters. being the final devices these results already prove that transparent CMOS circuit annealed at 250 °C. by using the sputtered GIZO TFTs being produced by reactive evaporation. A more detailed knowlused to achieve the ambipolar behaviour. even for low VIN the Following the previous paper. Two identical ambipolar TFTs. the same authors for the fi rst time fully oxide based CMOS CMOS inverter. Mater. inverters were annealed at 200 °C for 30 min in air. fabricated with a maximum temperature of 750 °C. being a gain magnitude above CMOS inverter based on this production method was presented 1 is required to sustain signal propagation in integrated circuits (Figure 58a).[495] reported in 2008 a hybrid CMOS inverter on Si substrates based on ambipolar TFTs comprising a stack of In2O3 and pentacene as the channel layer. In 2010.advmat. such as ROs. but no actual CMOS devices were fabricated. Yabuta et al. Figure 55 by using a SiOx capping layer on top of sputtered SnO films.[483] in 2011. After production. the initial CMOS inverters were based on hybrid the SnO TFTs. KGaA. The CMOS inverter operates with a peak design is achievable using transparent oxide semiconductors gain of ≈2. nium-based dielectric and IZO electrodes.www. the CMOS n-type SnO2 TFTs and p-type SnO TFTs in the same substrate. using inverters. this being the first edge regarding how to control the subgap density of states in demonstration of a CMOS circuit using a single oxide semiconp-type oxide semiconductors will certainly allow to improve ductor. VTC and gain for a CMOS inverter with p-type SnOx and n-type In2O3 TFTs (adapted from [474]). Korea). by combining p-type SnOx and n-type In2O3 TFTs. The SnO films were deposited by PLD at room temperadevice and circuit performance. comprising n-type oxide TFTs and p-type organic TFTs. A conceptual design of a Figure 56. 2945–2986 REVIEW solutions. [474] reported Figure 55. but even at this initial stage ture on thermally oxidized Si substrates.7.5 (Figure 58b).[477] reported the formation of both a passivation layer was not used. VTC and gain for a transparent CMOS inverter with n-type GIZO and p-type SnO TFTs fabricated at CENIMAT/I3N. Weinheim wileyonlinelibrary. The low gain when compared with with maximum (post-)processing temperatures of 200 °C.[495] only SnO was that for larger VIN we have VOUT > 0 V. were used to build a CMOS inverter that exhibits a peak gain of 9. © 2012 WILEY-VCH Verlag GmbH & Co. something crucial to The VTC for a transparent CMOS inverter is presented in obtain p-type behaviour in SnO. The fact that the p-type inverter by Nomura et al. At this initial stage.com Figure 56.de www. rather TFT cannot be entirely switched off also contributes to the fact than using organic and oxide semiconductors.[477] the ambipolar effect p-type TFT has some non-negligible current flowing between observed in SnO films was successfully applied to a CMOS source and drain. being the channel layers Hwang from ETRI. The ambipolar behaviour critically depends on the thickness and morphology of the In2O3 layer.MaterialsViews. Given that p-type oxide TFTs are still at the initial stage gains 5–20) is justified by the large off-current and imbalance of of research. shows a 2.5 × 2. during an annealing process (300 °C). Adv. 2012. 24.com 2975 . The peak gain is ≈1. inverters. The inverter operates at and SnO TFTs presented in section 4. causing VOUT < VDD. b) optical microscopy image of an oxide Still in 2008. Figure 57. other ambipolar transistors containing channel layer of different Reports on oxide semiconductor based CMOS are fairly materials such as microcrystalline silicon and organics (voltage recent. However. But in this case. Dhanajay et al. with multilayer haffairly high voltages and exhibits a peak gain of ≈11 (Figure 57). a) Transparent CMOS inverters on glass.

Conclusions Figure 59. Weinheim Adv. Schematic of a conceptual CMOS inverter using n-type SnO2 and p-type SnO TFTs to the architecture of circuits naturally do not (adapted from [477]).2 which is an encouraging value for the future prospects of paper electronics (Figure 60). tags. Notwithstanding the strong advantages of oxide based TFTs. 2012. 24.and n-channel FETs exhibit electron and hole mobilities greater than 21 cm2 V−1 s−1 is highly promising. this means that the complexity of thus creating an opportunity for light weight. AU Optronics. Martins et al. 2945–2986 . thus fueling the intended microelectronics revolution in the so-called technologies of information and communication.com There has been tremendous progress in oxide based TFTs performance during the last 7 years.de REVIEW www. This is is reduced. b) Image of the real paper-CMOS and c) SEM cross section of the n-type paper TFT.[496] succeed to perform a paper-CMOS tomorrow. Samsung Mobile Display.MaterialsViews. we have reached the point where several companies such as Samsung Electronics. Indeed. it is not surelectrode. ture. Mater. batteries[499.advmat. the type of TFT structure/ architecture including passivation issues will play an important role in stability questions. Sharp. sensors and memories packed integrated circuits. dc inverter with n. CMOS on and with paper looks good. leading Figure 58. b) VTC for an ambipolar SnO CMOS inverter (adapted from [483]).com as computer memory chips. GIZO deposited by sputtering remains the best performer because of is amorphous structure and excellent electrical properties. All the layers that constitute the CMOS device were prising given the advance from a rigid substrate to paper. As the paper itself can act as here does not inhibit the implementation of CMOS on paper. The challenge of paper electronics is to be able expected to create applications in disposable and recyclable electo produce low power consumption devices to allow densely tronics that range from smart labels. and analogue (linear) circuits. Both TFTs The use of paper dielectrics and layering of p. and LG Display have already demonstrated many prototypes of AMLCD and AMOLED panels that integrate oxide TFT backplanes and some of them have announced the mass production of flat panel displays using this new technology. microprocessors.500] and integrated systems. both substrate and dielectric.[497. More fundamental research includes a better understanding of the density of states and defect levels in ionic bonding © 2012 WILEY-VCH Verlag GmbH & Co. Toppan.498] The paper-CMOS gain was 4. 2976 wileyonlinelibrary. KGaA. respectively. research on stability is still an open question. a) Cross sectional schematic of fabrication sequence of the paper-CMOS showing all layers that constitute the final device and how they are interconnect as well as image of the real device. contributing today for the shaping of electronics of Recently.and p-type oxide TFTs using GIZO and Although in this first attempt of fabricating a CMOS device non-stoichiometric SnOx (x < 2) respectively. low cost and fully transferring a stand-alone electronic circuit onto a paper page recyclable complementary circuits–green electronics. as illustrated by the inverter example described. 6. among others. for a plethora of applications such to TFT driven electro-chromic paper displays. Besides the best dielectric material as well as dielectric/semiconductor combination. digital logic circuits. with an IZO gate with and on paper a high leakage current is observed. draw power and can easily be implemented as static circuits without the need for clocking circuitry. At present.www. The process sequence is depicted in Figure 59. Additionprocessed by reactive magnetron sputtering at room temperaally the conventional FET gate dielectric is now replaced by paper. Concerning n-type oxide semiconductors. The performance of the circuit presented and 1 cm2 V−1 s−1.

PTDC/EEA-ELC/099490/2008 (From Electronic Paper to Paper Electronic–Paper_@). Status Solidi-Rapid Res. POCI/CTM/55942/2004 (Transparent thin film transistors based on zinc oxide to be used in flexible displays). Since 2009 substantial improvements have taken place in solution-processed oxide semiconductors. directly related to this topic.6 cm2 V−1 s−1. 2012. The Microelectronic and Optoelectronic Materials Team (December 2011). oxide semiconductor based devices is today a new technology that not only may replace the conventional silicon technology in some applications but also opens new areas of applications.com Figure 60. flexible and paper substrates have already been presented. exceeding 4. and the obtained mobilities are competing with the ones obtained trough physical techniques. PTDC/ CTM/103465/2008 (Integrated Memory Paper using oxide based Channel thin film Transistors). which will lead to a more detailed understanding on the mechanisms that govern device stability. 24. the oxides reported in the literature are mostly limited to n-type device applications. PTDC/CTM/73943/2006 (Multifunctional Oxides: a Novel Approach for Low temperature Integration of oxide Semiconductors as Active and passive thin films in the future generation of electronic systems). The best results obtained are for Cu2O and SnO with mobilities and on/off ratios of the order of 4. Solution-based processes and novel applications will also be seriously considered in future research. probably faster than you can imagine or realize! The successful development of these new materials will require increased multidisciplinary partnerships among physicists. This work was partially funded by the Portuguese Science Foundation (FCT-MCTES) through Multiannual contract with I3N and with projects related to oxide semiconductors like: POCI/CTM/55945/2004 (Development of transparent and conductive oxide semiconductors p-type: from synthesis to devices). 7 × 104. Wager. based semiconductors. QREN No. Mater. ring oscillators and CMOS inverters. 2012 [1] J. without them this work would be impossible. KGaA. 48. that are related to multifunctional oxide based electronic materials and printable organic-inorganic transparent semiconductor devices. PTDC/ EEA-ELC/64975/2006 (High mobility transparent amorphous oxide semiconductors thin film transistors for active matrix displays). Osterbacka. Phys. Weinheim wileyonlinelibrary. Adv. specially the group of Microelectronic and Optoelectronic Materials of CENIMAT|I3N and CEMOP. they are not restricted to TFTs to be used in AMLCDs or AMOLEDs display applications. 5. This can be achieved by developing novel low-temperature chemistries and/or processes. the first 100% running project on Transparent Electronics in Europe. 42. 2011. Inverters. respectively. chemists. either on glass.www. Taking into account the excellent properties presented by oxide semiconductors. E. nevertheless huge achievements have been made and TFT mobilities around 10 cm2 V−1 s−1 have been obtained at temperatures as low as 200 °C. Concerning the work developed so far on this topic. respectively.2006-S079-03.advmat.de www. Hoffman. We would like also to thank the fruitful collaborations done directly with companies and institutes like SAIT-SAMSUNG project “STABOXI”. The accomplishment of a low temperature process and reasonable device stability/reliability will be critical to the success of this new but very promising technology. 1935. related to the passivation of a-GIZO TFTs. Mater. for the project related to oxides for glazing. since there is a lack of p-type oxide semiconductors. and engineers. biochemists. as well as to the support given from European Commission and the partners involved under the following projects: Multiflexioxides (NMP3-CT-2006-032231). 23. Although the performance achieved with oxide transistors processed at low temperature exceed far beyond the ones obtained with amorphous silicon and organic semiconductors. [3] D. The actual limitation of solution-based processes are the need to use higher temperatures. and more recently to ORAMA (NMP3-LA-2010-246334) and POINTS (NMP3-SL-2011-263042). currently two promising candidates for p-type oxide TFTs seem to exist: copper oxide and tin oxide based semiconductors. I. 3 × 106 and 4. R. Electronic and Telecommunications Research Institute of South Korea (ETRI) with the project IT R&D program of MKE . R. “Smart window with transparent electronic devices” and to Saint Gobain Recherche France. Voltage transfer characteristic of the paper CMOS under a VDD = 17 Volts (right scale) and the CMOS gain. 2012 Published online: May 10. Martins. F. Tobjork. From what was already proved. 332. Fortunato. REVIEW Acknowledgements Received: August 22. 3454 (New nanoxide composites for advanced fabrication of targets for passive and active Opto/Micro/Nano-electronics applications). IEEE Spectrum 2011. We finish by acknowledging those who made this review possible. Lett.MaterialsViews. 2945–2986 First of all we would like to thank to European Research Council trough the Advanced Grant (given to EF) under the project “INVISIBLE” (ERC2008-AdG 228144) Advanced Amorphous Multicomponent Oxides for Transparent Electronics. © 2012 WILEY-VCH Verlag GmbH & Co.com 2977 . PTDC/CTM/099124/2008 (Electrochromic thin film transistors for smart windows applications). [2] R. CMU-PT/SIA/0005/2009 (Self-organizing power management for photo-voltaic power plants) and ERA-NET/0005/2009 (Multifunctional zinc oxide-based nanostructures: from materials to a new generation of devices).3 cm2 V−1 s−1. 2011. Adv. Ferreira.

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