7 views

Uploaded by Sana Nazir

a brief description of logic gates

save

- A New Family of Optically controlled logic Gates using Naphthopyran Molecule
- Descr
- d4
- Network Theorem
- Tutorial 4
- EC_EI_EN_WESTIN_QUESTION_PAPER.doc
- SeqAnalysisDesignExamples
- Experiment3_kcl & Kvl
- rlc1-v1
- PSPICE Tutorial
- HC157
- logic
- Logic
- Adder & Subtractor
- 3-4s
- LM723 53946_DS.pdf
- 07_dft_2pp
- digital
- Counters
- Single State Transistor
- CZ80PIO
- Tut Timing Verilog
- Verilog Examples Useful for FPGA & ASIC Synthesis
- Leaving Class A
- 39sf020Adatasheet
- Flow Transmitters
- Competitive Exams_ Electronics MCQs (Practice Test 4 of 13)- Examrace
- Pyro Electronics
- TA2-2_Kao_paper
- System Perspective Cp Ravikumar
- 1 Concrete Testing and Sampling
- sow_road_construction_022610.docx
- 5 Method Statement for BRICK WORKS
- Form for Upgradation of Firms
- Machine Design
- Op Tim Ization
- ZEC Fire Fighting Brochure.pdf
- ZEC Fire Fighting Brochure
- Subhan
- Method Statement for Plastering
- Transformer Oil Density
- 079_088.pdf
- Opf Network 1
- 16-Hydraulic Turbines [Compatibility Mode].pdf
- Chart
- Chapter 4 (Combinational Logic
- analy(2)
- CV Format.doc
- NOTICE for Admission
- EDC LAB Darlington New (Rebuilt)
- Chapter 1 Digital Systems and Binary Numbers
- 232561026-University-of-Lahore-UOL-Entry-Test-Sample-Paper.pdf
- UP-GRADATION PEC FORM.pdf
- Reapear.doc
- Up-gradation Pec Form
- Sample Test Engineering
- Chapter 5 Synchronous Sequential Circuit
- 227348337-COMSATS-Entry-Test-Sample-Paper(1).pdf
- 40342833-How-to-Select-Perfect-Name.pdf

You are on page 1of 7

Binary Logic

Logic Gates

• Binary logic uses 2 possible values

• Logic Gates

• 1 and 0

• Yes and no

• True and False

**– Basic building blocks of the digital circuits
**

– Control flow of information

– Represent Logical Operations (Functions)

• Fundamental Gates

• AND, OR, NOT

• Logic functions modify input values

• Characteristics

– What is the minimum no. of input ?

•

•

•

•

**• 1 bit -> Pretty uninteresting
**

• 2 bits -> basic logic functions

**Operation of the gate (what it does)
**

Function/truth table

Timing diagram

Application example

5

AND Function

AND Gate

• Operation to check if two conditions are met.

**• Timing Diagram - a graph that accurately displays the relationship of two
**

or more waveforms with respect to each other on a time basis

• Two inputs

• Outputs ‘1’ if and only if both inputs are ‘1’

• Symbolized by a dot (.) or absence of the operator:

» X.Y, XY

• Truth table

• Needs to consider 2^2= 4 combinations

• Graphical Symbol

• AND Gate

Graphical representation of AND gate operation

7

OR Gate

AND Gate (Application)

**• Operation to check if at least one condition is met
**

• Two inputs

• Outputs ‘1’ if any one or both inputs are ‘1’

• Symbolized by a plus (+) sign: X + Y

**• Application example of AND gate
**

– Device (Stop-watch) enable/disable switch

• Truth Table

• Graphical Symbol

• OR Gate

**– When the input B is set to HIGH (enabled), the clock
**

signal is applied to the counter

8

9

1

31/10/2012 OR Gate (Application) OR Gate • OR gate application example • Timing diagram of the OR-Gate – Car door alarm system – When all the doors are closed. 0000 is applied to the input of the OR gate – When one or more doors are open. which activates the alarm 10 11 NOT Function NOT Gate • Complement Operation • Single input • Inverts value of input • Symbolized by prime or overbar: • Timing diagram of NOT-Gate • Truth Table • Graphic Symbol • NOT Gate • Little circle indicates inversion 12 13 NOT Gate NAND Gate • Contraction of NOT-AND • Standard logic symbol • NOT gate application example – 1’s complement F = A •B F = A •B • Output is LOW only when all inputs are HIGH • Bubble indicates ACTIVE LOW output • Output level is opposite to that of the AND gate 14 15 2 . the output of OR gate is 1.

• When all the fans are working. the input to the NAND gate is 111 and the output is 0 • If any one of the fan stops working. the output of the NAND gate becomes 1.31/10/2012 NAND Gate NAND Gate • The truth table for a two input NAND gate Input Middle Output Output A B E F 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 • Timing diagram of NAND gate 16 17 NAND Gate NAND Gate as Negative-OR • NAND gate application example • Device Failure Alarm System • The truth table for a two input NAND gate looks awfully similar to an OR gate with the inputs inverted. OR) – Universal NAND gate Bubble signifies ACTIVE LOW INPUT 20 21 3 . AND. which activates the alarm A 0 0 1 1 Input B 0 1 0 1 NAND Output F 1 1 1 0 Input A 1 1 0 0 B 1 0 1 0 OR Output F 1 1 1 0 18 NAND Gate as Negative-OR 19 NAND Gate as a Universal Gate • NAND gate can be used to perform all the fundamental gate operations (NOT.

31/10/2012 NAND as AND Gate NAND as NOT Gate • Using NAND gate to perform the AND gate operation • Remember NAND is NOT-AND. What if we inverse this one more level? NOT-(NOT-AND) = AND Join all the input pins of the NAND gate together Input A B 0 0 0 1 1 0 1 1 Output F 1 1 1 0 • Accomplished by applying a NOT operation (implemented through NAND gate) to the output of the NAND gate 22 NAND as OR Gate 23 NOR Gate • Contraction of NOT-OR • The standard logic symbol • Using NAND gate to perform the OR gate operation • Produces a LOW output when one or more of its input is HIGH • Bubble indicates ACTIVE LOW output • The output logic is opposite to that of the OR gate – Can we form NOR gate as well? 24 NOR Gate NOR Gate • Timing diagram of a NOR gate • Truth table for a two input NOR gate Input A B 0 0 0 1 1 0 1 1 25 Output F 1 0 0 0 26 27 4 .

AND. the output of corresponding sensor is set to 1. Switch Input A 0 0 1 1 – If the machine lid is open or the water in the tub is below certain level or the machine is overloaded (weight of water and clothes in the tub is above certain limit).31/10/2012 NOR Gate NOR Gate as Negative-AND • Application as Washing Machine Controller • The truth table for a two input NOR gate looks awfully similar to an AND gate with the inputs inverted. producing a 0 at the NOR gate output that switches the machine off B 0 1 0 1 NOR Output F 1 0 0 0 Input A 1 1 0 0 B 1 0 1 0 AND Output F 1 0 0 0 28 NOR Gate as Negative-AND 29 NOR Gate as a Universal Gate • NOR gate can be used to perform all the fundamental gate operations (NOT. OR) – Universal NOR gate Bubble signifies ACTIVE LOW INPUT 30 31 NOR as OR Gate NOR as NOT Gate • Using NOR gate to perform the OR gate operation • Remember NOR is NOT-OR. What if we inverse this one more level? NOT-(NOT-OR) = OR Join all the input pins of the NOR gate together Input A B 0 0 0 1 1 0 1 1 Output F 1 0 0 0 • Accomplished by applying a NOT operation (implemented through NOR gate) to the output of the NOR gate 32 33 5 .

C and D respectively generates 0 at the output of XOR gate 1. B. Name the gate? Name the following gate? • Name the following gate? – Can we form NAND gate as well? 34 35 XOR Gate XOR Gate • Exclusive OR (XOR for short) • The truth table for XOR Gate – Standard logic symbol Input – This gate has only two inputs – Logical expression F = A ⊕ B – The output is HIGH only when the two inputs are at opposite logic level Output A B F 0 0 0 0 1 1 1 0 1 1 1 0 36 37 XOR Gate XOR Gate • Application example of XOR gate – Detecting odd parity • Timing diagram of XOR gate – Applying 0011 at the input A.31/10/2012 Review NOR as AND Gate • • Using NOR gate to perform the AND gate operation • The output of a logic gate is used to activate an alarm whenever at least one of its inputs is LOW. XOR gate 2 and XOR gate 3. indicating that number of 1s are not odd – Applying 1011at the input generates a 1 at the output of XOR gate 3 indicating odd number of 1s 38 39 6 .

a 0 at the output of XOR gate 2 and a 0 at the output of XNOR gate 3.31/10/2012 XNOR Gate XNOR Gate • Exclusive-NOR (XNOR for short) • Truth table for XNOR gate – Standard logic symbol Input A B 0 0 0 1 This gate has only two inputs – Logical expression F = A ⊕ B – The output is LOW only when the two inputs are at opposite logic level Output F 1 0 1 0 0 1 1 1 40 XNOR Gate 41 XNOR Gate • Application example of XNOR gate • Timing diagram of XNOR gate – Detecting even parity – Applying 1011 at the input A. C and D respectively generates 1 at the output of XOR gate 1. B. indicating even number of 1s 42 43 Summary of logic gates • Fundamental logic gates – AND – OR – NOT • Universal gates – NAND – NOR • Other gates – XOR – XNOR • • • • Standard logic symbol Logical/Boolean expression Truth table Application example 44 7 . indicating that the number of 1s in the input sequence are not even – Applying 0011 generates 1 at the XNOR gate output.

- A New Family of Optically controlled logic Gates using Naphthopyran MoleculeUploaded byijoejournal
- DescrUploaded bynithilan92
- d4Uploaded byMangal Prakash
- Network TheoremUploaded bysksivasu
- Tutorial 4Uploaded byManisha Garg
- EC_EI_EN_WESTIN_QUESTION_PAPER.docUploaded byTijo Thomas
- SeqAnalysisDesignExamplesUploaded bymankinda
- Experiment3_kcl & KvlUploaded byDeependra V Singh
- rlc1-v1Uploaded byapi-243810683
- PSPICE TutorialUploaded bykumar_9583
- HC157Uploaded byaxf9dtjhd
- logicUploaded byapi-417400228
- LogicUploaded byAldrin Matibag
- Adder & SubtractorUploaded byShobhit Kumar Deepanker
- 3-4sUploaded bycikbon
- LM723 53946_DS.pdfUploaded byok1222
- 07_dft_2ppUploaded byAdiseshuMidde
- digitalUploaded byRaja Ravi Sankar
- CountersUploaded byvenkat
- Single State TransistorUploaded bykaran007_m
- CZ80PIOUploaded byAnonymous XS9jAhY1pE
- Tut Timing VerilogUploaded byuptcalc2007
- Verilog Examples Useful for FPGA & ASIC SynthesisUploaded byVIJAYPUTRA
- Leaving Class AUploaded byrgrrbbt
- 39sf020AdatasheetUploaded byqueequeg73
- Flow TransmittersUploaded byseeker4earth
- Competitive Exams_ Electronics MCQs (Practice Test 4 of 13)- ExamraceUploaded byDurga Devi
- Pyro ElectronicsUploaded bySasa Mohamed
- TA2-2_Kao_paperUploaded byMiteshwar Patel
- System Perspective Cp RavikumarUploaded bykawsik

- 1 Concrete Testing and SamplingUploaded bySana Nazir
- sow_road_construction_022610.docxUploaded bySana Nazir
- 5 Method Statement for BRICK WORKSUploaded bySana Nazir
- Form for Upgradation of FirmsUploaded bySana Nazir
- Machine DesignUploaded bySana Nazir
- Op Tim IzationUploaded bySana Nazir
- ZEC Fire Fighting Brochure.pdfUploaded bySana Nazir
- ZEC Fire Fighting BrochureUploaded bySana Nazir
- SubhanUploaded bySana Nazir
- Method Statement for PlasteringUploaded bySana Nazir
- Transformer Oil DensityUploaded bySana Nazir
- 079_088.pdfUploaded bySana Nazir
- Opf Network 1Uploaded bySana Nazir
- 16-Hydraulic Turbines [Compatibility Mode].pdfUploaded bySana Nazir
- ChartUploaded bySana Nazir
- Chapter 4 (Combinational LogicUploaded bySana Nazir
- analy(2)Uploaded bySana Nazir
- CV Format.docUploaded bySana Nazir
- NOTICE for AdmissionUploaded bySana Nazir
- EDC LAB Darlington New (Rebuilt)Uploaded bySana Nazir
- Chapter 1 Digital Systems and Binary NumbersUploaded bySana Nazir
- 232561026-University-of-Lahore-UOL-Entry-Test-Sample-Paper.pdfUploaded bySana Nazir
- UP-GRADATION PEC FORM.pdfUploaded bySana Nazir
- Reapear.docUploaded bySana Nazir
- Up-gradation Pec FormUploaded bySana Nazir
- Sample Test EngineeringUploaded bySana Nazir
- Chapter 5 Synchronous Sequential CircuitUploaded bySana Nazir
- 227348337-COMSATS-Entry-Test-Sample-Paper(1).pdfUploaded bySana Nazir
- 40342833-How-to-Select-Perfect-Name.pdfUploaded bySana Nazir