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A Pro ject Report on

16 Bit SRAM Implementation


And Analysis
by

Aamodh K (15VL01f )
Arjun S Kumar (15VL04f )
Vikas Bhardwaj (15VL26f )
I Semester M.Tech VLSI Design

Under the guidance of

Dr. Ramesh Kini

As part of
VL720: Digital IC Design

Department of Electronics and Communication


National Institute of Technology
Surathkal
6th November, 2015

16 bit SRAM Implementation and Analysis

Abstract
The objective of this project is to design and implement 16 bit SRAM with supply
voltage of 3.3V. The total number of address lines needed for accessing 16 locations is
four. 6T (6 transistors) cell is used to store one bit data. The design blocks required
are Precharge circuit, Sense amplier, 2x4 Decoders, Write enable circuit and CMOS
SRAM cell.
Post layout simulations are performed and the outputs are analysed for correct functionality using open source tools - Magic, NG Spice, IRSIM, Electronics Workbench
and Netgen. Characterization of the SRAM cell is done in term of read 0, read 1,
write0 and write 1 delays, power dissipation and Area.

Department of ECE, NITK, Surathkal

16 bit SRAM Implementation and Analysis

Contents
1

Introduction

1.1 Problem statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Implementation methodology . . . . . . . . . . . . . . . . . . . . . . .

Design

2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 SRAM cell design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Write enable circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Sense amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10

2.6 Precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11

Schematic and layout

12

3.1 Schematic of 16 bit SRAM with peripheral circuitry . . . . . . . . . .

12

3.2 Layout of SRAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13

3.3 Layout of 2-to-4 decoder . . . . . . . . . . . . . . . . . . . . . . . . . .

13

3.4 Layout of write enable circuit . . . . . . . . . . . . . . . . . . . . . . .

14

3.5 Layout of precharge circuit . . . . . . . . . . . . . . . . . . . . . . . .

14

3.6 Layout of sense amplier . . . . . . . . . . . . . . . . . . . . . . . . . .

15

3.7 Layout of 16 bit SRAM with peripheral circuit . . . . . . . . . . . . .

15

Observations

17

REFERENCES

19

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16 bit SRAM Implementation and Analysis

List of Figures
1

Block diagram of 16 bit SRAM . . . . . . . . . . . . . . . . . . . . . .

Circuit diagram of SRAM cell . . . . . . . . . . . . . . . . . . . . . . .

SRAM cell during read 0 operation . . . . . . . . . . . . . . . . . . . .

SRAM cell at start of write '0' operation . . . . . . . . . . . . . . . . .

Write enable circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Circuit diagram of pseudo NMOS NOR decoder . . . . . . . . . . . . .

Circuit diagram of sense amplier . . . . . . . . . . . . . . . . . . . . .

10

Precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11

Schematic of 16 bit SRAM with periheral circuitry . . . . . . . . . . .

12

10

Layout of SRAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13

11

Layout of 2-to-4 decoder . . . . . . . . . . . . . . . . . . . . . . . . . .

13

12

Layout of write enable circuit . . . . . . . . . . . . . . . . . . . . . . .

14

13

Layout of precharge circuit . . . . . . . . . . . . . . . . . . . . . . . .

14

14

Layout of sense amplier . . . . . . . . . . . . . . . . . . . . . . . . . .

15

15

Layout of 16 bit SRAM array along with peripheral circuits . . . . . .

16

16

Transient analysis plot of write operation . . . . . . . . . . . . . . . .

17

17

Transient analysis plot of read operation

17

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. . . . . . . . . . . . . . . .

16 bit SRAM Implementation and Analysis

List of Tables
1

Truth table of write enable circuit . . . . . . . . . . . . . . . . . . . .

Truth table of 2-to-4 decoder . . . . . . . . . . . . . . . . . . . . . . .

10

Delays for Write and Read operations . . . . . . . . . . . . . . . . . .

18

Power dissipation during Read, Write and Hold operations . . . . . . .

18

Department of ECE, NITK, Surathkal

16 bit SRAM Implementation and Analysis

Introduction

1.1 Problem statement


The aim of the project is to design and implement 16 bit SRAM (4 x 4 array) along
with the peripheral circuitry - write enable circuit, precharge circuit, row and column
decoder and sense amplier. Characterization of SRAM cell is carried out in terms of
Read delay
Write delay
Power dissipation
Area

1.2 Implementation methodology


The project implementation consisted of the following steps:
Schematic of the entire circuit was drawn using Electronics Workbench.
Layout corresponding to the schematic was laid out in Magic layout design tool.
Layout versus Schematic was performed in Netgen.
The layout was simulated in IRSIM and functional testing was done.
Parasitic capacitances were extracted from layout, appended to the NG Spice

netlist and simulated in NG Spice.

Characterization of single SRAM cell was conducted on the simulated result

with the help of the scripting language - Perl.

Department of ECE, NITK, Surathkal

16 bit SRAM Implementation and Analysis

Design

2.1 Block diagram


The block diagram of our project implementaion is as shown in Figure 1. It consist of
4 x 4 array of SRAM cell, in addition to the preipheral circuitry that includes write
enable circuit, sense amplier, precharge circuit, row and column decoders.

Figure 1: Block diagram of 16 bit SRAM

2.2 SRAM cell design


The circuit diagram of an SRAM cell is shown in Figure 2. MOSFETs M3 and M4
are pass transistors which are controlled by the word line. The nodes Q and Qbar
store the voltages corresponding to the data.

Figure 2: Circuit diagram of SRAM cell

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16 bit SRAM Implementation and Analysis


As in probably every technical system, not all performances can be improved together;
some of them are oppositional requests. The most important fact for SRAM is that
reading and writing are conicting challenges[2]. Generally, SRAM stability is limited
by switching level of the two inverters. When the '0' memory side node voltage
surmounts the switching level of the '1' side inverter, the cell ips. This must be
avoided in read case, but must be achieved in write case. This means that a cell is
either very stable and has good reading quality, but then does not ip easily during
write access and therefore has poor writing quality. A cell must always be a tradeo
between these two qualities.

Figure 3: SRAM cell during read 0 operation


The voltage levels in the SRAM cell at the start of Read 0 operation is as shown
in Figure 3. When the pass transistors M3 and M4 are turned on, by row decoder
M1 and M3 conduct a nonzero current and voltage level on the CB will begin to
drop slightly. The node voltage V 1 will increase from its initial value of 0 V. The
node voltage V 1 may exceed the threshhold voltage of M2 during this process, forcing
an unintended change of this stored state. Therefore voltage must not exceed the
threshold voltage of M2, so the transistor M2 remains turned o during read phase,
ie.,
V1max VT 2

The transistor M3 is in saturation whereas M1 is linear , equating the current equations we get
N 3
2

(VDD V1 VT N ) = N2 1 2 (V DD VT N ) V1 V12
2

Substituting V T N = 0.3121V (as in level 49 NG Spice model le) and V DD = 3.3V


we get
(W/L)1
(W/L)3

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> 4.051

16 bit SRAM Implementation and Analysis

Figure 4: SRAM cell at start of write '0' operation


The voltage levels in the SRAM cell at the start of Write 0 operation is as shown in
Figure 4. The transistor M5 is in linear region and M3 is in saturation region at the
start of write operation and once 0 is written into the cell the M5 goes to saturation
and M3 enters linear region . Then equating the current equations of M5 and M3
P 5
2

(0 VDD VT P ) = N2 3 2 (V DD VT N ) V1 V12
2

and V1max VT 2
In level 49 NG Spice model le, oxide thickness of both PMOS and NMOS is equal.
Substituting V T P = 0.411V , V T N = 0.3121V (as in level 49 NG Spice model le)
and V DD = 3.3V we get
(W/L)5
(W/L)3

< 0.4814

The selected dimensions of length and width are


L1 = L2 = L3 = L4 = L5 = L6 = 2
W1 = W2 = 42
W5 = W6 = 4
W3 = W4 = 10

The above dimensions result in Cell


satisfy the design constraints.

Ratio = 4.2

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and Pullup

Ratio = 0.4

which

16 bit SRAM Implementation and Analysis

2.3 Write enable circuit

Figure 5: Write enable circuit


Table 1: Truth table of write enable circuit
Writebar Data out1 out2
0
0
1
0
0
1
0
1
1
0
0
0
1
1
0
0
This circuit shown in Figure 5, which is the write enable circuit [1], is used to control
writing data into SRAM cell. 'Writebar' is an active low control signal. Table 1 is
the truth table of write enable circuit.

2.4 Decoder

Figure 6: Circuit diagram of pseudo NMOS NOR decoder

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16 bit SRAM Implementation and Analysis

Table 2:
A2
0
0
1
1

Truth table of 2-to-4 decoder


A1 R4 R3 R2 R1
0
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
1
0
0
0

In decoder circuit of Figure 6, A2 and A1 are the inputs to the decoder and R4,

R3, R2 and R1 are the outputs out of the decoder. It's truth table is shown in
Table 2.

The purpose of the decoder is to select a single SRAM cell among the array of

16 SRAM cells.

Pseudo NMOS 2-to-4 NOR decoder[1][2] is used. It is an active high output

decoder.

Active high decoder is used because the pass transistors within SRAM cell are

NMOS.

Design constraint: NMOSs must be suciently strong to pull down decoder

output lines when required.

2.5 Sense amplier

Figure 7: Circuit diagram of sense amplier


The circuit shown in Figure 7, is a cross-coupled CMOS inverter latch[2] used

as a sense amplier with the two bit line voltages as inputs.

The purpose of sense amplier is to increase logic detection speed during read

operation.

SE is the sense enable control signal.

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16 bit SRAM Implementation and Analysis

2.6 Precharge circuit

Figure 8: Precharge circuit


This circuit[2] shown in Figure 8 is used to maitain xed voltage on the bit lines

between consecutive read operations.

Equalization transistor maintains same voltage on the two bit lines.

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16 bit SRAM Implementation and Analysis

Schematic and layout

3.1 Schematic of 16 bit SRAM with peripheral circuitry


Vdd

Vdd

Vdd

presel

Q97

presel

Q100

Q98

Q104

presel

Q106

Q105

Q102

Q99

Vdd

presel

Q103

Q101

Q107

Q108

Vdd

Q109

B0

Vdd

Q110

Q111

Q169

Q8

Q5

Q14

Q10

Q11

Q6

Q7

Vdd

Q16

Q20

Q17

Q12

Q3

Q1

Vdd

Vdd

Q4

Q2

Q18
Q13

Q9

Q22

Q23

Q24

Q15

Q19

Q21

Vdd

B1

Q112

Vdd
Q113

Vdd

Vdd

Q170

Q114

Q26

Q28

Q32

Q38

Q34

Vdd

Q40

Q44

Q46

Vdd
Q29

Q30

Q35

Q41

Q36

Q42

Q115
Q25

Q27

Q31

Q37

Q33

Q47

Q48

Q39

Q43

Q45

B2
Q171

Q116

Q117

Vdd

Q50

Vdd

Vdd

Q52

Q56

Q62

Q58

Vdd

Q64

Q68

Q70

Vdd
Q53
Q118

Q54

B3
Q120

Q119

Q49

Q59

Q65

Q60

Q51

Q55

Q66
Q61

Q57

Q71

Q72

Q63

Q67

Q69

Q172

Vdd

U2

U1

Q74

Q80

Q77

Q78

A0 dec_dsbl

A1

Q73

Q86

Q82

Q83
Q79

Q131

Q130

Vdd

Q149

Q151

Vdd

Q141

Q148

Q143

SE
Q175

Q135

Q150
Q152

SE
Q174

Q126

Q93

Vdd
Q139

Q132

SE
Q173

Q91

Q142

Q134

SE

Q96

Q87

Vdd

Q123

Q94

Q95

Vdd

Q140

Q133

Q125

writebar

Q85

Q81

Vdd
Q121

Q92

Q90

Vdd

Q124

Vdd

Q88

Q89

Q84

Q75

Vdd

Q122

Vdd

Vdd

Q76

Q144

Q176

Q153

U5
Q127

Vdd

Q136

Q145

Q154

U6
Q157

Data

Q128

Q158

Q137

Q146

Q155

Q159

D0

Vdd

Q129

Q138

Q147

Q156

Q160

Q161

D1

Q162

Vdd
Q163

Q164

Q165

D2

Vdd
Q166

D3

Q168

Q167

U3

C1

U4

C0

Figure 9: Schematic of 16 bit SRAM with periheral circuitry


Figure 9 represents the schematic of our project.

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16 bit SRAM Implementation and Analysis

3.2 Layout of SRAM cell


Figure 10 shows the layout of SRAM cell. The word line 'wl' is made up of Polysilicon
and bit line 'bl' and 'blb' are of Metal2. 'q' and 'qb' are the data storage nodes of
the SRAM cell.

Figure 10: Layout of SRAM cell

3.3 Layout of 2-to-4 decoder


The type of decoder used in our prject is pseudo NMOS NOR decoder. The same is
shown in Figure 11.

Figure 11: Layout of 2-to-4 decoder

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16 bit SRAM Implementation and Analysis

3.4 Layout of write enable circuit


The layout corresponding to the write enable circuit of Figure 5 is as shown in Figure
12.

Figure 12: Layout of write enable circuit

3.5 Layout of precharge circuit


Figure 13 depicts the layout of precharge circuit, whose schematic is as shown in
Figure 8.

Figure 13: Layout of precharge circuit

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16 bit SRAM Implementation and Analysis

3.6 Layout of sense amplier


The layout in Figure 14 is that of the sense amplier.

Figure 14: Layout of sense amplier

3.7 Layout of 16 bit SRAM with peripheral circuit


The layout of 16 bit SRAM array along with peripheral circuitry and power rings is
shown in Figure 15. The word lines are laid out with polysilicon, while the bit lines
are laid out with Metal 2.

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16 bit SRAM Implementation and Analysis

Figure 15: Layout of 16 bit SRAM array along with peripheral circuits

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16 bit SRAM Implementation and Analysis

Observations

Plot of writing data into SRAM cell is as shown in Figure 16.

Figure 16: Transient analysis plot of write operation


Plot of reading data from SRAM cell is as shown in Figure 17.

Figure 17: Transient analysis plot of read operation


Conventions:
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16 bit SRAM Implementation and Analysis


v(50) - Bit line voltage
v(75) - word line voltage
v(X_sramcell.25) - SRAM cell's 'Q' voltage
Spice netlist corresponding to the layout in Magic was extracted. The parasitic capacitances obtained were then appended to the manually coded NG Spice netlist of
SRAM cell. The data of the plots of Figure 16 and 17 were extraxted and written
into a .data le using the command 'wrdata' in NG Spice. Applying some logic on
the extracted data using the scripting language Perl, the delays were calculated. The
delays obtained for one SRAM cell are as shown in Table 3.
Operation
Write 0
Write 1
Read 0
Read 1

Table 3: Delays for Write and Read operations


Delay (with parasitic capacitances) Delay (without parasitic capacitances)
94.99 ps
35 ps
160 ps
103 ps
19.586 ps
72.482 ps
0

Table 4 is a tabulation of our observations of power dissipation during various operations in SRAM cell for a supply voltage of 3.3V in NG Spice.
Table 4: Power dissipation during Read, Write and Hold operations
State
Power dissipation type Current Maximum instantaneous Power
Hold
Static
10 uA
33 uW
Read/Write
Dynamic
300 uA
990 uW
The area occupied by single SRAM cell shown in Figure 10 is 62 x 57 2 .
The area occupied by the entire circuit shown in Figure 15 is 443 x 565 2 , where
is the size of the grid in Magic.

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16 bit SRAM Implementation and Analysis

REFERENCES

[1] S.M. Kang and Y. Leblebici, CMOS Integrated Circuits Analysis and Design, 2nd
Edition, McGraw Hill, 2003.
[2] J.M. Rabaey, A. Chandrakasan and B. Nikolic, Digital
Design Perspective, 2nd Edition, Pearson Education, 2003.

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Integrated Circuits - A

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