Professional Documents
Culture Documents
I.
INTRODUCTION
II.
H Z
Let
> H Z @
H1 Z H n Z
H Z
AV
1 j Z Z1, L
AV
1 j Z Z1, L
1
2
AV
Z 3 dB , total
Z1, L 2 n 1
Z1, 3 dB 2 n 1
(2)
Eq. (2) readily shows that the overall bandwidth of a multistage cascaded amplifier network shrinks monolithically.
B. Bandwidth Analysis for Interpolated Flash ADCs
Consider an interpolated flash ADC consisting of preamplifier stages and the comparator stage, the number of preamplifier stages varies upon ADC resolution bits and its
interpolation factors. Normally, higher resolution results in
more stages; while a larger interpolation factor reduces the
stage numbers. Detailed structure for a practical 4bits
capacitive interpolated flash ADC is given in Figs. 1&2. Fig. 1
depicts pre-amplifier influences on the flash ADC, which
consists of edge pre-amplifiers and interpolated pre-amplifiers.
- 166 -
ISOCC 2010
CL,central
C p 3 Cs // Cm Cgs ,in
C p 3 Cs // 1 AV Cgd ,in Cgs ,in
Z3 dB , ADC
>
2n 1
Rout C p 3 Cs // Cm C gs ,in
- 167 -
ISOCC 2010
vo t
AV vin 1 e
t
f speed , ADC
RL CL , AV is low
frequency amplifier gain, RL and CL are load resistance and
capacitance of the amplifier, respectively. It is understood that
the time required to amplify input signals to a certain output
magnitude depends strongly on the difference of the input
signals. For an ADC chip, the worst case is when the
difference between the input and one of the reference is 1/2
LSB, which makes both the two adjacent pre-amplifiers take
longer time to amplify signals. On the other hand, the output
of a pre-amplifier will be sent to a latched comparator, which
requires the output signal to be large enough in order to be
sensed by the latched comparator for accurate signal
comparison. Thus, the following can be obtained,
t
W
AV LSB 1 e 'vL
n 1
2
2
comparator,
LSB
is
Full Scale
constant. 1 2
n 1
number
2 , W
n
of
pre-amplifier
III.
stages,
ts
1
1
W ln
W
ln
n
n
n
'vL 2
'v L 2 2
1
1
An LSB
n
AV FS
fs
1
2 ts
S f 3 dB
1
ln
n
n
1 'vL 2 2
n
AV FS
2 n 1 f 3 dB , central
1
ln
n
n
1 'vL 2 2
n
AV FS
(9)
- 168 -
ISOCC 2010
shows that the current flowing from the capacitor to ground has
periodic spikes when capacitors charge and discharge. Note
that the input and output capacitors are used for interpolation in
ADC design, hence, parasitic capacitances should be
considered when calculating dynamic power. The dynamic
power dissipation can be expressed as,
PD ,total
Pin PL
(10)
PD ,total
(11)
90PW
Compare the dynamic power with the static power, which
is about 2.28mW, the dynamic power is still relatively small
for a single amplifier. However, for the whole ADC core, the
overall dynamic power could be relatively large. The
capacitive interpolation makes whole chip power estimation
complicated, because the edge pre-amplifiers and interpolated
pre-amplifiers have different input and loading capacitors. For
our 4-bit ADC designed, the dynamic power is roughly
(including 19 edge pre-amps and 15 interpolated pre-amps),
PD ,overall
new ADC design matrix technique. Fig. 2 shows the 4bits flash
ADC designed in 90nm CMOS in this work. The individual
interpolation pre-amplifier bandwidth is obtained as about
3.3GHz. Apply it into Eq. (9), the overall ADC sampling speed
can be calculated as,
19 u 90 PW
0.5 u 4 u 100f u 0.32 2 u 150f u 0.6 2 u 2G u 15 (12)
3.87 mW
f speed , ADC
S 2 4 1 u 3.3
1
ln
4
4
1 20mV 2 2
24 400mV
2.8GSps
The theoretical maximum speed calculated for this ADC is
about 2.8GSps, which is reasonably close to the actual ADC
sampling rate of about 2.3GSps obtained. Another practical
design in 130nm CMOS technology simulated a maximum
speed of 1GSps while theoretical calculation is 1.22GSps.
These examples confirm that our new design matrix works
reasonably well in practical designs. It can also be used to
directly map whole-chip ADC performance specs with key
design factors at different levels, i.e., ADC architecture, block
circuit, device and process parameters, hence, provides useful
quantitative design guidelines for flash ADC designs.
V.
CONCLUSION
[4]
[5]
- 169 -
ISOCC 2010