Configurable System-on-Chip: Xilinx EDK

Mr. A. B. Shinde
Lecturer, Department of Electronics Engg., P.V.P.I.T., Budhgaon.
1

Field-Programmable Gate Arrays (FPGAs)
  

Fine-grained reconfigurable hardware Gate-Array: regular structure of “logic cells”, connected through an interconnection network Configuration stored in SRAM, must be loaded on startup

EPROM

2

FPGA toolflow
HDL
(VHDL / Verilog)


Synthesize

Hardware design is traditionally done by modeling the system in a hardware description language An FPGA “compiler” (synthesis tool) generates a netlist,

Netlist

Map Place

 

Route


Bitstream

which is then mapped to the FPGA technology, the inferred components are placed on the chip, and the connecting signals are routed through the interconnection network.
3

HDL Synthesis
HDL
(VHDL / Verilog)

process(clk, reset) begin

Synthesize

if reset = ‚1‘ then output <= ‚0‘; elsif rising_edge(clk) then output <= a XOR b; end if;
end process;

Netlist

Map Place Route
a b Register


clk

D

Q

output

clear

Bitstream

reset

4

Technology Mapping
Register

HDL
(VHDL / Verilog)

a b


clk

D

Q

output

clear

Synthesize

reset

Netlist

Map Place Route

Bitstream

5

Place & Route
HDL
(VHDL / Verilog)

Synthesize

Netlist

Map Place Route

Bitstream

6

Xilinx ISE

7

Traditional Embedded System

Ethernet MAC

Audio Codec

CLK CLK

Power Supply

GP I/O
Address Decode Unit Memory Controller

Interrupt Controller

Timer

CPU
(uP / DSP)
CoProc.

UART
custom IF-logic

L C

CLK

SRAM

SRAM

SRAM

SDRAM

SDRAM

Display Controller

Images by H.Walder

8

Traditional Embedded System

Ethernet MAC

Audio

CLK CLK

Power Supply

FPGA Codec
Interrupt Controller Address Decode Unit Memory Controller

GP I/O

Timer

CPU
(uP / DSP)
CoProc.

UART
custom IF-logic

L C

CLK

SRAM

SRAM

SRAM

SDRAM

SDRAM

Display Controller

Images by H.Walder

9

Configurable System on Chip (CSoC)

Audio Codec

EPROM

Power Supply

L C

SRAM

SRAM

SRAM

SDRAM

SDRAM
Images by H.Walder

10

Advantages

Fewer physical components Shorter development cycles Field-programmable (updates, new features...) Possibly higher performance through on-chip integration
 Signals

on a chip can typically be clocked higher than signals across board traces  Optimization between modules possible

Partial reconfigurability
 Exchange

peripherals while the rest of the system keeps running

11

Embedded CPUs

PowerPC 405 (hard core)
32 bit embedded PowerPC RISC architecture  Up to 450 MHz  2x 16 kB instruction and data caches  Memory management unit (MMU)  Hardware multiply and divide  Coprocessor interface (APU)  Embedded in Virtex-II Pro and Virtex-4  PLB and OCM bus interfaces

MicroBlaze (soft core)
32 bit RISC architecture  2-64 kB instruction and data caches  Barrel Shifter  Hardware multiply and divide  OPB and LMB bus interfaces

Images by Xilinx

Others

NIOS (Altera), ARM, PicoBlaze (Xilinx), ...
12

CoreConnect Bus Architecture

Flexible bus architecture for embedded Systems and SoCs
 Developed

by IBM  Used by Xilinx EDK

 

Processor Local Bus (PLB) On-Chip Peripheral Bus (OPB) Device Control Register Bus (DCR)

Alternatives:
 AMBA

(Altera)  Wishbone (OpenCores)  Proprietary bus architectures

13

Bus Configurations

Images by H.Walder

LMB: Local Memory Bus (for on-chip memory) OPB: On-Chip Peripheral Bus

14

CSoC Design Flow (Hardware)
HDL Platform (VHDL / Description
Verilog)


Netlist Synthesize Generation Netlist Netlist Map Place XST
(Map, Place & Route)

Platform description is translated/assembled into netlist, which in turn is either mapped, placed and routed onto FPGA, or

VHDL

Xilinx ISE
(VHDL Edit, Map, Place & Route)

Route

imported into ISE and used in a larger FPGA design

Bitstream

15

CSoC Design Flow (Hardware)
Platform Description

Netlist Generation

Netlist

VHDL

XST
(Map, Place & Route)

Xilinx ISE
(VHDL Edit, Map, Place & Route)

Bitstream
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration

16

CSoC Design Flow (Software)
Platform Description

Library Generation

*.a *.h

User sources *.h *.c

Netlist Generation

Compile & Link

Netlist

Update Bitstream
XST or ISE
(Map, Place & Route)

*.elf

Bitstream

Bitstream with executable Code

Program

17

CSoC Design Flow (Software)
Platform Description

Library Generation

*.a *.h

User sources *.h *.c

Netlist Generation

Compile & Link

Netlist

Update Bitstream
XST or ISE
(Map, Place & Route)

*.elf

Bitstream

Bitstream with executable Code

Program

18

Demonstration

Simple System: LED Counter
 Bus

Configuration:

DOPB
MicroBlaze CPU Core


MicroBlaze CPU Instruction- and data memories attached to local memory buses General Purpose I/O (GPIO) attached to data-side OPB

GP I/O

ILMB

DLMB

BRAM
Image by H.Walder

Target: Xilinx Spartan-III (XC3S200)
 200’000

gates (4’320 logic cells)  480 CLBs (24 x 20)  216 Kbits Block RAM  173 User I/O pins  12 18x18 bit multipliers

19

Demonstration
Spartan III FPGA

50 MHz clock (back side) 7-segment display Reset button
E14

CLK
RST

LED0 F13
LED7 R16 P15
Image by H.Walder

N16

G13
N15

P16

20

Any

?’s
shindesir.pvp@gmail.com
21

Sign up to vote on this title
UsefulNot useful