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Home Work: 2

Uday A Korat
Red Id: 818480618

Uday A Korat | SAN DIEGO STATE UNIVERSITY

always @(posedge CLK) begin //control signal RESET with highest priority if (RST) begin reg_a<=0. //multiplier input CLK. //multiplicand input [WL-1:0]b. partial_product<=0. reg [2*WL-1:0] partial_product. Uday A Korat | SAN DIEGO STATE UNIVERSITY .//control signal to load input value in register output [2*WL-1:0]Mult_out). partial_product<=0. //control signal to reset all register input LOAD.Question: 1 Shift and Add Multiplier  Verilog Code:  Top Module: `timescale 1ns / 1ns module shift_add_multiplier #(parameter WL = 4) //word length parameter of input and output (input [WL-1:0]a. end //left shift for multiplicand reg_a <= reg_a<<1. //register for multiplier assign Mult_out = partial_product. reg_b<=0. //register for multiplicand reg [WL-1:0] reg_b. reg_b<=b. end //control signal to LOAD input value in register else if (LOAD) begin reg_a<=a. //clock signal input RST. end else begin//partial product generation and addition if(reg_b[0]) begin //if LSB of multiplier is 1 //then add shfted muliplicand according iteration value partial_product <= partial_product + reg_a. // partial product accumulator reg [2*WL-1:0] reg_a. //right shift for multiplier reg_b <= reg_b>>1.

a(a). @(posedge CLK) LOAD =0. @(posedge CLK) LOAD = 1. parameter ClockPeriod = 50.LOAD(LOAD).end //multiplier output after //every partial product generation and addition end endmodule  Test Bench: `timescale 1ns / 1ns module tb_shift_add_multiplier. reg CLK. // Inputs reg [3:0] a. RST = 0. @(posedge CLK) RST = 1. // Outputs wire [7:0] Mult_out. reg LOAD.LOAD = 0. always #(ClockPeriod/2) CLK = ~CLK. . // Instantiate the Unit Under Test (UUT) shift_add_multiplier uut ( . reg [3:0] b. . . end endmodule Uday A Korat | SAN DIEGO STATE UNIVERSITY . b = 4'b1001. a = 4'b1000. RST = 0. initial begin LOAD = 0. .b(b).CLK(CLK).RST(RST).Mult_out(Mult_out)). . initial CLK = 0. #300 $finish. reg RST.

 Waveform: Uday A Korat | SAN DIEGO STATE UNIVERSITY .

// width for fraction part of sum reg [int_len+frc_len-1:0] reg_in1.Question: 2 Fixed Point Adder  Verilog Code:  Top Module: `timescale 1ns / 1ns `define WIO1 (WIO >= 2)? (WIO+frc_len-2) : frc_len `define Max_len ((int_len+frc_len-2)>= (WIO+frc_len-1)) ? (int_len+frc_len-2) : (WIO+frc_len-1) `define trun_size (WIO < int_len)? ((int_len+frc_len-1)-(WIO+frc_len-1)) : 1 module FixedPoint_Adder #(parameter WI1 = 3. //INPUT-2 fraction length WIO = (WI1>WI2)? WI1+1:WI2+1. //reg [(`trun_size)-1:0] reg_sign. //OUTPUT integer length WFO = (WF1>WF2)? WF1:WF2) //OUTPUT fraction length (input signed [WI1+WF1-1:0] in1. //register for Integer part of IN1 reg [int_len+frc_len-1:frc_len] int_in2. wire [int_len+frc_len:0] tmp. //width for integer part of sum parameter frc_len = (WF1>WF2)? WF1:WF2. parameter int_len = (WI1>WI2)? WI1:WI2. //register for Fraction part of IN1 reg [frc_len-1:0] frc_in2. // register for Integer part of IN2 reg [frc_len-1:0] frc_in1. //INPUT-2 integer length WF2 = 3. //register for Fraction part of IN2 //reg [(`trun_size)-1:0] reg_trun. // Integer register for output SUM reg [WFO-1:0] frc_out. //INPUT-1 integer length WF1 = 4. //INPUT-1 fraction length WI2 = 4. // wired connection of SUM reg sign_bit. output reg signed [WIO+WFO-1:0] FixedPoint_Add_Out). // Fraction part register for output SUM //---------------------------------------------------------------------------// //ADJUSTING NUMBERS TO MAKE EQUAL RADIX POINT PLACE //--------------------------------------------------------------------------// //INTEGER adjustment Uday A Korat | SAN DIEGO STATE UNIVERSITY . output reg overFlow. reg [WIO-1:0] int_out. input signed [WI2+WF2-1:0] in2. //register for INPUT2 = IN2 reg [int_len+frc_len-1:frc_len] int_in1. //register for INPUT1 = IN1 reg [int_len+frc_len-1:0] reg_in2.

int_in1 = in1[WI1+WF1-1:WF1].always @* begin if (WI1 <= WI2) begin int_in1 = {{(WI2-WI1){in1[WI1+WF1-1]}}. frc_in2 = in2[WF2-1:0]. in1[WI1+WF1-1:WF1]}. int_in2 = in2[WI2+WF2-1:WF2]. in2[WI2+WF2-1:WF2]}. //----------------------------------------------------------------------// //adjust bits for OUTPUT_FRACTION as user define output fraction bitwidth //padding with zero or truncation from least significant bits always @* begin if (WFO >= frc_len) begin frc_out = {tmp[frc_len-1:0]. end Uday A Korat | SAN DIEGO STATE UNIVERSITY . end //-------------------------------------------------------// ADDITION of bit adjusted two input assign tmp = reg_in1 + reg_in2. end end //--------------------------------------------------------------------------// //new adjusted NUMBERS always @* begin reg_in1 = {int_in1 . {(WF2-WF1){1'b0}}}. {(WFO-frc_len){1'b0}}}. {(WF1-WF2){1'b0}}}. frc_in1 = in1[WF1-1:0]. reg_in2 = {int_in2 . end end //--------------------------------------------------------------------------// //FRACTION adjustment always @* begin if (WF1 <= WF2) begin frc_in1 = { in1[WF1-1:0]. end else begin frc_in2 = {in2[WF2-1:0]. frc_in1}. end else begin int_in2 = {{(WI1-WI2){in2[WI2+WF2-1]}}. frc_in2}.

end end else begin int_out = {{(WIO-int_len){sign_bit}} . tmp[int_len+frc_len-1:frc_len] }. end else begin sign_bit = tmp[int_len+frc_len-1].else begin //(WFO<frc_len) frc_out = tmp[frc_len-1:frc_len-WFO]. overFlow = 1'b0. end end else begin // (WIO<int_len) if (WIO == 1) begin int_out = {sign_bit}. end else begin overFlow = 1'b1. end end //--------------------------------------------------------------------// // signbit of OutPut always @* begin if ((in1[WI1+WF1-1] == in2[WI2+WF2-1])) begin sign_bit = tmp[int_len+frc_len]. end end //--------------------------------------------------------------------// //OUTPUT_INTEGER SignBit Padding . if (int_out[WIO-1] == in1[WI1+WF1-1]) begin// overflow checking for corner case overFlow = 1'b0. //Signbit only for integer part if WIO = 1 end else begin Uday A Korat | SAN DIEGO STATE UNIVERSITY . Truncation and Overflow conditions always @* begin if (WIO >= int_len) begin if ((in1[WI1+WF1-1] == in2[WI2+WF2-1])) begin int_out = {{(WIO-int_len){sign_bit}} . tmp[int_len+frc_len-1:frc_len] }.

int_out = {sign_bit . tmp[`WIO1:frc_len]}. end end end //-----------------------------------------------------------------------// //overFlow // comparison of truncated bit and sign bit to check error in output and // generate overflow always @* begin if(WIO < int_len) begin if ( tmp[`Max_len: WIO+frc_len-1] == ({(`trun_size){tmp[int_len+frc_len-1]}})) begin overFlow = 1'b0. end end end //------------------------------------------------------------------// // Final Answer with truncation and adjustment always @* begin FixedPoint_Add_Out <= {int_out.frc_out}. end else begin overFlow = 1'b1. end endmodule Uday A Korat | SAN DIEGO STATE UNIVERSITY .

i = i+1) begin if (in[i] == 1'b1) begin retVal = retVal + (2. i < WI+WF-1.WI1(3). input [63:0] in.WI2) . //Real Number Presentation real in1_real. input integer WI.(in[WI+WF-1] * (2.WF2(3).WI2(4). . wire [3:0]Out3. real Floatout1. wire overFlow2. out3_real. in2_real.WIO(5). Floatout2.0**(i-WF)). //===== Function Definition function real FixedToFloat. . wire overFlow1. out2_real. wire [6:0] Out2. // Outputs wire [9:0] Out1. for (i = 0. //Inputs reg [6:0] in1. real out1_real. wire overFlow3.WFO(5)) Uday A Korat | SAN DIEGO STATE UNIVERSITY . . real retVal. end end FixedToFloat = retVal . . begin retVal = 0. WFO>max(WF1. input integer WF.WF2) FixedPoint_Adder #(. integer i. . end endfunction // Instantiate the Unit Under Test (UUT) //WIO>max(WI1. Test Bench: `timescale 1ns / 1ns module tb_FixedPoint_Adder.WF1(4). reg [6:0] in2. Floatout3.0**(WI-1))).

.WF2(3).WFO(3)) uut02 (. end always @ in1 in1_real = FixedToFloat(in1.FixedPoint_Add_Out(Out2)). in1 = 7'b100_0000.WI1(3).in2(in2).overFlow(overFlow2). in2 = 7'b0011_000.//Ideal Output always @ Out2 out2_real = FixedToFloat(Out2.WI2).in2(in2). initial begin // Initialize Inputs in1 = 7'b011_1111. . 3).WI2). .WIO(4). 4).overFlow(overFlow3). in2 = 7'b0110_000.WI1(3).in1(in1). //convert in2 to real always @ Out1 out1_real = FixedToFloat(Out1. //WIO<min(WI1. .WI2(4). .WF1(4). in2 = 7'b0111_111. .FixedPoint_Add_Out(Out3)). 2).WI2(4). 3. .WFO(2)) uut03 (. $finish. .WIO(2).//convert Out2 to real always @ (in1_real or in2_real) Floatout2 = in1_real + in2_real. . . . // Wait 100 ns for global reset to finish #100.in1(in1).WF2) FixedPoint_Adder #(. //convert in1 to real always @ in2 in2_real = FixedToFloat(in2.in1(in1).uut01 (. . 5.WF2) FixedPoint_Adder #(.in2(in2).//Output1 //WIO=max(WI1. 4.WF2(3). 3). 2. . WFO <min(WF1.FixedPoint_Add_Out(Out1)). in1 = 7'b111_0000. . .overFlow(overFlow1). // Wait 100 ns for global #100.//convert Out3 to real always @ (in1_real or in2_real) Floatout3 = in1_real + in2_real. . .//Ideal Output always @ Out3 out3_real = FixedToFloat(Out3. WFO < max(WF1.//convert Out2 to real always @ (in1_real or in2_real) Floatout1 = in1_real + in2_real. 5). // Wait 100 ns for global reset to finish #100.//Ideal Output endmodule Uday A Korat | SAN DIEGO STATE UNIVERSITY . . . 4.WF1(4).

 Wave Form: Uday A Korat | SAN DIEGO STATE UNIVERSITY .