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Course-­‐PM  MCC091  2013/KJ&LP  

Version  1.0  

2013-­‐09-­‐02  

Course  PM  MCC091    
Introduction  to  Integrated  Circuit  Design  
Academic  year  2013—2014  
Course  web  site  
For the latest information always check the course web site, which is located in PingPong,
Chalmers learning management system. We publish as much as we can with open access, but
to access all information you must log in with your Chalmers login ID and you must be
registered for the course. The URL for the login page is https://pingpong.chalmers.se
The three sections below are taken from the syllabus that can be found at
https://www.student.chalmers.se/sp/course?course_id=18256

Aim  
The overall aim of the course is to introduce the student to the field of CMOS integrated
circuit design and to the use of industrial CAD tools and their role in the application-specific
integrated circuit (ASIC) design flow.

Goals    
After the course the student should be able to
• conceive, design, implement, and verify the functionality of basic digital and analog
CMOS building blocks in the context of standard-cell design.
• critically and systematically integrate knowledge to model, simulate, predict and
evaluate CMOS circuit behavior, also with limited or incomplete information.
• use simple models suitable for back-of-the-envelope hand calculations to predict and
evaluate circuit performance measures like power dissipation and critical path delays, and to
use such models for choosing the appropriate cell structure and driving capability.
• carry out basic circuit design tasks within given constraints by applying suitable
methods, also when in a context where technical aspects that are not cost effective might
be sacrificed for simplicity and time-to-market aspects.
• identify, formulate, and solve basic problems concerning subsystem structures such as
adders/ALUs, and to make layout/performance trade-offs.
• use industrial-type design automation tools for designing basic CMOS circuit elements
following the design flow set up by such tools (including tools for schematic capture, circuit
simulation, layout, design rule checking (DRC) and layout-vs-schematic (LVS)).
• describe the fundamental limitations of the available circuit level design automation
tools and the available CMOS technology platforms.
• propose solutions to basic design problems and after having solved the problem, on paper or
in lab, communicate their conclusions and the rationale underpinning these conclusions.

 
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Path efforts. basic building blocks. • Critical path delays. • Clock generation and clock distribution.resistive load. second-order effects.transistor sizing for improved driving capability. • Basic layout using standard-cell layout templates. . Power gating. buffer sizing. FO4 delay. . pseudo-NMOS load. and XOR gates. • Interconnect and wire delay.biasing and small-signal voltage amplification. . active CMOS load. Set-up and hold time requirements. Front-end and back-end processing steps. technology scaling. circuit simulation. • Latches and flip-flops. rise/fall time. • SPICE technology files. Hands-on design skill training using Cadence electronic design automation tools. schematic capture.Course-­‐PM  MCC091  2013/KJ&LP   Version  1.the basic building block • Static properties . technology platforms and circuit design tools. and output parasitic capacitance • Definition of logical effort. process corners • The inverter as an analog amplifier . • The use of repeaters for delay optimization.large-signal two-port inverter model: input and output parasitic capacitance. • The MOSFET as a digital switch and an analog small-signal amplifier • piecewise linear (PWL) current model with the MOSFET as a voltage-controlled resistor or current-source • MOSFET two-port large-signal model . • Power dissipation. NAND. Sizing gates for minimum path delay. • Sizing MOSFETs in a logic gate for equal rise and fall times. . • CMOS technology and fabrication.analog building blocks. 2 . • Dynamic logic gate two-port model: input capacitance.the voltage transfer characteristics (VTC) . DRC and LVS. • The inverter . • Two-port RC wire model • Elmore's formula for wire delay estimations. or current source. • Dynamic properties .simple RC delay formula. output driving capability. Building logic gates with MOSFET switches. Current mirrors. output driving capability. Clock gating. OAI.0   2013-­‐09-­‐02   Content     • Introduction to CMOS integrated circuit design. Power distribution. • Design flow including basic floor planning. NOR.definition of propagation delay. • Carry look-ahead and prefix-tree adders. layout. small-signal two-port model .adding the intrinsic input capacitance and the parasitic output capacitance to the two-port model. • Case study: 4-bit digital comparator. AOI. Single stage CMOS amplifiers.the MOSFET as a resistor. • MOSFET capacitance model . • Static CMOS logic gates.

If you fall ill. You must hand in your solutions no later than the deadlines shown in the table below. If you worked with another student this way. and one or two circuitdesign tasks organized as a series of hands-on laboratory exercises using industrial electronic design automation (EDA) tools from Cadence. The labs are compulsory. giving you generic tools to estimate cost and performance properties of present and future CMOS technologies. both on Mondays. one floor below the lecture hall ED.5 credit points. All submissions are individual because they are an integral part of the assessment in the course. 3 . through CMOS logic gates to sub-systems like adders and data paths.15-5PM Tuesdays 1. There will be two lab sessions.45AM Mondays 1. so called lab pairs. The course is organized as a bottom-up sister course to the top-down organized DAT092 "Introduction to electronic system design". Scheduled  times  and  activities   Time     Mondays 8-11.0   2013-­‐09-­‐02   Course  organization   The course runs during study period 1 and gives 7. The course takes you from the basic building block. that person must be identified on your handed-in solution. or other unforeseen things happen to you very late. you will not be allowed to do the lab. the MOS Field Effect Transistor. Lab  sessions   The lab sessions will run in study weeks 4-7. The course is organized with weekly lectures. If we detect deficiencies in your solutions you get a return and you will have revise and resubmit. You must be able to explain your solution at our request. You may work together with one other student when you complete the problem sets but each of you must hand in your own solution. If you have not submitted your prelab on time. They will take place in the CSE dept’s lab room 4220 on floor 4 in the EDIT building. The labs will be performed in groups of two students. home assignments. We will let you know of any changes to the schedule on the course homepage in PingPong. The groups will be posted on the course web page no later than at the beginning of study week 3.15-4PM Thursdays 1.15-5PM Activity       Labs group 1 Labs group 2 Lecture/tutorial Lecture/tutorial Week/Room   weeks 4-7 room 4220 weeks 4-7 room 4220 weeks 1-7 room ED weeks 1-7 room ED We will not use all seven hours of lecture/ tutorial time each week. please send a text message or an e-mail to Lena and Kasyab. Technology-node-independent performance models for power and speed are derived.Course-­‐PM  MCC091  2013/KJ&LP   Version  1. The teachers will decide who gets assigned to which session and on the lab pairs. Hand-­‐in  problem  sets  &  pre-­‐lab  preparations   There will be three hand-in problem sets and four pre-lab preparations for the labs: all in all 7 solution sets to hand in. the submission of which on time before the lab session is a prerequisite for being allowed to the lab hall. Each laboratory session is associated with a pre-lab home assignment.

59PM (midnight) Fri Sept 20 1PM Fri Sept 27 1PM Fri Oct 4 1PM Fri Oct 11 1PM Fri Oct 18 11.59PM (midnight) Feedback   Feedback on your submission will be given in PingPong. We prefer typed solutions since they are easier to read.  feedback. Only submissions through PingPong will be considered since we are several teachers who cooperate on the grading and feedback. you will receive feedback no later than by the start of the lecture on the following Thursday. Your solutions shall be submitted as pdf files except when you are expected to submit an excel file. we want your resubmission within one week from when you received our feedback. we shall use the timestamp on your submission to decide whether your submission was submitted on time or not. as well as the number of bonus points you have.0   2013-­‐09-­‐02   Submissions. Submission     1 Hand-in set 1 2 Hand-in set 2 3 Pre-lab 1 4 Pre-lab 2 5 Pre-lab 3 6 Pre-lab 4 7 Hand-in set 3   Deadline   Mon Sept 9 11. If you write by hand. After that we will not grade any submissions until January 2014 unless there are special circumstances such as illness. however we accept hand-written solutions (except when we want you to submit an excel file). The final deadline for any resubmissions or late submissions that are to be included in the examination for period 1 2013 is Monday November 11 at 8AM.59PM (midnight) Mon Sept 16 11. we shall give you feedback no later than at the beginning of your lab session.Course-­‐PM  MCC091  2013/KJ&LP   Version  1. Revisions   If you get a return. you shall zip them into one file. Instead. If you submit your prelabs on time.this is intentionally so. Please.     4 . For solutions to hand-in problem sets that you hand in on Mondays.  returns  and  re-­‐submissions   Submissions   Your solutions to hand-in problems and prelab assignments shall be submitted via PingPong. if rejected it must be revised and resubmitted in PingPong for approval. You will be able to see if you passed or if you got a return and have to revise. note that the assignment deadlines are not shown in PingPong . If your hand-in solution comprises more than one file. This way any late submission and revisions can be submitted to the same inbox. your submission will either be approved or rejected. but then you to scan your solution and submit it as a pdf file. you have to write legibly so we can read it. You can follow your progress in PingPong.

se phone: 772 1822. Cremona.se room 4447 (EDIT building floor 4V) Jesper Johansson: jjesper@student. If you already have Sedra & Smith: Microelectronics Circuits. Lena you can find in her office. This book is the international edition of the more expensive hardback book ”CMOS VLSI Design” 4th edition.jeppson@chalmers. 5th or 6th Edition. It is however not available as an e-book. In that case. office: room B528 in MC2 building.com For the analog part we will use a couple of sections from the book: Allen & Holburg: CMOS Analog Circuit Design 2nd Edition.chalmers. 4113.chalmers.0   2013-­‐09-­‐02   Literature     The main textbook is Weste and Harris: ”Integrated Circuit Design” 4th Edition. or 0706-268907 office: room 4113 (EDIT building floor 4 V. Week 2: Week 3: Week 4: Week 5: Week 6: Week 7: Mon Sept 9 3-4PM (Lena) Thu Sept 12 right after lecture (Lena) Mon Sept 16 3-4PM (Lena) Fri Sept 20 9-9. Some of these times we may have to change due to unforeseen events. the consultation times are entered as events. It is available at the Chalmers bookstore. It is available as an e-book from the Chalmers Library so you do not have to buy an entire book for this part. Instructors   Lecturer and Kjell Jeppson. which is the meeting room in the same corridor.se Consultation  hours   We have scheduled consultation times that should fit with the deadlines for the pre-lab and hand-in problem sets.cmosvlsi. Live links and reading instructions will be made available on the course web site. facing Rännvägen) Lab teaching Kasyab Subramanian assistants: kasyab@chalmers. notices will be posted in the message board on the course PingPong page. 5 .se Christoffer Fougstedt: chrfou@student. phone: 772 1856. Examiner: kjell. that book can also be used for most of the analog part.45AM (Lena) Fri Oct 18 2-3PM (Lena & Kjell) In the PingPong calendar for the course.45AM (Lena) Fri Sept 27 2-3PM (Kjell) Fri Oct 4 9-10AM (Lena) Fri Oct 11 9-9. Kjell can be found in room 4128.There is a companion web site for the book at http://www.se Lecturer: Lena Peterson lenap@chalmers.Course-­‐PM  MCC091  2013/KJ&LP   Version  1. and at DC in the EDIT building. used in previous courses at Chalmers.

legibly written 4. Estimated time for the home assignments are 35 hours (5 hrs. we must understand what you mean) 5. Parameter sheets and design rule sheets are also allowed when needed.Course-­‐PM  MCC091  2013/KJ&LP   Version  1. The remaining 100 hours are allotted for self-studies.5-credit course is to correspond to 1/8 of an academic year. comprehensible (that is. i. a hand-in or prelab problem-set solution must be 1. They will be included with the exam when needed so you do not have to bring your own. Bonus points will be shown in PingPong for each assignment as Mark=1 or Mark=0. handed in on time 2. substantially correct (that is only minor mistakes) Your submissions should be written in English. Any bonus points (see below) will be added to your score before the resulting higher grade is determined once you have reached 30 points on the exam.5 credits are divided into three course elements (Sw. So. reading textbooks. Hence. for lab sessions and 49 hrs. kursmoment): Course  element   Credits   What  you  have  to  do  to  earn  these  credits   0111  Written  examination   3   Pass  the  final  exam   Pass   the   four   pre-­‐lab   problem   sets   and   pass   the   0211  Laboratory   3   four  in-­‐lab  sessions   0311  Home    assignments   1. with two courses running in parallel the nominal work load is 50 hours/week. complete 3. etc.5   Pass  the  three  hand-­‐in  problem  sets   Your grade is determined by the final exam (for details./assignment). 40 points for the grade 4 and 30 points for the grade 3.one point per hand-in and prelab problem set. The exam comprises six problems each with a maximum score of 10 points. If you have less than 30 points you fail the exam (usually recorded as U in the grading records). to a work load of 1600/8=200 hours.e. You need at least 50 points to earn the grade 5. Workload   A 7. Bonus points are valid for one year. see below). thus in all 60 points. Allowed aids are pen and paper and a calculator. Bonus  points     Good hand-in problem-set and prelab solutions submitted on time will earn you bonus points .0   2013-­‐09-­‐02   Examination   The course’s 7. The time scheduled for this course 65 hours. you can earn seven bonus points. bonus points cannot be used to pass the course but can give you a higher grade. The  final  exam   The final exam is a four-hour closed-book exam. During the eight weeks of a study period this corresponds to 25 hours a week. 16 hrs. All in all.   6 . To earn you a bonus point. for lectures and exercises.

59PM   1.45AM & 1.15-4PM 1.15-4PM 1.15-5PM 1.15-4PM 1.30-­‐12.15-5PM 1.59PM   1. Week 1 (36) Tues 3/9 Thurs 5/9 1.15-5PM 11. there may be some changes.15-4PM 1.15-5PM 1.59PM     Lab 4 group 1 Lab 4 group 2 Lecture/tutorial Lecture/tutorial Deadline  hand-­‐in  3     Exam week Mon  21/10     8.15-5PM Lecture Lecture/tutorial   Week 2 (37) Mon  9/9   Tues 10/9 Thu 12/9 11.15-5PM in study weeks 4-7 in lab room 4220.15-5PM 1. This is a preliminary schedule.15-5PM. especially not in weeks 4-7 when there are lab sessions. both in lecture room ED.45AM 1. Lab slots are Monday 8-11.15-5PM 1PM         Deadline  hand-­‐in  2   Lecture/tutorial Lecture/tutorial Deadline  prelab  1   Week 4 (39) Mon 23/9 Mon 23/9 Tues 24/9 Thur 26/9 Fri  27/9     8-11.Course-­‐PM  MCC091  2013/KJ&LP   Version  1.15-5PM 1PM     Lab 2 group 1 Lab 2 group 2 Lecture/tutorial Lecture/tutorial Deadline  prelab  3   Week 6 (41) Mon 7/10 Mon 7/10 Tues 8/10 Thur 10/10 Fri  11/10         8-11.15-4PM 1.15-5PM 1PM         Lab 1 group 1 Lab 1 group 2 Lecture/tutorial Lecture/tutorial Deadline  prelab  2   Week 5 (40) Mon 30/9 Mon 30/9 Tues 1/10 Thur 3/10 Fri  4/10     8-11.45AM 1.15-4PM 1.0   2013-­‐09-­‐02   Overview  of  scheduled  activities  &  deadlines   The classroom time slots are Tuesdays 1.15-5PM Deadline  hand-­‐in  1 Lecture/tutorial Lecture/tutorial   Week 3 (38) Mon  16/9   Tues 17/9 Thur 19/9 Fri  20/9     11.45AM 1.15-4PM 1.15-4PM and Thursdays 1.45AM 1.15-5PM 1PM         Lab 3 group 1 Lab 3 group 2 Lecture/tutorial Lecture/tutorial Deadline  prelab  4   Week 7 (42) Mon 14/10 Mon 14/10 Tues 15/10 Thur 17/10 Fri  18/10     8-11. All four hours may not be used every Thursday.30              Final  exam  in  V  building 7 . These will be posted on the course web site.