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Process control

Electro/Digital
Latch flip-flop circuit
In previous lessons, we discussed the flip-flop circuit. In a normal flip-flop
circuit, the output state changes immediately after a change in input state.
In latch flip-flop circuits, the output of a circuit can change only if a clock signal
is present.
In this lesson, we will describe a number of different types of latch flip-flop
circuit designs.

Contents of the lesson


1

Latch circuit

D-latch

Flank-triggered D-latch

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Lesson
1. Latch circuit

- time-lock

In SR flip-flops, the output state changes immediately when the input state
changes. As this is often undesirable, a circuit was developed that also depends
on the presence of a clock signal. The output of this type of flip-flop can only
change when the clock signal is present. The clock signal acts as a sort of timelock for the flip-flop, hence the name latch. The clock signal can be supplied
using a combination of AND gates or OR gates.

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Figure 1
Latch circuit

- retaining a signal

In the circuit shown in figure 1, the set or reset signal will reach the input of the
SR flip-flop only if the clock signal is equal to one. The output signal Q can
therefore change only if the clock signal is equal to one. This latch enables the
retention of a signal on the output for an extended period even with changes
occurring at the inputs during that period.
Electronic components such as flip-flops tend to switch too fast for the
connected process equipment to be able to react in time. In practice, a
mechanical valve for instance needs a voltage for a duration of at least 0.1
second to be able to open at all. Should the valve be controlled by a flip-flop
circuit, the chances are it would not react at all. The output signal of the flip-flop
remains active for 10-6 second, and consequently the valve will no longer react
when the clock signal is zero. The time-sequence diagram shown in figure 2
clearly shows how the output reacts to the R and S signals with a clock signal C.
Question 1
Explain the name latch circuit.

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Figure 2
Time-sequence diagram of valve-control system
2

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2. D-latch
- forbidden
combination
- inverse
- Data

A latch circuit also allows the forbidden combination to be supplied to the


inputs. To prevent a forbidden combination, the R and S signals can be supplied
to the latch as each other's inverse values. In practice, this means that we bring
about the following with an invertor: R = S.
This input is called D (derived from Data), so the following applies:
D=S= R
The data signal placed on the input is transmitted to the output the moment the
clock signal (C) becomes equal to one.

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Figure 3
D-latch circuit

A separate symbol is used for the D-latch circuit, too. This symbol is shown in
figure 4.

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Figure 4
Symbol of D-latch

The functioning of the D-latch circuit is illustrated by the time-sequence


diagram shown in figure 5. The information carried by output Q can change only
when the clock signal is equal to one. The information supplied is retained if the
clock signal is equal to one.

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Figure 5
Time-sequence diagram of D-latch circuit
3

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Question 2
What is the function of the invertor in a D-latch?

3. Flank-triggered D-latch
- flank-triggered Dlatch

- flanks of the clock


pulse

In addition to the D-latch circuit mentioned, there is also a flank-triggered Dlatch. The flank-triggered D-latch differs from the D-latch mentioned above only
in the time when the clock signal is active. In the D-latch, the output is changed
if the clock signal is equal to one. In the flank-triggered D-latch, the input signal
will be transmitted to the output when the clock signal changes, i.e. the moment
the clock signal changes from 0 to 1 or from 1 to 0. Only at these moments,
which correspond to the flanks of the clock pulse, can the input signal be
transmitted to the output. As long as the clock remains in the 0 or 1 position, the
state of the flank-triggered latch cannot change.
There are two versions of the flank-triggered D-latch. One version reacts to the
positive flank, i.e. during the transition from 0 to 1. There is also a version that
reacts to the negative flank, i.e. the transition from 1 to 0. The D-latch used in
the digital simulation program is a positive flank-triggered D-latch. Figure 6
represents a time-sequence diagram of a positive flank-triggered D-latch. This
figure makes it clear that this circuit is active only on the 0-to-1 flank of the
clock pulse.
Question 3
Which two versions of the flank-triggered D-latch are there?

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Figure 6
Time-sequence diagram of a positive flank-triggered D-latch

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Summary
A latch circuit changes in reaction to the input signals only during the presence
of a clock signal. Normal flip-flop circuits on the other hand react directly to a
changing input signal.
To prevent a forbidden input combination, the R and S signals can be supplied to
the latch as each other's inverse values.
This input is called D (derived from Data), so the following applies:
D=S= R
For the D-latch circuit, a separate symbol is used, as shown in figure 4.
The flank-triggered D-latch differs from the D-latch mentioned above only in
the time when the clock signal is active. In the D-latch, the output is changed if
the clock signal is equal to one. In the flank-triggered D-latch, the input signal is
transmitted to the output when the clock signal changes.
There are two different versions of the flank-triggered D-latch:
- positive flank reacts during transition from 0 to 1;
- negative flank reacts during transition from 1 to 0.

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Test
Exercises
Do not send in your answers for correction
1.

Describe the difference between a D-latch and a flank-triggered D-latch.

2.

Describe the time-sequence diagram of a negative flank-triggered D-latch.

Answers to the questions in the lesson


1.

In the latch circuit, the output signal can change only during the presence of
the clock signal. The clock signal acts as a sort of time-lock for the flip-flop,
hence the name latch.

2.

To prevent a forbidden input combination, the R and S signals can be


supplied to the D-latch as each other's inverse values.
This input of the D-latch is called D (derived from Data) so the following
applies:
D=S= R

3.

The flank-triggered D-latch comes in two different versions:


positive flank reacts during transition from 0 to 1;
negative flank reacts during transition from 1 to 0.

Answers to the exercises


1.

The flank-triggered D-latch differs from the D-latch mentioned above only
in the time when the clock signal is active. In the D-latch, the output is
changed if the clock signal is equal to one. In the flank-triggered D-latch,
the input signal is transmitted to the output when the clock signal changes.

2.

Figure 9 shows the time-sequence diagram of a negative flank-triggered Dlatch. This figure shows that the circuit is active only on the 1-to-0 flank of
the clock pulse.