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A Fully Integrated Low-Power BPSK Demodulator

for Implantable Medical Devices
Yamu Hu, Student Member, IEEE, and Mohamad Sawan, Fellow, IEEE

AbstractDuring the past decades, research has progressed on

the biomedical implantable electronic devices that require power
and data communication through wireless inductive links. In this
paper, we present a fully integrated binary phase-shift keying
(BPSK) demodulator, which is based on a hard-limited COSTAS
loop topology, dedicated to such implantable medical devices. The
experimental results of the proposed demodulator show a data
transmission rate of 1.12 Mbps, less than 0.7 mW consumption
under a supply voltage of 1.8 V, and silicon area of 0.2 mm2 in the
Taiwan Semiconductor Manufacturing Company (TSMC) CMOS
0.18- m technology. The transmitter satisfies the requirement
of applications relative to high forward-transferring data rate,
such as cortical stimulation. Moreover, the employment of BPSK
demodulation along with a passive modulation method allows
full-duplex data communication between an external controller
and the implantable device, which may improve the controllability
and observability of the overall implanted system.
Index TermsBinary phase-shift keying (BPSK) demodulator,
biotelemetry, COSTAS loop, electronic implant, inductive link,
wireless data transmitter.
Fig. 1. Inductive link to transmit power/data.

I. INTRODUCTION

ITH the rapid development of microelectronics during

the last ten years, high performance implantable electronic devices (sensors and neuromuscular stimulators) play an
increasingly important role in modern medical treatments [1].
Inductive links have been widely used in functional electrical
stimulation (FES) [2][5] and neural signal recording (NSR)
applications [6][8] to provide power to the implantable device.
Meanwhile, the link is also employed as a media to transmit data
between the external controller and the implanted unit. Fig. 1
presents a block diagram of such a system using the inductive
link.
Generally, the external controller needs sending commands
and stimulation data to the implant. The desired transmission
rate is dependent on different applications, varied from a few
kilobits per second (kbps) (command data package) to several
megabits per second (Mbps) (stimulation data in visual prosthesis). On the other hand, the monitored data, such as nerve
signals, are required to be sent to the external controller from

Manuscript received February 1, 2005; revised August 1, 2005. This work

was supported by the Natural Sciences and Engineering Research Council of
Canada and the Canadian Research Chair on Smart Medical Devices. This paper
was recommended by Guest Editor T. S. Lande.
Y. Hu was with the Polystim Neurotechnologies Laboratory, Department of
Electrical Engineering, cole Polytechnique de Montral, Montral, QC H3C
3A7, Canada. He is now with Texas Instruments, Dallas, TX 75243 USA.
M. Sawan is with the Polystim Neurotechnologies Laboratory, Department of
Electrical Engineering, cole Polytechnique de Montral, Montral, QC H3C
3A7, Canada (e-mail: mohamad.sawan@polymtl.ca).
Digital Object Identifier 10.1109/TCSI.2005.858163

the implantable device in NSR applications. In the remaining

sections, we refer to the data transmission from the external
controller to the implant as downlink, and the data transmission
from the implant to the external controller as uplink. Realizing
bidirectional data transmission between the two parts has become a trend in state-of-the-art biotelemetry systems. This is because the backward information can serve for several purposes.
1) Improved controllability: Bidirectional data communication provides a means of in situ confirmation of system
status, which allows the external controller to make adjustment according to the implant status. This may also
improve the safety of the patient, prevent the overheating
of the system by monitoring the on-site temperature.
2) In-vivo measurement: For instance, with the knowledge
of programmed current, the end-of-phase voltage will provide a means of estimating the tissue complex impedance.
Also, electroneurogram recording technique [1] has been
proposed and used to enhance diseased bladder functions.
Furthermore, full-duplex transmission mode is desirable for
the reasons that it makes it possible to monitor and control the
implantable system in real-time. In addition, it simplifies the
protocol control circuitry and can increase the data transmission
speed by reducing the time of handshaking.
During the past ten years, few novel circuits and system
topologies on the inductive link have been reported [2][10].
Table I presents major data communication characteristics
of these main works. In [2], the authors reported a 100-electrode neurostimulation application-specific integrated circuit.

1057-7122/$20.00 2005 IEEE

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TABLE I
MAIN CHARACTERISTICS OF REPORTED INDUCTIVE LINK SYSTEM

Data of stimulation are delivered by a sequence of data,

which contains a series of packet bursts. Each packet burst
has a beginning and an end whereby fixed carrier frequency
pulses commence and cease, respectively. Each packet burst
is separated in time by a silent period or packet burst gap
wherein no pulses are present. The authors of [3] introduced a
neural-stimulus chip with telemetry unit for retinal prosthetic
device. The data are processed by a pulsewidth modulation circuit and subsequently modulated onto a radio-frequency carrier
using amplitude-shift keying (ASK) technique. The data rate
varies between 25 and 250 kbps with 1 to 10 MHz carrier frequency. Gudnason et al. [4] described a chip for a multichannel
neural stimulator for FES. The data signal is encoded by a pulse
amplitude modulation of the carrier with onoff keying (OOK).
The data rate has been set to 100 kbps with a carrier frequency
of 5 MHz. Smith et al. [5] described an integrated stimulator
and telemetry system with bidirectional data communication,
which is dedicated to the functional neuromuscular stimulation
(FNS) applications. Commands are transmitted into the implant
by means of OOK, and sampled data is sent out of the implant
using load-shift keying (LSK). This configuration is capable
of reliably transmitting data bytes at rates of 200 kbps with
a carrier frequency of 6.78 MHz. Akin et al. [6] reported a
fully integrated wireless multichannel neural recording system
using amplitude modulation. Data are encoded using a variable
pulse-width modulation technique with a data transmission rate
of 125 kbps at a carrier frequency of 4 MHz.
All of the above reported works employed ASK or OOK
to transmit data between the two parts of device due to their
simplicity. Some of them realized bidirectional communication
but only half duplex. The ASK modulation suffers from the
problems of relatively low data transmission rate and reduced
amount of transferred power to implants. Some works, which
used frequency-shift keying (FSK) [9] or phase-shift keying

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(PSK) [10] as the modulation method, were also reported.

Theoretically, the carrier using either one of the two modulation methods has constant amplitude, which may increase
the maximum amount of transferred power. And both modulation methods allow a full-duplex communication with LSK
modulation being used as the backward transmission method.
However, FSK modulation is only applicable on the wide-band
inductive link applications [9], which requires a low quality
factor of the resonant circuit. This leads to an inherently low
transfer efficiency of power.
In this paper, we mainly address the implementation of a
fully integrated low power binary phase-shift keying (BPSK)
demodulator, which is used as downlink data communication of
narrow-band inductive link systems. Low power consumption,
miniaturization, and reliability of the circuit are of our main concerns. This paper is organized as follows. In Section II, we first
introduce the characteristics of narrow-band inductive link and
phase-shift keying modulation. Then we describe the principle
of BPSK demodulator and our proposed circuit implementation
in Section III. Experimental results of the prototype chip and
conclusions are presented in the last sections.
II. DATA COMMUNICATION WITH NARROW-BAND
INDUCTIVE LINK
As shown in Fig. 1, the biotelemetry system consists of two
coils, one integrated in the implant, isolated in the human body,
and another put close but outside the body. Since the 1970s,
several works have been reported to address maximizing the
gain and power-transmission efficiency of these inductive links
[11][13]. They concluded that to have better power transfer efficiency, both sides of the link could be tuned at the same resonant frequency. In most cases the primary circuit is tuned in series to provide a low-impedance load to the driving transmitter.
On the other hand, the secondary is almost invariably a parallel
LC circuit to better drive a nonlinear rectifier load. Fig. 2(a) derepresents the
picts a simplified inductive link model, where
(this is equal to the output
resistance of the voltage source
resistance of the power amplifier),
represents the equivalent
ac resistance of load that depends on the configuration of the
represents the mutual inductance between the
rectifier, and
two coils of the link.
The transfer function (in Laplace domain) of the transcutaneous link can be derived from its two network equations [14],
as shown in (1) at the bottom of the page. The link behaves
as a narrow-band fourth-order bandpass filter due to the existence of the resonant circuitry. Fig. 2(b) presents the voltage
transfer function (magnitude and phase) at the secondary coil
under three different load resistances, with a source resistance
)
of 3 and coupling coefficient (defined as
of 0.07. It illustrates that the bandwidth of the link is extremely
narrow due to the high quality factor of the LC tank to increase

(1)

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frequency of 13.56 MHz. The spectrum of the modulated

carrier is the convolution of the carrier tone with the spectrum
of the data stream that contains high-order harmonics. To investigate aforementioned links effect on the BPSK demodulation,
Fig. 3(a) simultaneously gives out the spectrum of the received
carrier of the link. The carriers spectrum is bandpass shaped
by the virtue of narrow-band link, as presented in Fig. 2(b).
Although the datas high-order harmonics have been suppressed to a significant extent, the main lobe of signal tone is
not attenuated and input signal-to-noise ratio (SNR) is still high
enough to efficiently demodulate the received signal. Assuming
that the interference coupling from external world could be ignored, which is reasonable due to the characteristics of close
coupling of the inductive link, the noise sources of this data
transmission channel mainly come from the thermal noise of the
power amplifier and the primary and the secondary coils resistive impedances. Simulation in Cadence shows that the overall
in-band (from 10 to 20 MHz) root-mean-square (rms) noise is
6.7 mV with a source resistance of 3 and coil quality factor
of 100. As shown in Fig. 3(a), the main lobe of received signal
is not attenuated from the input signal, which is higher than 700
mV. Consequently, the input SNR of the BPSK demodulator is
higher than 40 dB. The theoretical error probability is calculated
by (2), as reported in [17], which gives a bit error rate (BER) of
less than 10 under SNR of 40 dB
Fig. 2. Typical inductive link. (a) Simplified schematic. (b) Magnitude and
phase transfer function. Rs = 3
, coupling coefficient k = 0:07, and resonant
frequency (fr) is 13.56 MHz.

the voltage/power transfer efficiency. This narrow band imposes

a challenge to design a bidirectional data transmission system,
as only one carrier frequency is available in such a system. In our
applications, a carrier with a frequency of 13.56 MHz is chosen
from the considerations of data transfer rate, power efficiency,
human safety, etc. A full-duplex bidirectional data communication system, which employs PSK method as the downlink and
utilizes LSK modulation as uplink data transmission method,
has been proposed in [15]. LSK, which is a passive modulation
method, has been reported in several papers [5], [16]. It utilizes
the property of inductive coupling where the impedance of the
primary coil reflects the effective secondary load. LSK modulation does not need the secondary carrier frequency, and its
implementation circuitry can be simple without using a power
amplifier, which is the most power consuming part of the transceiver circuit. Through some circuit techniques, we can realize
the full-duplex data communication by extracting the two directional data from the carriers amplitude and phase, respectively. In this paper, we will focus on the implementation of
the BPSK demodulator only, since the design of an implantable
device encounters more constraints and challenges than its external controller.
PSK is a modulation process whereby the input signals, a
binary pulse code modulation (PCM) waveform, shift the phase
of the output waveform to one of a fixed number of states.
BPSK modulation shifts the carriers phase between 0 and
180 . Fig. 3(a) presents the spectrum of the modulated signal
with a random bitstream at data rate of 1 Mbps and a carrier

(2)
where represents the function that denotes the area under the
tail of the Gaussian probability density function and
represents the SNR here. Note that the BPSK modulated carrier
still contains a great amount of energy at the carrier frequency,
as shown in Fig. 3(a). It is further amplified by the inductive
link to provide the power of the implantable system. This is
one critical advantage comparing with FSK method. In fact,
Fig. 3(b) presents the spectrum of the binary frequency-shift
keying (BFSK) modulated signal with a random bitstream at
data rate of 1 Mbps and a carrier frequency of 13.56 MHz. Since
no energy exists at the carrier frequency, which is the most efficient tone from the power-transferring viewpoint, all the power
has to be recovered from the data stream bins (12.56 and 14.56
MHz), which reduces the received power and deteriorates the
power efficiency to a great extent. Fig. 4(a) shows the received
power of the equivalent load resistance using BPSK and BFSK
modulations, respectively. Correspondingly, Fig. 4(b) gives the
power transfer efficiency, which is defined as a ratio between the
carriers power received from the secondary coil and modulated
signal power sending on the primary side, of these two methods.
It illustrates that using BPSK modulation is much more power
efficient than using the BFSK method under the narrow-band inductive link. This could be very important when power budget
is becoming a bottleneck in an implantable device.
The impact of coils movement and load impedance variation
may be of great concern. From (1), we know that the phase of
the received signal is a function of coupling coefficient, load
impedance. Fig. 5 shows the phase shift versus the coupling
coefficient from 0.05 to 0.09 under three equivalent resistive

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Fig. 3. Spectrum of the modulated and received carriers: (a) BPSK and (b) BFSK (32 768 points fast Fourier transform analysis with data recorded from the
simulation result under Cadence environment).

Fig. 5. Phase shift of received voltage at the secondary coil versus coupling
coefficient.

Fig. 4. Power transfer under different resistive loads with a full-wave rectifier,
primary carrier amplitude of 700 mV, Rs = 3
and coupling coefficient of
0.07. (a) Received power and (b) transfer efficiency.

loads. We could find that the overall phase ambiguity is 37 ,

which is much less than the phase difference (180 ) of BPSK.
It may cause a slight increment of BER. However, it is still
higher than using quaternary phase-shift keying (90 phase
difference).
III. PROPOSED BPSK DEMODULATOR
Since the received PSK modulated waveform is a suppressed
carrier in nature, coherent detection is required and the carrier
has to be recovered first. Several techniques, such as squaring
loop, COSTAS loop, and remodulator loop, have been proposed
to solve the problem [18]. Among them, the COSTAS loop is
the most often used technique due to its practical feasibility. It
consists of two parallel phase-locked-loops (PLL), where one
is called in-phase loop and the other is called quadrature-phase

(90-phase-shift) loop [18]. Their phase error outputs are multiplied to control the frequency of the oscillator. The square term
of the data stream makes the control signal onlyproportional
to the phase difference as the conventional PLL. In the locked
state, the output at the in-phase branch becomes the demodulated signal.
The main drawback of the conventional COSTAS loop BPSK
demodulators is their complexity. Normally, a four-quadrant
analog multiplier is adopted to realize the I/Q arm phase detector and the multiplier in the voltage-controlled oscillator
(VCO) branch. Demodulation is sensitive to the input operating
points of each block. Present BPSK demodulators are implemented mostly by digital technique, including multiplication,
filtering, phase shifting, and digital controlled oscillator, such
as HSP50210 manufactured by Harris. However, all digital
COSTAS loop demodulators suffer from high power consumption, which is intolerable for implantable applications.
Fig. 6 presents the block diagram of our proposed BPSK demodulator, which is inspired from digital PLLs. First, a comparator converts the received sinusoidal carrier to the square
waveform. This allows using two simple digital phase detectors in the demodulator arms. Although the analysis in [18] is

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Fig. 6. Block diagram of the proposed BPSK demodulator.

based on sinusoidal input signal, it can be extended into square

wave due to the fact that the low-pass loop filters will reject thehigh-order harmonics. In addition, another comparator is added
into the lower branch, which forms a hard-limited COSTAS
loop. It relaxes the requirement of the center multiplier, which
will be explained later. A fully differential architecture is extensively adopted everywhere to improve circuits reliability,
power-supply rejection ratio (PSRR), and noise immunity.
A. Phase Detector and Loop Filters
From the above analysis, we know that the key issues of
the BPSK demodulator are to generate a square term of data
stream in the control signal of VCO and to make it being only
proportional to the phase error. There are three main digital
phase detector categories available: exclusive-OR, J-K flip-flop,
and phase frequency detector (PFD). Among them, only exclusive-OR can be directly used here as the I/Q arm multipliers. It
can be illustrated from the following analysis. Considering the
effects of low-pass arm filter, Fig. 7(a) and (b) gives the outputs
of two arm phase detectors using exclusive-OR as
(3)
(4)
where
is a constant and denotes the phase detector gain.
Fig. 7(c) illustrates their multiplication (curve
), which is
quite similar to the output (
) using analog multipliers

as shown in (5). After introducing a comparator to the demodulators bottom branch, which is called a hard-limited COSTAS
loop [19], the phase detection output to VCO can be derived as
(5)
represents the signum function. Their waveforms are
where
presented in Fig. 7(d) and (e). It is important to note that the
overall loop gain is independent of its input signal amplitude
by using the digital phase detectors along with the hard-limited
technique. Furthermore, the overall phase-error output of hardlimited COSTAS loop has a larger linear range (from
2 to
2) than using the analog multiplier (only around ). These
features facilitate the stability analysis and the design of the
whole feedback loop. In addition, the phase detection range of
instead of
2 in
the hard-limited loop is enlarged twice to
the previous case. On the contrary, by using the same analytical
method, we could find that the other two digital phase detectors, J-K flip-flop and PFD, cannot be employed in this loop,
since their overall phase errors (I-branch phase error multiplied
by Q-branch phase error) are not locked at either in-phase or
quadrature state at all.
As the input carrier and the output of Q-branch have been converted into the binary form, a fully differential exclusive-OR as
well as a chopper style multiplier used in the central multiplier
can be simply realized by the same circuit based on transmission
gates (Fig. 8). The only difference between these two multipliers
is their input signal level. The input at pin
(Fig. 8)
could be either digital format (high or low) when using I/Q phase

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Fig. 7.

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Phase detection error (a) I-phase, (b) Q-phase, (c) overall phase error using XOR gates, (d) Q-phase, and (e) overall phase error with hard-limitation.

Fig. 8. Transmission gate-based multiplier.

detector or analog signal using central multiplier. Since this multiplier only consists of eight switch transistors, no static power
is consumed in it.
On the other hand, on-chip passive first-order lag filters are
chosen from the consideration of design simplicity and weak
power consumption. The value of , , and should be considered from the tradeoff of data transfer rate, damping factor,
and silicon area space. From the above analysis, we find that
the hard-limited COSTAS loop is analogous to a second-order
linear PLL using XOR as the phase detector. Its nature frequency
and damping factor are given as [18]
(6)
(7)
and
represent the gain of the phase detector
where
denotes the frequency-division
and VCO, respectively, and
ratio. For the design of PLL, damping factor has an important influence on the dynamic performance of the loop. Our
target is to set it at a value between 0.707 and 1 in order to
avoid oscillation and sluggish dynamic response. The nature fredetermines the loops lock-in time, which reflects the
quency

maximum data rate of the demodulator. Choosing a high nature

frequency may decrease the damping factor. Therefore, some
compromises should be considered to obtain an optimum performance. Another important characteristic is the loops lock
range, as written in (8), which dictates the maximum deviation
of center frequency of VCO
(8)
B. Fully Differential Comparator
The comparator squares up the received sinusoidal carrier,
which allows the implementation of the proposed BPSK demodulator in the classical digital PLL method. Fig. 9 presents the
comparator [21] used in our system. Transistors
construct a constantbias voltage/current generation circuit,
where rgw startup circuit is not shown in the figure. The biasing
loop current is produced by the gainsource voltage ( ) differand
divided by resistor
ence between the transistors
. One current sink (
and
) is put into the input stage to
limit current consumption of the comparator. Otherwise, the case
may occur where all transistors of the input stage are turned on
when the common-mode input voltage stays around threshold
voltage and a large amount of undesired power is consumed. As

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Fig. 9. Low power consumption fully differential comparator.

Fig. 10.

Circuit implementation of VCO.

the amplitude of received carrier can be higher than VDD (1.8 V)

to some extent, two input transistors ( and
) are designed to
work under 3.3 V, whose gate oxide thickness is enhanced. In addition, the input stage is protected by an off-chip shunt regulator,
which is not shown in the figure. The output stage consists of
and two digital buffers. Common-mode
transistors
feedback circuit is not needed here due to the employment of two
,
) and the
fully symmetric current mirrors (transistors
inherently nonlinear characteristic of the comparator.

C. VCO and Quadrature Signals Generator

Fig. 10 shows the schematic of the implemented CMOS
VCO, where labels BP, CP, and CN represent constant voltages
generated from a biasing circuit. The VCO mainly includes a
) cell.
relaxation oscillator [20] and a transconductance (
and
operate as switches, which are turned
Transistors
on and off in turn in accordance with voltage potentials of
their gate and source terminals. A linear transconductance cell,

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TABLE II
SIMULATED CURRENT CONSUMPTION OF PROPOSED DEMODULATOR

Fig. 11.

Simulated waveforms of the demodulator.

formed by transistors

and resistor , controls the

oscillators frequency. The frequency of oscillation is given by

Fig. 12.

Microphotograph of the proposed BPSK demodulator.

Fig. 13.

Measured oscillated frequency of the VCO.

(9)
where
represents the transconductance value and
deand
. Wide-swing
notes threshold voltage of transistors
current sources/sinks are widely used here to have a more precise branch current due to less variation of drainsource voltage
( ) of the mirror transistor, which improves the frequency precision. In addition, their enhanced output impedances increase
overall PSRR and common-mode rejection ratio of the oscillator. To facilitate investigating the proposed demodulator loop,
a continuous-mode tuning method is adopted to trim the center
frequency and VCO gain of the oscillator. Another transconductance cell (transistors
) converts trimming voltage
to a dc current injecting into the oscillator. As a consequence,
the center frequency can be trimmed bidirectionally through
and
. As illuschanging the differential voltage of pins
trated in (9), this VCOs gain mainly relies on the transconductance ( ), which can be tuned by varying biasing current of
cell. As shown in Fig. 10, a multiplexer formed by tranthe
sistors
and an inverter allow this VCO being able
to work in either normal mode (selecting BP) or tuning mode
(connecting with the gate of transistor
). An external current sink from a source measurement unit or a simple resistor
can be used to provide tuning current through pin Tin.
A quadrature pair of the oscillated signal can be simply fulfilled by a divide-by-two circuit in digital domain, which consists of only two D-flip-flops. Note that a reference with twice
the carrier frequency has to be generated in the VCO in this
circumstance. Although it leads to approximately 40 A more
current consumed in the VCO, the overall power increment remains very small.

Fig. 11 shows the simulated waveforms of the proposed

BPSK demodulator under Cadence environment with SpectreS
simulator, where the free-running frequency of VCO is set
0.5 MHz less than carrier frequency. The top three traces
(13) represent the input data, received carrier, and squared up
carrier, respectively. Note that the quadrature-phase error (trace
4) follows the input data transitions while in-phase error (trace
5) stays at around half of power rails (0.9 V). The simulated
overall power consumption is 652 W, which includes the
demodulator and front-end comparator. Table II presents the
consumed current in each subblock. It illustrates that most of
the power is consumed in the VCO and comparators. Since the

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Fig. 14.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 52, NO. 12, DECEMBER 2005

Testing setup of the proposed BPSK demodulator.

back gate of switch transistors is hooked to power rails, only a

few nanoampere leakage currents are expected in multipliers.

TABLE III
PROPOSED BPSK DEMODULATOR PERFORMANCE

IV. EXPERIMENTAL RESULTS

Five prototype chips of the proposed BPSK demodulator
have been fabricated in Taiwan Semiconductor Manufacturing
Company (TSMC) 0.18- m one-poly six-metal CMOS technology. An analog testing bus/multiplexer is introduced when
implementing the demodulator, which can cut the loop and
allow us to test the components separately. The microphotograph of the proposed BPSK demodulator is presented in
Fig. 12, which costs a total area of only 0.19 mm including
the testing components. The on-chip resistors are implemented
through unsalicided polysilicon, and the capacitors are fulfilled
using metalinsulatormetal (MIM) capacitor. Fig. 13 presents
the measured oscillation frequency of the integrated VCO
versus the control voltage as well as the simulation result. We
find that the measured oscillation frequencies are 30% less
than the simulated counterparts, while the variation of the
VCOs gain is in the range of 10%. The oscillators frequency
can be tuned from 19.5 to 21.5 MHz, rather than 27 MHz as
we designed. These variations mainly come from the process
variation when implementing the 0.6 pF on-chip capacitor
(Fig. 10) and the biasing resistor. This problem can be mitigated
at the expense of
through increasing the size of capacitor
more power consumption. All five prototype chips give us similar results. Fig. 14 presents the testing setup of the proposed
BPSK demodulator. As the frequency of the fabricated VCO
can not be tuned up to the twice of 13.56 MHz, to evaluate the
performance of our demodulator, the modulated carrier of 10
MHz is adopted and provided from the pattern generator of
logic analyzer (TLA715). Through a class-E power amplifier,
the amplified carrier is then transmitted to the secondary coil
through the link with the characteristics listed in Table III.
and
are introduced here to form a
The capacitors
is turned on. It is imporvoltage doubler when LSK switch
tant to note that the received carrier at node A will be affected
by the backward LSK modulation to some extent when full

Fig. 15.

Measured results of the prototype BPSK demodulator.

duplex communication mode is employed. The proposed BPSK

demodulator processed the received carrier from node B, and
the reference (not shown in figure) comes from the rectified
dc voltage. The loop is currently established at outside of the
chip, which employs commercially available components (XOR
and flip-flop) as the phase detector and quadrature clocks generator due to one internal connection problem. Fig. 15 presents
the measured BPSK data in, data out received carrier and
recovered clock, respectively. The received carrier is probed

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V. CONCLUSION

Fig. 16.

Block scheme of the proposed on-chip frequency tuning module.

with a circled wire instead of hooking to node B directly to

avoid parasitic capacitor effects on the whole detection circuit.
The measurement result indicates the maximum data rate the
proposed demodulator can reach is 1.12 Mbps. Note that the
amplitude of the received carrier is maintained around a stable
value when the BPSK data are transferred. The measured data
are recorded by using a digital oscilloscope (TDS7154) and
postprocessed further using MATLAB programming language.
The overall power consumption of the demodulator is only
610 W, where the system works under a supply voltage of
1.8 V. Table II summarizes the simulation result as well as the
obtained experimental result.
For future work, we know that the center frequency of the
VCO (Fig. 10) is highly reliant on to the static current of
transistors (M3 and M4) and the capacitance . The absolute
capacitance value is not well controlled in CMOS technologies
because they are affected by the process parameter tolerances.
Currently, the oscillation frequency is tuned through off-chip
components and only able to work under the carrier of 10
MHz due to the limited tunable range. Eventually, an on-chip
automatic frequency-tuning block is desired to initialize the
VCO center frequency inside the lock range of the demodulator and expected to work under the carrier frequency of
13.56 MHz. Fig. 16 presents a block diagram of the proposed
frequency tuning block. Its principle can be explained as
follows: the carrier without modulation is sent to the implant
first. As the conventional PLL, a phase-frequency detector
combined with a charge pump generates a tuning voltage
signal to control the VCO. When the lock frequency and
phases are detected, the final tuning voltage is restored into an
8-bit register through an on-chip programmable second-order
sigmadelta analog-to-digital converter (ADC). Once locked,
the PFD and charge pump will be turned off to save power. Also
the ADC is used for recording nerve signal and monitoring
system status [22]. Therefore, the overall power consumption
is not increased significantly due to the existence of this tuning
block. The data stored in the register will keep tuning the VCO
cell.
through a digital-to-analog converter (DAC) and a
The in-lock detection is fulfilled by connecting a low-pass filter
and an Schmitt trigger to the quadrature branch of the BPSK
demodulator [18].

We reported in this paper a novel fully integrated BPSK demodulator based in a hard-limited COSTA loop topology, which
features small integration area, low power consumption, high
data transmission rate, and easy implementation. The achieved
data transfer rate and power consumption are quite competitive
with the reported implantable ASK demodulators, and it is theoretically more power efficient comparing with FSK modulation
in narrow-band inductive link applications. Using PSK as the
downlink modulation method facilitates the design of a bidirectional data transmission in inductively coupled parts of medical devices. In addition, this BPSK demodulator is prone to be
modified as a QPSK demodulator, which is quite similar to the
BPSK except needing one more multiplier and an analog addition circuit. The data rate in QPSK modulation is expected to
double compared to BPSK at the expense of increasing the BER.
However, the BER can be improved by introducing some communication encoding techniques, such as differential phase-shift
keying . The proposed topology is intended for biomedical devices, ;it also can be used in other wireless applications.
ACKNOWLEDGMENT
The authors thank the Canadian Microelectronics Corporation for design tools and fabrication support.
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Yamu Hu (S03) received the B.S degree in electrical engineering from Huazhong University of
Science and Technology, Wuhan, China, in 1993
and the M.S degree in electronics engineering from
Ecole Polytechnique of Montreal, Montreal, QC,
Canada, in 2000, where he is currently pursuing the
Ph.D degree in electronics engineering.
His research interests include low-noise lowpower analog/mixed-signal ICs for biomedical
applications and RF front-end for wireless communications. He is with Texas Instruments, Dallas, TX.

Mohamad Sawan (S88M89SM96F04)

received the B.Sc. degree from Universit Laval,
Quebec, QC, Canada, in 1984 and the M.Sc. and
Ph.D. degrees from Universit de Sherbrooke, Sherbrooke, QC, Canada, in 1986 and 1990, respectively,
all in electrical engineering.
He conducted postdoctoratal training at McGill
University, Montreal, QC, Canada in 1991. He
joined Ecole Polytechnique de Montral in 1991,
where he is currently a Professor in microelectronics.
His scientific interests are the design and test of
mixed-signal (analog, digital, and RF) circuits and systems, digital and analog
signal processing, and modeling, design, integration, assembly, and validation
of advanced wirelessly powered and controlled monitoring and measurement
techniques. These topics are oriented toward biomedical implantable devices
and telecommunications applications. He holds the Canadian Research Chair
in Smart Medical Devices. He is leading the Microelectronics Strategic
Alliance of Quebec. He has published more than 300 papers in peer-reviewed
journals and conference proceedings. He holds six patents. He is Editor of the
Mixed-Signal Letters.
Dr. Sawan is a Fellow of the Canadian Academy of Engineering. He is
Founder of the Eastern Canadian IEEE Solid-State Circuits Society Chapter,
the International IEEE-NEWCAS conference, cofounder of the International
FES Society, and Founder of the Polystim neurotechnologies laboratory, Ecole
Polytechnique de Montreal. He is a Distinguished Lecturer for the IEEE
Circuits and Systems Society. He received the Barbara Turnbull 2003 Award
for spinal cord research, the Medal of Merit from the President of Lebanon,
and the Bombardier Medal of Merit from the French Canadian Association for
the Advancement of Sciences.