Digital Logic Design Tutotrial Sheetes
with solution.
Very Helpful for B.Tech Students .

© All Rights Reserved

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Digital Logic Design Tutotrial Sheetes
with solution.
Very Helpful for B.Tech Students .

© All Rights Reserved

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TUTORIAL SHEET

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, SPMIT,Allahabad

TUTORIAL SHEET -1

1.

(a) 757.2510

(b) 123.1710

[B] Convert to octal and then to decimal:

(a) 10111011.12 (b) 1101101.

2.

(a) 11100111.12 (b) 110100111.

3.

(a) Convert to hexadecimal 747.6410 round to digit past the hex point.

(b) Convert to decimal: ADE.B16

4.

(a) Construct a 6-2-2-1 weighted code for decimal digits. What number do 10010110 represent in their

code?

(b)What do you mean by boolean algebra? What is its use? Briefly discuss.

5.

(a) X(X+Y) = XY

(b) (X+Y) (X+Y) = X+ YZ

6.

(a) ABC+ (ABC)

(b) (AB + CD) (AB + DE)

7.

(b) WX + WYZ

[B] Draw a network to realize each of the following function using only one AND Gate and one OR Gate:F= WXYZ + VXYZ + UXYZ

Draw a network to realize the following function using two OR gates and two AND Gates.

F= (V+W+X) (V+X+Y) (V+Z)

8.

9.

10.

11.

State and prove the De- Morgans theorem? Explain with suitable circuit diagram?

Multiply out to obtain a sum of four terms:(A+B+D) (A+C) (A+B+D) (A+C+D) (A+B)

[A] Find F & G & simplify

A

Fi g. 11( a)

2

R

S

T

R

S

10

P

9

11

T

Fi g. 11( b)

13.

(b) Simplify the following expression using only the consensus theorem or its dual:- WXY+ WYZ +

WXZ + WYZ

14.

(A+B+D) (A+B+D) (B+C+D) (A+C) (A+C) (A+C+D)

= ACD + ACD + BCD

15. Which of the following statement are always true? Justify your answer

(i) if x(y+a) = x(y+b) then a=b

(ii) if a=b then x(y+a) = x(y+b)

16.

17.

18.

19.

(b) Show that ac + bc +ab = ab + bc +ac

Given F(A,B,C,D)=m(0,1,2,6,7,13,15).

Find the minterm expansion for F (both decimal & algebraic form).

Given F1 = M(0,4,5,6) and F2= M(0,3,4,6,7), find the maxterm expansion for F1F2.

State a general rule for finding the maxterm expansion F1F2 given the maxterm expansion of F1 and F2.

Prove your answer by using the general form of maxterm.

find the minimum sum of products for each function using K map.

F(a,b,c,d) = (1 , 3,5, 7,9,11)

20. Find the minterm sum of products for each function using a Karnaugh map.

f1 (a,b,c) = m1+m3+m4+m6.

TUTORIAL SHEET

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, SPMIT,Allahabad

TUTORIAL SHEET -2

1. Plot the following function on a Karnaugh map (Do not expand to minterm form before plotting)

F(A,B,C,D) = AB+CD+ABC+ABCD+ABCD

2. [A] Find the minimum sum of products expression for each function .

(a) f(a,b,c,d) = M (0,1,4,5,10,11,12). D(3,8,14)

(b) f(a,b,c,d) = M (1,2,3,4,9,15).

3. A switching network has two control inputs (C1 , C2 ) two data inputs (X1,X2) and one output (Z). The network

performs one of the logic operations AND, OR, EQU, or XOR (exclusive-OR) on the two data inputs.

The function performed depends on the control inputs:

C1 C2

Function performed by network

0

0

AND

0

1

OR

1

0

EQU

1

1

X-OR

(a) Derive a truth table for Z.

(b) Use a K-map to find a minimum AND-OR gate network to realize Z.

X

1

F1

4. (a) Find the minimum sum of product for F1(A,B,C,D)

4.

F2

(b) Find the minimum product of sum of F2 (A,B,C,D).

5. find all possible minterm sum of products expressions for each function

f(a,b,c)= M (2,3,4)

Find the minimum sum of product and minimum product of sum expression of each function.

4

7. f(A,B,C,D) = AB +ABC +ABD +ACD +ABD +ABCD

8. f(A,B,C,D) = M (0,2,10,11,12,14,15) d(5,7)

9. [A] (a) Find the Boolean function f simulated by the logic circuit.

1

2

A

3

1

2

1

2

F=(A.B) + (C.D)

10 (a) Buildup two different logic circuits to simulate the Boolean function f=(A+B).C

(b) Use only NAND gates to design a logic circuit to simulate the Boolean function f=A.(B+C).

11. Design a circuit to perform XOR logic using only NAND gate.

12. Design a logic circuit to implement the boolean function

f= A.B.C +ABC+BC

13. find the minimum multiple output two level OR-AND network to realize

f1=bd+ab+cd and f2= ad+bc +bd

14. find the minimum multiple output two level NAND-NAND network to realize

f1=m(3,6,7,11,13,14,15) and f2=m(3,4,6,11,12,13,14).

15. What is difference between PLA and ROM give suitable description.

16. What do you mean by PLD? How many types of PLD?

17. Find a minimum two level NOR gate network to realize f1 and f2 use as many common gates as possible

f1(a,b,c,d)= m(1,2,4,5,6,8,10,12,14)

f2(a,b,c,d) =m(2,4,6,8,10,11,12,14,15)

18. Realize f1 and f2 using PLA give table and internal connection diagram for the PLA from Q17.

19. The PLA below will be used to implement the following equations

X=ABD+A C +BC +CD

Y=AC+AD+CD

Z=CD+AC+AC+AD+ABD

Indicate the connections that will be made to program the PLA to implement then equations.

20 Describe an implementation of f=AB +CD using only NOR gates.

TUTORIAL SHEET

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, SPMIT,Allahabad

TUTORIAL SHEET -3

1. What do you mean by sequential circuit? What is the difference between sequential & combinational circuit?

2. [A] Explain the operation of given circuit?

14

12

A1

13

15

A2

Q'

fi g. 2( a)

[B] Show that the circuit of fig 2 (b). with S=R=0 is the same as that fig. 2 (a).

16

14

17

12

13

15

A2

Q'

fi g. 2( a)

3. Design clocked S-R FF using NAND gate and write the truth table.

4. Design Master slave J-K FF using NAND / NOR gate and write the truth table.

5. Design a T- FF using NOR gate / NAND gate and write the truth table.

6. Explain a general method for conversion from one type of FF to another type.

Convert the following given FF from one form to another form.

7. (a) S-R to J-K (b) S-R to D FF

8. (a) J-K to D FF (b) J-K to T FF.

9. What do you mean by debounce switch? Draw the circuit diagram and briefly explain its functions.

10. What do you mean by FF? What is the meant by race around condition in Flip-Flop?

11. What do you mean by level triggered FF? Differentiate between S-R and J-K Flip-Flop?

12. Write the count sequence of a 3-bit binary DOWN counter, Design a ripple counter with a control using FLIPFLOP for this sequence.

13. Design a 4 bit binary UP/DOWN ripple counter with a control for UP/DOWN counting.

14. Design the following ripple counters using FLIP-FLOP:- (a) Divide by 5

(b) Divide by 7

16. Draw the state diagram of a modulo 4 UP/DOWN counter, Design its circuit using J-K FLIP-FLOP.

17. Design a Synchronous BCD UP counter using minimum number of M-S J-K FLIP-FLOP and AND Gates.

18. [A] What is sequential logic circuit ?

[B] What is meant by the term register in a digital system?

19. What do you mean by counter? What is difference between Synchronous and Asynchronous Counter?

20.

21. What do you mean by the Schmitt trigger ? What is its use?

TUTORIAL SHEET

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, SPMIT,Allahabad

MUDULE 4

1. Add binary which is given below:

(a) 110, 101 (b) 1101, 1001, 101

write result in terms of binary, decimal & octal.

2. Use the 5420 to add 1101 and 0101.

3. Subtract in binary & write the result in binary, octal form.

(a) 1111 and 1011 (b) 10001001 and 1111010

4. Subtract in binary place a 1 over each column from which it was necessary to borrow and write the result in

binary, decimal

(a) 11001011 1110101 (b) 10010100 1001101

5. Add the binary and write the result in decimal, octal & hex form.

(a) 101101.100 and 11011.111 (b) 0.00101 and 1001.001

6. Add the binary and write the result in base 3 form?

(a) 1001.101 and 1001.111 (b)1010.101 and 10111.1101

7. Add the binary and write the result in base 5 form.

(a) 100111.1001 and 10111.101 (b) 11011.1011 and 101011.10

8. Add the hex number and write the result in binary, octal form

(a) 3EB and 47F (b) 9EC and 3BE

9. Add the hex number and write result in hex and binary ?

(a) 3EC.4F and 3BE.3A (b) 4BC and 4CB.3AC

10. Subtract hex number and write the result in decimal, binary form.

(a) E3F.3BA AB2.2EB16 (b) 39BA 23AB16

Multiply given data :11. (a) 11011 and 10112 (b) 100.111 and 111.0112

12. (a) 7374 and 64378

Divide given data :14. (a) 1011011 10102 (b) 11000011 10112

17. (a) 763255 338

19. . Design half adder with the help of general gates and universal gate and write the truth table.

20. Design full adder and full subtractor using universal gate and write the truth table.

TUTORIAL SHEET

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, SPMIT,Allahabad

MODULE 5

1. What is the application of FLIP-FLOP? Give the suitable description/

2. Design 3- bit register using FLIP-FLOP.

3. What do you mean by counter? And design 3 bit counter using FLIP- FLOP.

4. What do you mean by register? How many types of registers? Give the brief description.

5. Design and explain 5-bit Shift register (7496). Write the application of shift register.

6. What do you mean by bi-directional register? Design 4-bit bi-directional shift register.

7. What is the difference between ripple and synchronous counter?

8. What is the ripple counter? Design 3-bit binary Counter. In a 4-stage ripple counter, The propagation delay of a

FLIP-FLOP is 50ns, of the pulse width of the stoke is 30ns, find the maximum frequency at which the counter

operates reliably.

9. What do you mean by modulo-N counter? Design a divide by 6 counter using 7490.

10. What do you mean by synchronous counter? Design 3 bit synchronous counter using T-FF.

11. Design a 3-bit binary UP/DOWN counter with a direction control M, use J-K FLIP-FLOP.

12. Design a decade UP counter. Use J-K FLIP-FLOP.

13. Write the application of asynchronous sequential circuits.

14. What do you mean by cascading BCD counter?

15.Design clocked sequential circuit and write its application.

16. Design logic circuit using S-R latches for the transition table of initial total state 1, Q 1Q2X1X2=0000. Find the

total state sequence for an input sequence X1X2=00,01,11,10,00.

17. Design a mod-12 UP counter using 74193 IC.

18. A clocked synchronous sequential circuit using positive edge trigger D-FFs has an input X and an output Y. The

excitation equations are:D1 = Q1. X + Q1.Q0.X + Q1 Q0.X

D0= Q0 X + Q0X and the output equation is Y = Q1.Q0.X

(a) Draw its circuit diagram

(b) Obtain its state diagram.

`19.

20. Design a 4 bit binary UP/DOWN ripple Counter with a control for UP /DOWN Counting.

TUTORIAL SHEET

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, SPMIT,Allahabad

TUTORIAL SHEET -6

1. A particular logic family defines a LOW signal to be in the range 0.0-0.8 V and a HIGH signal to be the range

2.0-2.3V. Under a positive logic convention, indicate the logic value associated with each of the following

values (a) 0.0V (b) 3.0V

2. Discuss how a logic buffer amplifier is different from an audio amplifier?

3. What kind of transistors are used in CMOS gate? Draw an equivalent circuit for a CMOS inverter using a singlepole, double through relay?

4. Define fan-in and fan-out which one you are likely to have to calculate?

5. Draw a circuit diagram, function table, and logic symbol for a 3-input CMOS NOR gate?

6. Draw a circuit diagram, function table, and logic symbol for a 3-input CMOS NAND gate?

7. Draw switch modes for 2 input CMOS NOR gate?

8. Draw a circuit diagram, function table, and logic symbol for 2-input CMOS OR gate.

9. Name and draw the logic symbols of four input CMOS gates that each use 8 transistors.

10. Design 2-input X-OR gate with the help of CMOS.

11. Design 4 input AND gate using NMOS and PMOS.

12. Name the two components of CMOS logic gates delay. Which one is most affected by load capacitance?

13. Determine the RC time constant for each of the following resistor- capacitor combination:- (a) R= 100,

C=50pf (b) R=330 , C=150Pf

14. Compute the maximum fan out for each of the following cases of a TTL output driving multiple TTL inputs.

Also indicate how much excess driving capability is available in the Low or HIGH state for each case.

(a) 74LS driving &74LS (b) 74LS driving 74S

15. Which would you expect to be faster, a TTL AND gate or a TTL AND-OR INVERTER gate? Why?

16. Design a CMOS 3 input OR gate .and write the truth table?

17. Draw a circuit diagram, Functional table for a CMOS gate with two inputs A and B an output Z, where Z=1 if

A=0 and B=1 and Z=0.

18. What is difference between TTL and CMOS logic gates.

19. Design 2 input AND gate and 2 input OR gate using TTL system.

20. Design half adder using CMOS logic ?

10

TUTORIAL SHEET -7

1. Design a 5-bit comparator using a single 7485 and one gate.

2. Setup a single 7-segment LED display using 7447 BCD to 7-segment decoder/driver.

3. Design a 4 bit 7- segment LED display system with leading zero blanking.

4. Design a 32:1 multiplexer using two 16:1 multiplexer ICs

5. Design a full adder using 8:1 multiplexer ICs. Compare the ICs package count with the NAND-NAND

realization

6. Design 1:20 demultiplexer using BCD to decimal decoder.

7. Implement the following multi-output combinational logic circuit using a 4 to 16 line decoder.

F1 = m(1,2,4,7,8,11,12,13)

F2 = m(2,3,9,11)

F3 = m(10,12,13,14)

F4 = m(2,4,8)

8. Design a hexadecimal to binary encoder using 74148 encoders and 74157 multiplexer.

9. What is the use of liquid crystal displays? Give the suitable example in terms of BCD.

10. what do you mean by encoder? What is the efficient use of priority encoders.

11. What do you mean by semiconductor memory? What is the memory organization and operation.

12. If a memory of size 32 words. Find the binary address of each location.

13. For the memory timing of table 13.1 Find the maximum rate (words/second) at which (a) Data can be stored,

and (b) Data can be read

Table 13.1

Parameter

Time

tWC

200

tWR

120

tRC

200.

14. Obtain a 16*8 memory using 16*4 memory ICs.

15. What do you mean by ROM? Build up the 16 bit ROM array with the help of decoder and diodes.

16. Write the Five difference between MOS RAM and Bipolar RAMs.

17. For a memory with M words storage, find the number of pins required for addressing and the address range in

binary format for each of the following cases.

(a) M=4 (b) M = 16 (c) M = 256 (d) 1024 = 1K

18. (a) What do you mean by static RAM and dynamic RAM.?

19. What is the role of dynamic shift resistor? Explain in terms of MOS technology? Explain two phase shift

register.

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