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2014 Ninth International Conference on Ecological Vehicles and Renewable Energies (EVER)

Analysis of Synchronous and Stationary Reference

Frame Control Strategies to Fulfill LVRT Requirements
in Wind Energy Conversion Systems
Matas Daz

Roberto Crdenas

University of Chile
Av. Tupper #2007
Santiago, PC PC 8370451 , Chile
AbstractIn order to avoid stability problems, LVRT
requirements (Low Voltage Ride Through) demand Wind
Energy Conversion Systems (WECS) to remain connected to the
grid in the presence of grid voltages dips. Because 88% of the
grid failures are asymmetrical, positive and negative sequence
components have to be controlled to fulfill LVRT requirements.
This paper present a comparison between synchronous and
stationary reference frame control strategies for an active frontend converter of a grid connected WECS working under grid
fault conditions. The mathematical analysis and design
procedure of both control system are presented in this work.
Experimental results obtained from a 3kW prototype are fully
discussed in this paper. The experimental implementation is
realized using a novel implementation of a voltage sag generator
which is based on a 3x4 Matrix Converter

University of Chile
Av. Tupper #2007
Santiago, PC PC 8370451 , Chile

To support voltage regulation in the power system. This

is accomplished through the consumption/injection of
reactive power by the grid side converter (see Fig. 3).
Typically only 12% of the grid-faults are symmetrical;
therefore, LVRT control system has to be able to deal with
positive and negative sequence currents and voltages. Several
Control systems for LVRT operation have already been

Index TermsLow Voltage Ride Through, Resonant

Controllers, Wind Energy Conversion Systems, Voltage Sag


ENERGY has become one of the industries with

the greatest and fastest growth in the renewable energy
sector [1]. The wind energy production capacity for the whole
world in 2012 was 282-GW [1]. Moreover, the penetration of
wind energy is steadily increasing. A good example is Spain,
where the average wind energy penetration has been 11%,
13.8%, and 16% in 2008, 2009, and 2010, respectively [x]
Therefore, some rather strict grid codes are enforced in
countries with relatively high penetration of wind energy, in
order to regulate the connection of large wind energy parks to
generation and transmission systems. In these grid-codes,
Low-Voltage Ride-Through (LVRT) requirements demand
wind-power plants to remain connected in the presence of
grid-voltage dips, contributing to keep grid voltage and
frequency stable. According with [2], [3], [4], in the presence
of a grid-voltage dip, the requirements of the LVRT control
strategy are:
To maintain the WECS connected to the grid, when the
line voltage is inside the boundaries specified in Fig.




Fig. 1. LVRT Requirements of the Spanish grid code. (a) Limit of the grid
voltage dip. (b) Demanded Reactive Current in function of grid-voltage dip.

presented in [5], [6], [7], [8]. In most of these papers the

controllers are based on revolving synchronous rotating d-q
axe where the negative and positive sequences are transformed

into dc signals and controlled using standard PI regulators.

Resonant controllers (RC) are well suited to manage positive
and negative sequence components of grid voltage [9], [10],
but no attention has been paid to stationary axis based control
systems under grid fault condition, in order to study WECS
LVRT requirements fulfillment.
This paper is focused on the comparison of synchronous
and stationary reference frame based control strategies to
fulfill the LVRT requirements for a system similar to Fig.
1(a). The system is composed of a wind turbine connected to
the grid through a low voltage two level Back to Back
converter. Low voltage two-level voltage-source converters
are the most used topology in WECS [11], [12], [13], [14]. In
this work it is assumed that the dc-link voltage is fairly
constant, both in steady state and under grid fault conditions
[2]. Therefore, grid-side and generator-side operations are
decoupled and only the control of the grid-side converter is

extraction is included in some advanced 3-phase PLL

structures, such as the 3-phase enhanced PLL (EPLL), double
second order integrator PLL (DSOGI-PLL), decoupled double
synchronous reference frame PLL (DDSRF-PLL), delayed
signal cancellation PLL (DSC-PLL) [20].

Fig. 3. Delay Signal Cancellation Method.

Delayed-signal-cancellation (DSC) is probably the best

suited method to separate sequences [21], [22]. This method
presents an intrinsic delay of T/4 and is described in the Fig. 3.
Regarding DSC, the PLL is employed to synchronize the
active Front-End converter to positive sequence of the grid
voltage at the Point of Common Coupling (PCC) [23], [24]
and [25].
Fig. 2. (a) Wind generator connected to the grid through a Back-to-Back
converter. (b) Grid-Connected Front-End Converter.


When a grid-voltage dip appears, the power injected to the
grid is decreased as a function of the voltage reduction,
therefore is not possible to supply to the grid all the power
produced by the machine. An active power surplus is stored in
the dc-link, resulting in an unacceptable dc-link voltage
increase that can be dangerous to the Back-to-Back converter.
Furthermore, the unbalance between the power generated and
the power supplied to the grid induces an increase in the speed
of the generator due to the mismatch between the mechanical
input power and electrical output power [2], [15], [16]. To
avoid this, Back-to-Back power converters are usually
equipped with a dc-link-voltage limiter unit (Crow-Bar,
Braking Chopper) [13], [14]. Therefore, generator side
converter and/or dc-link Crow Bar regulate the active power
surplus through grid-voltage dips, and the assumption of
decoupled generator-grid side converter is realistic [2], [17].
For asymmetrical grid-voltage dip conditions, a separation
sequence method is required to guarantees correct grid
frequency detection due to the second harmonics produced by
the negative sequence is reflected in the grid-frequency
estimation [18], [19].
To improve the performance of the PLL, positive sequence


The apparent power at grid terminal, calculated considering
three-leg unbalanced system with positive -and negativesequence components, is show in (7):



The superscripts (c), (p), and (n) are used to denote the
complex conjugate of the current vector, positive-sequence
component and negative-sequence component, respectively.
Developing the previous equation and separating real and
imaginary parts:

are the grid average active and reactive power.
Furthermore, and as it is well known, an unbalanced gridvoltage dip produces double frequency components in both
active power as reactive power, represented by
A. Synchronous Reference Frame Current Reference
According to [26], (11)-(12) could be expressed in function
of sequence components voltages/currents in d-q frame as






is the average active power dissipated in the
are the double frequency active power
It is also important to note that the system described by
(11)-(16) has four degrees of freedom (
) to
control six variables (
. In this
case, reactive power oscillations (
) are not
controlled again.
Two different current references methods are presented.
The first one, considers that the Front-End converter supplies
the oscillating active power to the filter, which results in zero
oscillating active power components on the grid side, i.e.


The system described by (4) - (9) has four degrees of

freedom (
) to control six variables (
. Therefore it is necessary to
make a choice of variables according to the control objectives.
Mainly, the reference currents are setting to regulate average
active and reactive power
and to eliminate the
double frequency oscillations in the active power (
Reactive power oscillations (
) are not controlled in
any case. Therefore, it is possible to write (4)-(7) in matrix

[ ]


B. Stationary Reference Frame Current Reference

Follow the same procedure, it is possible to demonstrate
that (2)-(3) can be represented by sequence component
voltages/currents in the natural frame:

[ ]


In the second case, the oscillating powers flow from the grid
into the filter, therefore oscillating active power components
are regulated to zero at the Front-End terminals,




This strategy is based in [6], [8]. Implementations for

LVRT fulfillment can be found in recent literature [27], [28]
and [29]. Positive and negative-sequence components are
regulated by independent rotational frame PI controllers.
Positive sequence current controller rotates
, that
correspond to the angle of the positive sequence voltage
component, founded by DSC-PLL. Negative sequence
current controller rotates with -
. A schematic of the d-q
control is represented in Fig. 4. Proportional Integral (PI)
controllers are used since they have correct behavior
controlling dc variables.
For improving the performance of the PI controller, crosscoupling terms and voltage feedforward are considering.

The apparent power at Front-End converter terminal follows
the same structure than (2) and (3), and the next expression
gives the power balance at the Front-End terminals (see Fig.
is the apparent power dissipated in the filter. It contains
average active and reactive power terms and cosine and sine
component oscillating with double grid frequency. The active
powers dissipated in the filter are obtained from [21], [27].


[ ]




Mainly, all strategies used in LVRT are based on
conventional d-q frame control systems explained in previous
section. Instead synchronous reference frame, the use of
stationary reference frame current controllers based on RC is
presented and development in this section.

Positive Sequence Current Controller





Negative Sequence Current Controller













Fig.4: Synchronous Reference Frame Control Strategy.

A RC have a couple of purely imaginary poles, with a

resonant frequency of
, found by the DSC-PLL. In the zplane, a RC controller has the follow transfer function [9],


) (
) (



Where: represents the distance between the pole and zero;

represent the sampling time;
is the controller gain.
A schematic of the proposed control is represented in Fig. 5
Positive and negative-sequence components are regulated by
the same RC. Each RC regulate line current get the current
reference calculated according to the method explain in
previous section. In this strategy, line current and voltages are
measured and trigonometric functions required to transform
from - to d-q coordinates (and vice versa) are not used for
the implementation.
RCs are designed using root locus in the z-plane. The
controllers should have an appropriate dynamic response
during grid-voltage dips, therefore, a second order lead lag
network is added for improvement of dynamic behavior [10].
The expression for the controller considering RC and lead lag
network is presented in (24):
The controller presented in (25) has been designed
=500s, closed loop poles damping
coefficientof 0.35,
=100 rads-1, =5
, =0.5 . The
root locus of the proposed control system is shown in Fig. 7:

Fig.5: Stationary Reference Frame Control Strategy

If the frequency at the PCC is proportioned for the

DSC-PLL, (25) represents a Self Tuning Discrete Resonant
Controller that can be easily implemented in a digital signal
The experimental system attempts to emulate the WECS
presented in Fig. 1(b) through the implementation of a low
power grid-connected Front-End converter. The SVM
algorithm, d-q based controllers, RC and all control structures
were implemented using a DSP based board and a FPGA to
generate signal IGBT drivers, IGBTs dead time, hardware
protection. The DSP board used in this application is based
on a TMS320C67 processor. For data acquisition purposes a
board with ten analogue to digital channels and 1conversion time is interfaced to DSP.

Open-Loop Bode for (6)

Root Locus for (6)

0.1 3.77e3


Zoom Root Locus for (6)









-200 G.M.: 3.33 dB


Freq: 8.35e+003 rad/s

Stable loop















-400 P.M.: 41.6 deg




Phase (deg)

Imag Axis


Magnitude (dB)



Freq: 6.8e+003 rad/s











Real Axis





Fig.6: Root locus for controller shown in (25).

A 3-kW grid-connected two-level Front-End converter is

used. The switching frequency is set to 2-kHz. Discrete RCs
and PI regulators have been calculated for 500-us sample time.
Three Hall-Effect voltage transducers are used to measure the
grid and dc-link voltages. Also, two Hall-Effect current
transducers are used to measure the grid currents. The FrontEnd converter is connected to the grid using a first order filter
of 20-mH 0.5-.
The grid-voltage dips have been produced a using a novel
3-kVA Matrix Converter Voltage Sag Generator, implemented
on a DSP board based on a high performance TI TMS320C67
processor, capable of a performance of 1350MFLOPS. For
data acquisition purposes an external board, with ten Analogue
to Digital (ADC) channels of 14bits, 1-s conversion time
each, is interfaced to the DSP.


This section presents experimental results for the system
shown in Fig.7. This Experimental Rig has been tested under
grid-voltage dip type B and C conditions [30]. Different tests
are carried out to validate the proposal strategy and to
compare it with the traditional d-q control scheme presented
in Fig.4. In all the cases, active power, line current and
reactive power responses are presented. The sag conditions
have duration of 140-ms and are produced by the Matrix
Converter based VSG. In state steady, the voltage in the PCC
is controlled to 110-V (rms value), the active power is set to
1-kW and the reactive power reference is controlled to 0kVA, in order to work with unitary power factor.
Test 1: 35% Grid-voltage dip type B.
Fig. 8 shows that Syn-RFC strategy is able to keep the
control through the grid-voltage dip. There is not presence of
double-frequency oscillations in active power (calculations
presented in (22) are also valid for synchronous reference
frame), but reactive power presents double frequency
oscillations that flows between the grid and the filter. At the
fault time appearance, the active power delivered to the grid
is 0-kW, and the Front-End starts to support to the grid
voltage through reactive power injection. When the fault is
over, the systems come back to state steady references.

Fig. 7. Experimental System.


Frequency (rad/s)

The same behaviour is observed in waveforms presented in

Fig.9. In this case, St-RFC strategy is utilised. During the
grid-voltage sag condition, the active power delivered to the
grid is 0-kW and the Front-End to support to the grid voltage
through reactive power injection. For both strategies, line
currents are slightly distorted and unbalance during the sag,
mainly due to the control objective is to regulate the power
and not the current.

Fig. 8: Syn-RFC responses for 50% Grid-Voltage Dip Type B. Up: Grid
Voltage. Medium: Grid Currents. Lower: Active and Reactive Power.

Fig.9: St-RFC responses for 50% Grid-Voltage Dip Type B. Up: Grid
Voltage. Medium: Grid Currents. Lower: Active and Reactive Power.

Fig. 10: Syn-RFC responses for 30% Grid-Voltage Dip Type C. Up: Grid
Voltage. Medium: Grid Currents. Lower: Active and Reactive Power.

Fig. 11: St-RFC responses for 30% Grid-Voltage Dip Type C. Up: Grid
Voltage. Medium: Grid Currents. Lower: Active and Reactive Power.

The responses using Syn-RFC are presented in Fig. 10. In

this case, a grid-voltage dip type C is tested. At the beginning
of the sag, phases A and C drop from 110
to the 35
In order to fulfil LVRT, the reference to reactive power
injection through the grid-voltage dip is 0.5 kVA.

However, when a fault appears, inaccurate values are feeding

to the control systems during
of the period. An amplified
view of the line current is shown in Fig.12.

Fig.11 presents the performance of St-RFC to the same

grid-voltage sag condition. Both strategies to allow grid
voltage support by reactive injection while the grid-voltage
dip is present. However, St-RFC presents slightly better
dynamic behaviour. At the appearance/clearance fault time using Syn-RFC- line current reaches 14 A, almost 3 times the
rated value. With St-RFC line current overshoot is lower,
reaching 9 A at the clearance fault time. An amplified view of
the line current is presented in Fig.13.
The time required by the DSC method to separate the
positive and negative sequences is very short, and it is
included within the sampling time (500 us) of the DSP
controller. Hence, this calculation time does not affect the
control dynamics.

Fig. 12: St-RFC responses for 30% Grid-Voltage Dip Type C. Left: Current
response at fault appearance time. Right: Current response at fault clearance

A comparison between Syn-RFC and a novel control
strategy, dealing with sequence components under unbalanced
voltage conditions, have been presented in this paper.
Proposed control strategy (St-RFC) is based on the use of
Resonant Controllers to regulate line currents in stationary
frame and is able to fulfill LVRT requirements.
According to experimental results, both strategies present
correct performance under unbalance grid-voltage conditions.
This fault conditions have been generated by a Matrix
Converter based VSG. In all the cases, the voltage sags
generated do not present peaks, transient effects or low
reliability. Therefore, the good performance of the novel VSG
has been ratified to test LVRT capability in grid-connected
Syn-RFC and St-RFC strategies are able to keep the system
grid-connected and to support grid-voltage through reactive
power injection when grid-voltage sag appears. Therefore,
both strategies meet LVRT requirements. However, St-RFC
strategy has slightly better dynamic behavior. St-RFC is more
stable and faster than Syn-RFC, mainly due to the lead lead
network, added to the RC in order to increase the dynamic
behaviour and stability. Also, St-RFC is simpler than SynRFC. A single RC could be used to regulate the positive and
negative sequence current and no transform from d-q to -
are needed. Additionally, for LVRT control, orientation along
any of the voltage or current vectors is not required and a PLL
is implemented only to obtain the grid-frequency which is
used to tune the resonant controller.
DSC presents a delay of T/4, which does not affect under
steady-state operation, but makes an inexact sequence
separation during the rts 5-ms (T=20-ms) after the
appearance of any grid-voltage dip. During this 5-ms,
inaccurate values are fed back to the control system. The
result of these inaccuracies can be observed in all responses
(currents and power), and explain the presence of non-desired
values during the 5-ms after at the appearance and clearance
fault time. Despite of the inaccuracies produced by DSC
method and the Voltage Sag Generator System, the results
obtained are acceptable for all the tests.











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