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B.Tech CSE C3/C4 (Sem. - 3 )

DIGITAL CIRCUITS & LOGIC DESIGN (BTCS-303)

rd

Time: 03 Hours

Instruction to Candidates:

1) Section - A is Compulsory.

2) Attempt any four questions from Section - B.

3) Attempt any two questions from Section - C.

Maximum Marks: 60

Section -A

Q1.)

(110001)2 - (101111)2

How many OR gates are required for Y= AB+DE+F. Identify with the Logic circuit.

Define Encoder.

(FFFF) 16 to (?)8

11001100

ii.) 00111100

(145.55) 10 to (?)2

Section-B

=0

(A+B) (A+

)C+

(B+

)+

B + ABC = C (A+B) +

)

Q3.) Write short note on a) Excess-3 code b) 9s and 10s Complement with example.

Q4.) Obtain min & max term

Y (A.B.C) = m (0,2,4,6,8,9,12)

Y (A,B,C) = M (0,2,4,6)

(B+

Q6) Describe full subtractor with k- map and logic circuit implementation.

Section-C

Q7.) Design octal to binary encoder with functional block diagram.

Q8.) What are half adder & Full adder? Discuss in detail. Also design 4 bit parallel adder.

Q9.) Reduce the following equations using k-map.

F(A,B,C,D) = m ( 0, 2, 4, 5, 7, 9, 10, 11, 12, 14, 15)

+A

+ ABC

C.

Section A

A1)

a.

De-Morgan's theorem states that (i) Compliment of sum of two or more variables is equal to the product of compliment of

variables.

(ii) Compliment of product of two or more variables is equal to the sum of compliment of

variables.

-----------------------------------------------------------------------------------------------------------------------------------------

b.

(i) (110001)2 - (101111)2

110001

- 101111

--------------------------

000010

10101010

- 00011111

---------------0 10001011

-----------------------------------------------------------------------------------------------------------------------------------------

c.

S.No.

Combinational Circuit

Sequential Circuit

1.

It contains no memory

elements

It contains memory

elements

2.

outputs are determined

solely by the present

values of its inputs

outputs are determined

by the present value of

its inputs and its past

state

3.

by the set of output

functions

by the set of nextstate(memory) functions

and the set of output

functions

-----------------------------------------------------------------------------------------------------------------------------------------

d.

Analog

Signal

Digital

Analog signal is a

represents physical

digital modulation.

measurements.

Waves

Representation

Example

Uses discrete or

values to represent

discontinuous values to

information

represent information

electronic devices.

devices.

Technology

numbers and records

them.

e.

Hence, Only 1 OR Gate will be used.

f.

L.H.S.

(A+B) (B+A)

A.B + A.A + B.B + B.A

A.B. + A + B + A.B

A ( B+1) + B ( 1 + A )

A.1+B.1

A+B

L.H.S = R.H.S

Hence Proved.

g.

Encoder is a combinational circuit used to convert binary information from 2n inputs to n

outputs. It is a device used to change data into specific code. It is used for purpose like

standardization , security, speed or saving space by shrinking size.

Eg : Priority encoder, decimal to BCD encoder etc.

h.

i) (FFFF) 16 to (?)8

(FFFF)16 to Binary --> 1111 1111 1111 1111

Now, making pair in 3 bits ..

001 111 111 111 111 111

Therefore, (FFFF) 16 to ( 1 7 7 7 7 7 )8

Redix = 2 , therefore, multiplying left side with 20 , 21 and so on... and right side with 2-1 , 2-2

and so on.

1x8 + 1x4 + 1x2 + 1x1 . 1x0.5 + 1x0.25 + 1x0.125

15.875

(1111.111)2 to (15.875)10

i)

i) (145.55) 10 to (?)2

Dividing the number by Redix ( ie : 2)

2

145

72

36

18

.55 x 2 = 1.1

.10 x 2 = 0.2

.20 x 2 = 0.4

1

0

0

(145.55) 10 to (10010001.100)2

Dividing the number by Redix ( ie : 8)

735

91

11

(735)10 to (1337)8

Section B

A2)

A3)

i) Excess-3 code is an example of unweighted code. Excess-3 equivalent of a

decimal number is obtained by adding 3 and then converting it to a binary

format. For instance to find excess-3 representation of decimal number 4,

first 3 is added to 4 to get 7 and then binary equivalent of 7 i.e. 0111 forms

the excess-3 equivalent.

Excess-3 code is also known as self complimenting code or reflective code,

as 1s compliment of any number (0-9) is available within these 10 numbers.

For example 1s complement of 9 (1100) is 0011.

ii)

The nines' complement of a decimal digit is the number that must be added

to it to produce 9; the complement of 3 is 6, the complement of 7 is 2, and

so on, see table. To form the nines' complement of a larger number, each

digit is replaced by its nines' complement.

10's complement, it is relatively easy to find out the 10's complement after

finding out the 9,s complement of that number. We have to add 1 with the

9,s complement of any number to obtain the desired 10's complement of

that number. Or if we want to find out the 10's complement directly, we can

do it by following the following formula, (10n - number), where n = number

of digits in the number. An example is given below to illustrate the concept of

obtaining 10s complement.

Let us take a decimal number 456, 9's complement of this number will be

-----------------------------------------------------------------------------------------------------------------------------------------

A4)

Truth Table

A5)

NAND and NOR Gates are called Universal Gates because all the other gates can be

created by using these gates

Here the same input is applied to the both inputs of a NAND Gate

According to NAND Gate If A and B are two inputs than output equation will be

(A.B)

For this case :

= (X.X)

= X

2. NAND Gate to AND Gate Convertion

For this case x and y are the two inputs to a NAND gate and the output of the First

NAND gate goes again to an another NAND gates inputs.

=>

=>

=>

=>

s1 = (X.Y)

s2 = (s1.s1) = s1

s2 = ((X.Y))

X.Y

According to diagram

s1 = (X.X) = X

s2 = (Y.Y) = Y

s3= (s1.s2) = (X.Y)

=> (X) + (Y)

=> X+Y

4. NAND Gate to NOR Gate Convertion

According to diagram

s1 = (X.X) = X

s2 = (Y.Y) = Y

s3= (s1.s2) = (X.Y)

=> (X) + (Y)

=> X+Y

s4 = (s3.s3) = s3

=> (X + Y)

-----------------------------------------------------------------------------------------------------------------------------------------

X

0

0

0

0

1

1

1

1

Y

0

0

1

1

0

0

1

0

BIN

Diff(D)

0

0

1

1

0

1

1

0

0

1

1

0

0

0

1

1

Truth Table For Full Subtractor

Borrow(B)

0

1

1

1

0

0

0

1

From above table we can draw the Kmap as shown below for "difference" and

"borrow".

D = X'Y'Bin + X'YBin' + XY'Bin' + XYBin

= (X'Y' + XY)Bin + (X'Y + XY')Bin'

= (X

=X

Y)'Bin + (X

Y

Y)Bin'

Bin

Section C

A7)

Octal To Binary Encoder

An encoder has 2n or fewer input lines, only one of which is in the 1 state

at a particular time and an n-bit code is generated on n output lines

an encoder is a circuit in which output lines generate the binary code

corresponding to the input value.

3

0

From the truth table, the outputs can be expressed by following Boolean

Function.

Y =D +D +D +D

Y =D +D +D +D

Y =D +D +D +D

Note: Above boolean functions are formed by ORing all the input lines for

which output is 1. For instance Y is 1 for D , D , D , D input lines.

0

A8)

bits. It has two inputs and two outputs. The two I/Ps are the two 1-bit

numbers A and B designated as augend and addend bits. The two O/Ps

are the sum S of A and B and the carry bit, denoted by C.

Truth Table of a half adder can be derived by performing binary addition

of augend and addend bits as follows:

S = AB + AB = A B

C = AB

A Half Adder circuit can be implemented using AND & OR logic gates or by

using XOR & AND logic gates. Both these implementations are shown

below:

Since NAND is considered as Universal Logic Gate which means that all

other logic gates can be derived from it, below is the implementation of

a Half Adder circuit using NAND logic gate:

bits. It consists of three inputs and two ouputs. Two of the inputs denoted

by A and B are augend and addend bits that are to be added, & third input

denoted by C represents the carry bit from the previous lower significant

i

position. The two O/Ps are the sum S of A and B and the carry bit,

denoted by C .

o

C

S=CAB

i

C = AB + (A B) C

o

A full adder circuit can be realized using half adder circuits as shown

below:

Using OR, XOR and AND logic gates, a full adder circuit can be

implemented as below:

A9)

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