WB SoC Top Level Coverage Model Testplan

Section Title
1
Initialization
1.1
Firmware Source

1.2

Power default Cfg

1.3

Clock default Cfg

2
2.1
2.1.1

Arbitraion Cfg
Static Fixed Priority
Priority Setting

2.1.2
2.1.3
2.1.4

Fixed Priority
Higher Wins
Equal Priority

2.2
2.2.1
2.2.2

TDM/RoundRobin
Slot Reservation
Last Master Granted

2.2.3

Time Slot Variation

2.2.4
2.2.5

Multi Slot Transactions

Arbitration Metrics

3
3.1

Clock Cfg
Block Clk Configuration

3.2

Block Clk timing checks

4
4.1

Power Cfg
Block Clk Configuration

4.2

Block Clk timing checks

5
5.1
5.2
5.3
5.4
6
6.1
7
7.1

Interface Cfg
usb cfg
eth cfg
i2c cfg
vga cfg
Traffic
Interupt

Description
Link
Power on bring up settings
FW_SRC pins (defined in WBsocDAD section 5.3.3) define the cov_init_fw_src_cp
initilization location of the base firmware. Four possible
sources [ROM, DDR, I2C, USB]
The power register (defined in WBsocDAD section 5.3.1)
cov_init_pwr_cp
defines the hard coded default power settings upon
initialization. Four settings [All off, All on, Processor Only, Top
Only]
The clock register (defined in WBsocDAD section 5.3.2)
cov_init_clk_zone_cp
defines the hard coded default clock settings upon
cov_init_clk_speed_cp
initialization. All 6 zones have their own settings [On/Off,
cov_init_clk_cross
speed setting]
Only 2 of the 5 arbitration schemes used
Setting each source/destination as master or slave and its
priority (defined in WBsocDAD section 3.2.12).
All source/destination priority unique
Simultaneous access with higher priority winning
Some source/destinations with same priority, first wins and
sumultaneous

Multiple requests with queued up requests to test last

master granted FSM (defined in WBsocDID section 6.5.2)
Total number of slots and slot duration (defined in
WBsocDAD section 4.1.7).

Total number of req/ack pairs, conflicts & no acks.

Req to Ack times

CoverPoint

Weight Goal Owner

1 100
1 100

CoverPoint

100

CoverPoint
CoverPoint
Cross

100

1
1
1

100
100
100

Sam

Sam

Joan

Joan
Joan
Joan

1
1
2

Joan
Joan
Joan

3
1
1

Joan

Joan
Joan

3
3

Joan

Sam

Sam

Sam

CoverPoint

cov_sfp_fixed_cp
cov_sfp_sametime_cp
dt_sfp_equal
cov_sfp_equal_cp

1
1
1

100
100
100

cov_tdm_slotset_cp
cov_tdm_lmg_cp

CoverPoint
CoverPoint
Test
CoverPoint
CoverPoint
CoverPoint
CoverPoint

1
1
1

100
100
100

cov_tdm_slotnum_cp
cov_tdm_slotlength_cp
cov_tdm_slot_cross

CoverPoint
CoverPoint
Cross

100

CoverGroup

1
1

100
100

CoverGroup

1
1

100
100

100

1
1

100
100

100

1
1
1
1
1
1
1
1
1

Sam
100
100 Ralph
100 July
100 George
100 Ben
100
100
100
100

cov_tdm_metric_cg

See clock bubble diagram (defined in WBsocDITL figure 5.1 & cov_clk_cfg_cg
priority paragraph following) and capture all the prioritized
configurations into coverpoints and crosses. Expand out here
later.
See clock definitinons tables (defined in WBsocDID Tables 4.1- assert_clk_xyz_prd
6) and apply assertions for the clock periods and clock skews. assert_clk_abc_skew
Expand out here later.
-root 5.1 usb.xml
-root 5.2 eth.xml
-root 5.3 i2c.xml
-root 5.4 vga.xml

Assertion
Assertion

CoverGroup

Assertion
Assertion

XML
XML
XML
XML

Priority

Fred

cov_sfp_priority_cp

See clock bubble diagram (defined in WBsocDITL figure 5.1 & cov_clk_cfg_cg
priority paragraph following) and capture all the prioritized
configurations into coverpoints and crosses. Expand out here
later.
See clock definitinons tables (defined in WBsocDID Tables 4.1- assert_clk_xyz_prd
6) and apply assertions for the clock periods and clock skews. assert_clk_abc_skew
Expand out here later.

Separate hierarchical spreadsheet

Separate hierarchical spreadsheet
Separate hierarchical spreadsheet from vip
Separate hierarchical spreadsheet
TBD - Filled out in next planning session
TBD - Filled out in next planning session
TBD - Filled out in next planning session
TBD - Filled out in next planning session

Type

2
see xls
see xls
see xls
see xls