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Multiplication of Pseudo-random codes for Multiple Access Interference (MAI

)
in DS-CDMA

ABSTRACT:
Direct Sequence Spread Spectrum Code Division Multiple Access
(DS-CDMA) is a modulation technique. As with other spread spectrum technologies, the
Transmitted signal takes up more bandwidth than the information signal that modulates the
carrier or broadcast frequency. CDMA is a channel access method used by various radio
communication technologies. One of the concepts in data communication is the idea of allowing
several transmitters to send information simultaneously over a single communication channel.
This allows several users to share a band of frequencies. This concept is called multiple accesses.
In telecommunication, a direct sequence spread spectrum system achieves its spreading
capability by modulating a narrow bandwidth data signal with a wide bandwidth spreading
signal. At the transmitter we use spreading code along with the symbol from different users and
the summed signal is transmitted and at the receiver the spreading code used must match with
that of the transmitter and both receiver and transmitter should be synchronized with each other
than at receiver we despread the code and information is recovered without multiple access
interference (MAI).

EXISTING:
A conventional DS/CDMA system treats each user separately as a signal, with other users
considered as noise or MAI -multiple access interference where the capacity is
interference-limited. The near/far effect: users near the BS are received at higher powers
than those far away. They suffer in degradation in performance. And also they need tight
power control.

Time shifted versions of a PN sequence will be nearly orthogonal. . 4. Transmitter 1. Generate orthogonal PN sequences for spreading having a length of 15 bits using linear feedback shift registers.03GHz (time period=30ns) 2. 5.5GHz (time period=2ns) and a second clock with frequency 0. Multiply the serial output of each shift registers with the generated PN sequences which are time shifted versions of one another and hence orthogonal. Provide all the four 8 bit long parallel inputs to four parallel in serial out shift register.PROPOSED: In this proposed system the DS-CDMA is implemented by VHDL where in the transmitter is designed with a clock generator matching with that at the receiver for synchronization and also the spreading code used at transmitter must match with that of the dispreading code used at receiver and the multiple access which is achieved by implementing with more users at transmitter side and this signal is transmitted and received at the receiver where in the information is recovered with little multiple access interference. Add the multiplier outputs of each user and transmit it through the channel. 3. Generate master clock having a frequency of 0. The shift registers are provided with a clock of 0.5GHz and a mode control input that controls the shift or load operation of the register.

Block Diagram of Transmitter: Clock generator 0.5GHZ Data input Transmitter output PN Sequence Generator PISO Shift Register PISO Shift Register X X SUM Clock of 0.5GHZ PISO Shift Register X PISO Shift Register X .

Generate PN sequences similar to that in the transmitter. Provide the output from the transmitter to the receiver. The same logic used in the transmitter should be used in the receiver. The nal output is obtained at the output of comparator . Give the received data to the four separate multipliers where the received data is multiplied with the four separate PN sequences 5. The output of multiplier is to be given to a comparator in parallel form which compares this parallel data with parallel converted PN sequence 7. Generate master clock for the receiver which is having the same frequency that is being used in the transmitter 2. 3. The multiplied output is converted into parallel by serial to parallel converter similar to that is done for the PN sequence 6.RECEIVER 1. convert the generated PN sequences to parallel 4. Using serial to parallel converter.

BLOCK DIAGRAM OF RECEIVER Clock Generato r 0.5GHZ output of Transmitter PN Sequenc e generato r Serial to parallel convertor PN sequence generato r Serial to parallel convertor PN sequence generato r Serial to parallel convertor PN sequence generato r Serial to parallel convertor Receiver X Compara tor X Compara tor X Compara tor X Compara tor .

Screen Shots for Transmitter part: .