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Carry Look Ahead Adder

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Carry-lookahead adder

4-bit adder with carry lookahead

**A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-lookahead adder
**

improves speed by reducing the amount of time required to determine carry bits. It can be

contrasted with the simpler, but usually slower, ripple carry adder for which the carry bit is

calculated alongside the sum bit, and each bit must wait until the previous carry has been

calculated to begin calculating its own result and carry bits (see adder for detail on ripple carry

adders). The carry-lookahead adder calculates one or more carry bits before the sum, which

reduces the wait time to calculate the result of the larger value bits. The Kogge-Stone

adderand Brent-Kung adder are examples of this type of adder.

Charles Babbage recognized the performance penalty imposed by ripple carry and developed

mechanisms for anticipating carriagein his computing engines.[1] Gerald Rosenberger of IBM filed

for a patent on a modern binary carry-lookahead adder in 1957.[2]

Contents

1 Theory of operation

2 Carry lookahead method

3 Implementation details

4 Manchester carry chain

**Theory of operation[edit]
**

A ripple-carry adder works in the same way as pencil-and-paper methods of addition. Starting at

the rightmost (least significant) digit position, the two corresponding digits are added and a result

obtained. It is also possible that there may be a carry out of this digit position (for example, in

pencil-and-paper methods, "9+5=4, carry 1"). Accordingly all digit positions other than the

rightmost need to take into account the possibility of having to add an extra 1, from a carry that

has come in from the next position to the right.

This means that no digit position can have an absolutely final value until it has been established

whether or not a carry is coming in from the right. Moreover, if the sum without a carry is 9 (in

pencil-and-paper methods) or 1 (in binary arithmetic), it is not even possible to tell whether or not

a given digit position is going to pass on a carry to the position on its left. At worst, when a whole

sequence of sums comes to ...99999999... (in decimal) or ...11111111... (in binary), nothing can

be deduced at all until the value of the carry coming in from the right is known, and that carry is

then propagated to the left, one step at a time, as each digit position evaluated "9+1=0, carry 1"

or "1+1=0, carry 1". It is the "rippling" of the carry from right to left that gives a ripple-carry adder

that group is going to propagate a carry that comes in from the right. on reaching the left-hand end of its supergroup. If that carry is going to propagate all the way through the next group. the lookahead units perform their calculations. a 256-bit adder could have up to 24 gate delays in its carry processing). On the other hand. before the carry emerges from the next group the lookahead unit is immediately (within 1 gate delay) able to tell the next group to the left that it is going to receive a carry . and the less acceleration is obtained as a result. but then move 4 times as fast. the lookahead unit will already have deduced this. With this kind of two-level implementation. for instance. The more bits in a group. However. within each group that receives a carry. and using this information. propagate through the "superfast road" of 16-bit lookahead carry logic. on reaching the left-hand end of its group. Each lookahead carry unit already produces a signal saying "if a carry comes in from the right. I will propagate it to the left". Suppose that a carry arises in a particular group. 2. the "slow roads" on the way to the faster levels begin to impose a drag on the whole system (for instance. and this is in fact usually done. to tell the next lookahead unit to the left that a carry is on its way. just as in a ripple-carry system. The increase in the number of gates is also moderate: if all the group sizes are 4. and the more time is spent on the "slow roads" in each group rather than on the "fast road" between the groups (provided by the lookahead carry logic). allowance has to be made for the possibility that a carry could have to ripple through every one of the 32 one-bit adders. Carry lookahead depends on two things: 1. for each group of digits.its name. Again. When adding 32-bit integers. then. Simultaneously. Deciding the group size to be governed by lookahead carry logic requires a detailed analysis of gate and propagation delays for the particular technology being used. for each digit position. and its slowness.and. the fewer bits there are in a group. The net effect is that the carries start by propagating slowly through each 4-bit group. the more complex the lookahead carry logic becomes. Finally. Supposing that groups of 4 digits are chosen. the more groups have to be traversed to get from one end of a number to the other. The "supergroup" lookahead carry logic will be able to say whether a carry entering the supergroup will be propagated all the way through it. and those signals can be combined so that each group of (let us say) four lookahead carry units becomes part of a "supergroup" governing a total of 16 bits of the numbers being added. a carry may first propagate through the "slow road" of individual adders. For very large numbers (hundreds or even thousands of bits) lookahead carry logic does not become any more complex. the group sizes to be chosen depend on the exact details of how fast signals propagate within logic gates and from one logic gate to another. because more layers of supergroups and supersupergroups can be added as necessary. and the mere physical transmission of signals from one end of a long number to the other begins . that carry will emerge at the left-hand end of the group and start propagating through the group to its left. Accordingly. at the same time. Then the sequence of events goes something like this: 1. leaping from one lookahead carry unit to the next. whether that position is going to propagate a carry if one comes in from the right. propagate through the "fast road" of 4-bit lookahead carry logic. then. It is possible to have more than one level of lookahead carry logic. 2. Combining these calculated values to be able to deduce quickly whether. Within at most 5 gate delays. it is able to propagate carries from right to left 16 times as fast as a naive ripple carry. one would end up with one third as many lookahead carry units as there are adders. the carry propagates slowly within the digits in that group. Calculating. All 1-bit adders calculate their results. 3.

If to represent the binary predicate that is true if and only propagates. Implementation details[edit] . the addition of the tens digits 5 and 6 generates because the result carries to the hundreds digit regardless of whether the ones digit carries (in the example. For example. Written in boolean algebra. for a multiple-level carry lookahead adder. Note that propagate and generate are defined with respect to a single digit of addition and do not depend on any other digits in the sum. we The addition of two 1-digit inputs A and B is said to propagate if the addition will carry whenever there is an input carry (equivalently. In the case of binary addition. In the case of binary addition. we have: Sometimes a slightly different definition of propagate is used. regardless of whether there is an input carry (equivalently. However.to be a problem. with the carry bit of digit i. Given these concepts of generate and propagate. In the case of binary addition. it is most natural to think of generating and propagating in the context of binary addition. the word digit can be replaced by bit when referring to binary addition of 2. Fortunately. when the next less significant digit in the sum carries). the concepts can be used more generally than this. this definition is expressed by: For binary arithmetic. the ones digit does not carry (2+7=9)). it is simpler to use . and and the propagate and generate bits of digit i respectively. write have: generates if and only if both A and B are 1. or is faster than xor and takes fewer transistors to implement. in the decimal addition 37 + 62. By this definition A + B is said to propagate if the addition will carry whenever there is an input carry. the addition of the tens digits 3 and 6 propagate because the result would carry to the hundreds digit if the ones were to carry (which in this example. For example. due to the way generate and propagate bits are used by the carry lookahead logic. it doesn't matter which definition is used. since they spend no time on carry propagation at all. At these sizes carry-save adders are preferable. Although in the context of a carry lookahead adder. The addition of two 1-digit inputs A and B is said to generate if the addition will always carry. In the descriptions below. when will a digit of addition carry? It will carry precisely when either the addition generates or the next less significant bit carries and the addition propagates. in the decimal addition 52 + 67. Carry lookahead method[edit] Carry lookahead logic uses the concepts of generating and propagating carries. but will not carry if there is no input carry. regardless of whether any less significant digits in the sum carry). it does not). we write if propagates if and only if at least one of A or B is 1. If we to represent the binary predicate that is true if and only if generates.

then into . The group propagate ( ) and group generate ( ) for a 4-bit CLA are: Putting 4 4-bit CLAs together yields four group propagates and four group generates. The Carry Look Ahead 4-bit adder can also be used in a higher-level circuit by having each CLA Logic circuit produce a propagate and generate signal to a higher-level CLA Logic circuit. the logic for the generate (g) and propagate (p) values are given below. there is no delay from waiting for the ripple carry effect (or time it takes for the carry from the first Full Adder to be passed down to the last Full Adder). The calculation of the gate delay of a 16-bit adder (using 4 CLAs and 1 LCU) is not as straight forward as the ripple carry adder. The XOR is used normally within a basic full adder circuit. Starting at time of zero: calculation of and is done at time 1 calculation of is done at time 3 . Note that the numeric value determines the signal from the circuit above. then into yields the expanded equations: To determine whether a bit pair will generate a carry. when the actual addition is performed. the following logic works: To determine whether a bit pair will propagate a carry. the OR is an alternate option (for a carry lookahead only) which is far simpler in transistor-count terms. starting from 0 on the far left to 3 on the far right: Substituting into . then the term is 1 (since its equation is ). The only difference in the truth tables between ( ) and ( ) is when both and are 1. However. The LCU then generates the carry input for each of the 4 CLAs and a fifth equal to in the . if both and are 1. either of the following logic statements work: The reason why this works is based on evaluation of . Below is a simple 4-bit generalized Carry Look Ahead circuit that combines with the 4-bit Ripple Carry Adder we used above with some slight adjustments: For the example provided.For each bit in a binary sequence to be added. and the term becomes irrelevant. This allows the circuit to "preprocess" the two numbers being added to determine the carry ahead of time. Then. the Carry Look Ahead Logic will determine whether that bit pair will generate a carry or propagate a carry. A Lookahead Carry Unit (LCU) takes these 8 values and uses identical logic to calculate CLAs.

A Manchester carry chain generates the intermediate carries by tapping off nodes in the gate that calculates the most significant carry value. The maximum time is 8 gate delays (for ). Manchester carry chain[edit] The Manchester carry chain is a variation of the carry-lookahead adder that uses shared logic to lower the transistor count. . One of the major downsides of the Manchester carry chain is that the capacitive load of all of these outputs. third & fourth CLA calculation of the final carry bit ( ) is done at time 5. CMOS being a major example. As can be seen above in the implementation section. third & fourth CLA calculation of the are done at time 4 for the first CLA time 8 for the second. A standard 16-bit ripple carry adder would take 31 gate delays. together with the resistance of the transistors causes the propagation delay to increase much more quickly than a regular carry lookahead. Not all logic families have these internal nodes however. Dynamic logic can support shared logic.calculation of the is done at time 2 calculation of the is done at time 3 calculation of the inputs for the CLAs from the LCU are done at time 0 for the first CLA time 5 for the second. A Manchester-carry-chain section generally won't exceed 4 bits. as can transmission gate logic. the logic for generating each carry contains all of the logic used to generate the previous carries.

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