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GLOBALFOUNDRIES 40nm CMOS Low Power (40nm-LP)


Technology Design Manual
YI-DM00085_14

GLOBALFOUNDRIES Confidential

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Copyright GLOBALFOUNDRIES 2011


All Rights Reserved
Printed in Singapore 2011
All information contained in this document is subject to change without notice. The products described
in this document are NOT intended for use in applications such as implantation, life support, or other
hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage.
The information contained in this document does not affect or change GLOBALFOUNDRIES product
specifications or warranties. Nothing in this document shall operate as an express or implied license or
indemnity under the intellectual property rights of GLOBALFOUNDRIES or third parties. All information
contained in this document was obtained in specific environments, and is presented as an illustration.
The results obtained in other operating environments may vary.
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are
made.
Note: This document contains information on products in the design, sampling and/or initial
production phases of development. This information is subject to change without notice.
Verify with your GLOBALFOUNDRIES field applications
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN AS IS BASIS. In
no event will GLOBALFOUNDRIES be liable for damages arising directly or indirectly from any use
of the information contained in this document.
GLOBALFOUNDRIES
60 Woodlands Industrial Park D Street 2
Singapore 738406
The GLOBALFOUNDRIES home page can be found at

http://globalconnect.GLOBALFOUNDRIESoundries.com/

April 2012 Confidential


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Contents
List of Figures ....................................................................................................................................................... 9
List of Tables ...................................................................................................................................................... 11
1. Technology Introduction ............................................................................................................................... 15
1.1 Features ......................................................................................................................................................... 15
1.2 Description ..................................................................................................................................................... 16
1.3 Ordering Information ...................................................................................................................................... 16
1.4 Chip Design Checklist .................................................................................................................................... 19
2. Physical Design Information ......................................................................................................................... 20
2.1 Design Scale and Grid ................................................................................................................................... 20
2.2 Mask and Design Levels ................................................................................................................................ 20
2.3 Nondesign Mask Levels ................................................................................................................................. 25
2.4 Design and Utility Levels ................................................................................................................................ 26
2.5 Data Preparation Levels ................................................................................................................................. 32
2.6 Kerf Design Levels ......................................................................................................................................... 33
2.7 Reference Levels ........................................................................................................................................... 33
2.8 Mask Alignment Sequence and Metallization Options ................................................................................... 34
2.8.1 General Remarks on BEOL Metallization Options ............................................................................. 34
2.8.2 BEOL Stack Designation Convention ................................................................................................. 34
2.8.3 BEOL Metallization Options................................................................................................................ 35
2.8.4 40nm-LP Cross Section...................................................................................................................... 37
2.9 Design Preparation (Boolean Level Generation) ........................................................................................... 39
2.10 Truth Tables ................................................................................................................................................. 39
3. Physical Design Rules ................................................................................................................................... 54
3.1 Design Rule Syntax ........................................................................................................................................ 54
3.1.1 Multiple Levels per Rule ..................................................................................................................... 54
3.1.2 Electrical Selection Functions ............................................................................................................ 54
3.1.3 Unary Operators ................................................................................................................................. 55
3.1.4 Binary Operators ................................................................................................................................ 58
3.1.5 Design Rule Conditions ...................................................................................................................... 61
3.2 Design Rule Abbreviations ............................................................................................................................. 64
3.4 Geometry Restriction Design Rules ............................................................................................................... 66
3.5 Polysilicon and Isolation Design Rules .......................................................................................................... 67
3.6 Short Edge Design Rules ............................................................................................................................... 72
3.7 Antenna Design Rules ................................................................................................................................... 73
3.7.1 Definitions ........................................................................................................................................... 74
3.7.2 Design Rule Assumptions .................................................................................................................. 74
3.7.3 Design Rules ...................................................................................................................................... 75
3.8 1.8 V, 2.5 V, or 3.3 V I/O Device Design Rules ............................................................................................. 77
3.9 High-Speed I/O Device Design Rules ............................................................................................................ 78
3.10 N-Well and Latchup Design Rules ............................................................................................................... 79
3.11 Triple-Well and Latchup Design Rules ......................................................................................................... 80
3.11.1 T3 Design Approach ......................................................................................................................... 80
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3.12 Moat Design Rules ....................................................................................................................................... 81


3.13 Zero-Vt NFET Design Rules ......................................................................................................................... 82
3.14 Low-Vt / Superlow-Vt Device Design Rules ................................................................................................. 84
3.15 High-Vt Device Design Rules ....................................................................................................................... 86
3.16 JX Design Rules ........................................................................................................................................... 87
3.17 JZ Design Rules ........................................................................................................................................... 88
3.18 Butted-Junction Design Rules ...................................................................................................................... 89
3.19 Bipolar Transistor Design Rules ................................................................................................................... 90
3.19.1 Vertical PNP Bipolar Trasistor .......................................................................................................... 91
3.19.2 Vertical NPN Bipolar Transistor ........................................................................................................ 91
3.20 Thick-Oxide / Medium-Oxide LDMOS Design Rules ................................................................................... 92
3.21 NFET in N-Well Capacitor Design Rules ..................................................................................................... 97
3.22 PFET in P-Well Capacitor Design Rules ...................................................................................................... 98
3.23 Silicide-Blocked OP Resistor Design Rules ................................................................................................. 99
3.24 Salicided Resistor Design Rules ................................................................................................................ 102
3.25 N-Well Resistor Design Rules .................................................................................................................... 104
3.26 Latchup Design Rules ................................................................................................................................ 107
3.26.1 Internal Latchup Design Rules ....................................................................................................... 107
3.27 ESD Silicide-Blocking Design Rules .......................................................................................................... 111
3.28 ESD Design Rules ..................................................................................................................................... 114
3.28.1 Net Definitions for ESD Checking .................................................................................................. 125
3.28.2 ED P+ Implant for ESD ................................................................................................................... 126
3.29 Contact Design Rules ................................................................................................................................ 127
3.30 1x Metal and Via Design Rules .................................................................................................................. 130
3.31 2x Metal and Via Design Rules .................................................................................................................. 146
3.32 1x to 6x Transitional Via Design Rules ...................................................................................................... 154
3.33 2x to 6x Transitional Via Design Rules ...................................................................................................... 155
3.34 6x Metal and Via Design Rules .................................................................................................................. 156
3.35 LB and VV Design Rules ............................................................................................................................ 159
3.36 BEOL Vertical Natural Capacitor Design Rules ......................................................................................... 161
3.36.1 Hierarchal Vertical Natural Capacitor (HCVNCAP) ........................................................................ 161
3.36.2 Alternative Polarity MoM Capacitor (APMOM) ............................................................................... 164
3.36.3 Using VNCAP_PARM and VNCAP_COUNT ................................................................................. 165
3.37 Inductor Design Rules ................................................................................................................................ 167
3.38 Fuse Design Rules ..................................................................................................................................... 169
3.39 DV Passivation Opening Design Rules ...................................................................................................... 171
3.40 RZ Design Rules ........................................................................................................................................ 171
3.41 Flip Chip Terminal Design Rules ................................................................................................................ 172
3.41.1 Mask Sequence and Alignment ...................................................................................................... 172
3.41.2 Active Flip Chip Terminals .............................................................................................................. 173
3.41.3 LB and LV Pad Design ................................................................................................................... 176
3.41.4 Dummy Flip Chip Terminals ........................................................................................................... 177
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3.41.5 Reliability Design Rules .................................................................................................................. 177


3.42 Wire-Bond Terminal Design Rules ............................................................................................................. 179
3.42.1 Inline Wire-Bond Pads .................................................................................................................... 180
3.42.2 Inline Dual Wire-Bond/Probe Pads ................................................................................................. 181
3.42.3 Staggered Wire-Bond Pads ............................................................................................................ 182
3.42.4 Testing and Packaging Restrictions ............................................................................................... 184
3.42.5 LB Wide Metal Slot Guidelines ....................................................................................................... 185
3.43 Chip Guard Ring Design Rules .................................................................................................................. 186
3.44 Permissible Chip Size Design Rules .......................................................................................................... 189
3.45 Mask Process Control Image Design Rules .............................................................................................. 190
3.46 Reserved Level Checking Design Rules .................................................................................................... 191
3.47 Product Label Design ................................................................................................................................. 191
3.47.1 General Requirements ................................................................................................................... 191
3.47.2 Chip Protection Notices .................................................................................................................. 193
3.47.3 Chip Identificaton ............................................................................................................................ 193
3.47.4 Mask Level Identification ................................................................................................................ 193
3.48 RX, PC, Metal Dummy Fill Design Rules ................................................................................................... 194
3.49 NOHALO and NOSD Design Rules ........................................................................................................... 196
3.50 ACLV macros Drop-In to PRIME die .......................................................................................................... 197
4. Design for Manufacturability ....................................................................................................................... 198
4.1 Recommended Nonminimum Design Rules for Yield Enhancement .......................................................... 199
5. Device Electrical Parameters ...................................................................................................................... 200
5.1 Available Devices ......................................................................................................................................... 200
5.2 Compact Models .......................................................................................................................................... 205
5.3 NFET in Isolated P-Well (Triple-Well) Devices ............................................................................................ 205
5.4 Well Edge-Proximity Effect ........................................................................................................................... 205
5.5 Shallow Trench Isolation Design Specifications .......................................................................................... 205
5.6 Stress Proximity ........................................................................................................................................... 205
5.7 Important Notes ............................................................................................................................................ 206
5.7.1 Device Operating Voltages ............................................................................................................... 206
5.7.2 Trigger and Sustaining Voltage of MOSFET Snapback ................................................................... 206
5.7.3 Device Length and Width ................................................................................................................. 206
5.7.4 Channel Length/Width Variation ....................................................................................................... 207
5.7.5 Threshold voltage ............................................................................................................................. 207
5.7.6 Gate Dielectric Thickness (T ox_eq, Tox_gl, Tox_inv) ................................................................................ 208
5.7.7 Gate-Oxide Leakage ........................................................................................................................ 208
5.8 Superlow-Vt / Low-Vt FET Device................................................................................................................ 209
5.9 Regular-Vt FET Device ................................................................................................................................ 211
5.10 High-Vt FET Device ................................................................................................................................... 212
5.11 Medium-Oxide 1.5V I/O FET Device .......................................................................................................... 213
5.12 Medium-Oxide 1.8V I/O FET Device .......................................................................................................... 214
5.13 Thick-Oxide 1.8V I/O FET Device .............................................................................................................. 215
5.14 Thick-Oxide 2.5V I/O FET Device .............................................................................................................. 216
5.15 Thick-Oxide 3.3V I/O FET Device .............................................................................................................. 217
5.16 Thin-Oxide Native NFET Device ................................................................................................................ 218
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5.17 Medium-Oxide Native NFET Device .......................................................................................................... 219


5.18 Thick-Oxide Native NFET Device .............................................................................................................. 220
5.19 5V LDMOS Transistor Device .................................................................................................................... 221
5.19.1 2.5V and 3.3V Thick-oxide 5V LDMOS Transistor Device ............................................................. 221
5.19.2 1.8V Medium-oxide 5V LDMOS Transistor Device ........................................................................ 222
5.20 Junction Diode............................................................................................................................................ 222
5.20.1 STI-Bounded Junction Breakdown Voltage ................................................................................... 222
5.21 Vertical PNP Bipolar Transistor .................................................................................................................. 223
5.22 Resistors .................................................................................................................................................... 223
5.22.1 Silicide-Blocked Resistors .............................................................................................................. 223
5.22.2 Silicided Resistors .......................................................................................................................... 224
5.22.3 Electrical Parameters (at 25C) ...................................................................................................... 224
5.22.4 Resistance Calculation ................................................................................................................... 225
5.23 Hierarchal Vertical Natural Capacitor (HCVNCAP) .................................................................................... 226
5.24 NFET in N-Well Capacitor (NCAP) ............................................................................................................ 227
5.24.1 Design Guidelines .......................................................................................................................... 227
5.24.2 ACLV Considerations ..................................................................................................................... 227
5.24.3 Fuse Considerations....................................................................................................................... 228
5.24.4 Yield and Reliability : Product Reliability Impact ............................................................................ 228
5.24.5 Use in Off-Chip Drivers................................................................................................................... 228
5.24.6 NCAP HSPICE Models................................................................................................................... 228
5.25 PFET in P-Well Capacitor (PCAP) ............................................................................................................. 229
5.26 Electrical Fuse ............................................................................................................................................ 229
5.26.1 eFUSE Structure ............................................................................................................................ 229
5.26.2 Power Requirements ...................................................................................................................... 229
5.26.3 eFUSE Programming, Sensing and Yield ...................................................................................... 230
5.27 Wiring Resistance Models .......................................................................................................................... 231
5.27.1 Contact and Via Resistance ........................................................................................................... 231
5.27.2 Sheet Resistance and Film Thickness ........................................................................................... 232
5.28 Wiring Capacitance Models ....................................................................................................................... 235
5.28.1 Parameters for Capacitance Calculation ........................................................................................ 235
5.28.2 Wiring Capacitance Tracking ......................................................................................................... 236
5.28.3 Quick Look-Up Wiring Capacitances (3D Model) ........................................................................... 236
5.28.4 CA-to-PC Capacitance ................................................................................................................... 238
5.29 Matching Characteristics ............................................................................................................................ 239
5.29.1 Recommended Design Rules ......................................................................................................... 239
5.29.2 Recommended Guidelines ............................................................................................................. 239
5.29.3 Transistor Mismatch ....................................................................................................................... 241
5.29.4 N-Well Proximity Effect ................................................................................................................... 243
5.29.5 Resistors Mismatch ........................................................................................................................ 243
5.29.6 Capacitors Mismatch ...................................................................................................................... 244
5.29.7 Parametric Uncertainty for Small-Geometry Devices ..................................................................... 244
6. Reliability Design Rules and Model............................................................................................................ 246
6.1 Guidelines for Optimal Reliability ................................................................................................................. 246
6.2 Reliability Screening ..................................................................................................................................... 247
6.2.1 Burn-In .............................................................................................................................................. 247
6.2.2 Wafer Screening ............................................................................................................................... 247
6.3 Front-End-of-Line (FEOL) Reliability Design Rules ..................................................................................... 248
6.3.1 Hot Carrier Effects ............................................................................................................................ 248
6.3.2 Hot Carrier Mechanism..................................................................................................................... 248
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6.3.3 Gate Dielectric Integrity .................................................................................................................... 256


6.3.4 Vmax and Vos for 1.8 nm, 2.8 nm and 5,2 nm Gate Dielectrics .......................................................... 257
6.3.5 Threshold Voltage Stability ............................................................................................................... 260
6.3.6 Nonionic Instability ............................................................................................................................ 260
6.3.7 Using Device Degradation Data ....................................................................................................... 261
6.3.8 Forward-Bias Injection Threshold Shift ............................................................................................ 262
6.3.9 P+Polysilicon OP Resistor Temperature Rise and Resistance Change .......................................... 262
6.3.10 Soft Error Rate ................................................................................................................................ 262
6.4 Back-End-of-Line (BEOL) Reliability Design Rules ..................................................................................... 262
6.4.1 Electromigration (EM) ....................................................................................................................... 262
6.4.2 Metal Corrosion ................................................................................................................................ 271
7. SRAM Device and Design Information ....................................................................................................... 272
7.1 General Remark ........................................................................................................................................... 272
7.2 Physical Design Information ......................................................................................................................... 274
7.2.1 Design Scale and Grid...................................................................................................................... 274
7.2.2 Mask and Design Levels .................................................................................................................. 274
7.2.3 Design and Utility Levels .................................................................................................................. 274
7.2.4
Mask Alignment Sequence and Metallization Options ............................................................. 275
7.2.5
Design of Single Port and Dual Port SRAM cells ..................................................................... 275
7.2.6
Truth Table ............................................................................................................................... 279
7.3.
SRAM Physical Design Rules ........................................................................................................... 280
7.3.1
7.3.2
7.3.3

Design Rule Abbreviations ....................................................................................................... 280


Additional SRAM Design Rules................................................................................................ 283
SRAM Design Hierarchy .......................................................................................................... 285
Electrical Parameters ........................................................................................................................ 286

7.4.1
7.4.2
7.4.3

Electrical Parameters for GLOBALFOUNDRIES 40LP GF299 SRAM Cell ................................. 286
Electrical Parameters for GLOBALFOUNDRIES 40LP GF374 SRAM Cell ................................. 288
Electrical Parameters for GLOBALFOUNDRIES 40LP GF589 SRAM Cell ................................. 290
Reliability Design Rules and Models ................................................................................................ 292

7.4.

7.5.

8. RF Device and Design Information ............................................................................................................. 293


8.1 Technology Introduction ............................................................................................................................... 293
8.1.1 General Remark ............................................................................................................................... 293
8.1.2 Features............................................................................................................................................ 293
8.1.3 Ordering Information ......................................................................................................................... 293
8.1.4 Chip Design Checklist ...................................................................................................................... 293
8.2 Physical Design Information ......................................................................................................................... 294
8.2.1 Design Scale and Grid...................................................................................................................... 294
8.2.2 Mask and Design Levels .................................................................................................................. 294
8.2.3 Nondesign Mask Levels ................................................................................................................... 294
8.2.4 Design and Utility Levels .................................................................................................................. 294
8.2.5 Data Preparation Levels ................................................................................................................... 294
8.2.6 Kerf design levels ............................................................................................................................. 294
8.2.7 Reference level ................................................................................................................................. 294
8.2.8 Mask Alignment Sequence and Metallization Options ..................................................................... 294
8.2.9 Design Preparation ........................................................................................................................... 294
8.2.10 Truth Tables ................................................................................................................................... 295
8.3 Physical Design Rules ................................................................................................................................. 305
8.3.1 Design Rules Abbreviations ............................................................................................................. 305
8.3.2 MIM Capacitor Design Rules ............................................................................................................ 305
8.3.3 UTM18x Metal and Via Design Rule (Copper Inductor Design Rule) .............................................. 309
8.4 Design for Manufacturability ......................................................................................................................... 311
8.5 Device Electrical Parameters ....................................................................................................................... 312
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8.5.1 Available Devices ............................................................................................................................. 312


8.5.2 Metal-Insulator-Metal (MIM) Capacitor ............................................................................................. 315
8.5.3 Wiring Resistor Model ...................................................................................................................... 316
Appendix A. General Introduction .................................................................................................................. 317
Appendix B. Design Flow for Tapeout to 40nm-LP ...................................................................................... 318
B.1 Design methodology .................................................................................................................................... 318
B.1.1 Design flow ....................................................................................................................................... 318
Appendix C. Designer Guidelines .................................................................................................................. 319
C.1 Guideline to usage of SPICE Model ............................................................................................................ 319
C.2 PEX Extraction Guideline ............................................................................................................................ 320
Appendix D. Design Hierarchy Guidelines .................................................................................................... 321
Appendix E. Definitions of Process-Related Terms ..................................................................................... 322
Appendix F. Design Services Design Rules .................................................................................................. 323
Revision Log ..................................................................................................................................................... 330

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List of Figures
Figure 2-1a. 40nm-LP Technology Example Cross Section ......................................................................................... 37
Figure 2-1b. 40nm-LP Technology Example Cross Section (including RF design) ...................................................... 38
Figure 3-1. Design Rule Syntax Dimension Definitions ................................................................................................ 56
Figure 3-2. Design Rule Syntax Area Definitions .......................................................................................................... 57
Figure 3-3. Design Rule Syntax Spacing Definitions .................................................................................................... 58
Figure 3-4. Design Rule Syntax Overlap Definitions ..................................................................................................... 59
Figure 3-5. Design Rule Syntax Containment Definition............................................................................................... 59
Figure 3-6. Design Rule Syntax Condition Definition .................................................................................................... 60
Figure 3-7. Design Rule Syntax Logical Function Definitions ....................................................................................... 61
Figure 3-8. Design Rule Syntax Sizing Function Definition .......................................................................................... 61
Figure 3-9. Design Rule Syntax Relational Selection Definitions ................................................................................. 62
Figure 3-10. Design Rule Syntax Geometrical Selection Function Definitions ............................................................. 63
Figure 3-11. Illustration for CAREC end and CAREC side ........................................................................................... 65
Figure 3-12. Gate Extension Area to Exclude from Rule 100R .................................................................................... 69
Figure 3-13. Polysilicon and Isolation Design Rules ..................................................................................................... 70
Figure 3-14. Design Rule 102h ..................................................................................................................................... 71
Figure 3-15. Charging Mechanism ................................................................................................................................ 73
Figure 3-16. Design Rule 3T02 ..................................................................................................................................... 81
Figure 3-17. Zero-Vt Device Design Rules .................................................................................................................... 83
Figure 3-18. Low- and High-Vt Device Design Rules .................................................................................................... 87
Figure 3-19. Butted Junction Design Rules .................................................................................................................. 89
Figure 3-20. Recommended Vertical PNP Bipolar Transistor Layout ........................................................................... 91
Figure 3-21. LDMOS Design Rules .............................................................................................................................. 94
Figure 3-22. Cross section view of LDMOS NFET key design rule ............................................................................. 95
Figure 3-23. Recommended Multiple-Cell LDMOS NFET layout ................................................................................ 95
Figure 3-24. Cross section view of LDMOS PFET key design rule ............................................................................. 96
Figure 3-25. Recommended Multiple-Cell LDMOS PFET layout ................................................................................. 96
Figure 3-26. OP Resistor Design Rules (Page 2 of 2) ................................................................................................ 101
Figure 3-28. Salicided Poly Resistor .......................................................................................................................... 103
Figure 3-29. Salicided Diffusion Resistor ................................................................................................................... 103
Figure 3-30. N-Well under STI Resistor Design Rules ............................................................................................... 105
Figure 3-31. N-Well over Active Resistor Design Rules ............................................................................................. 106
Figure 3-32. Internal Latchup Design Rules (Page 1 of 2) .......................................................................................... 108
Figure 3-32. Internal Latchup Design Rules (Page 2 of 2) .......................................................................................... 109
Figure 3-33. Space Between SBLK and Gate ............................................................................................................ 112
Figure 3-34. ESD Silicide-Blocking Design Rules ....................................................................................................... 113
Figure 3-35. ESD Design Rules for Diode-Based Protection ..................................................................................... 120
Figure 3-36. ESD Design Rules for MOSFET-Based Protection (Page 1 of 3) .......................................................... 121
Figure 3-36. ESD Design Rules for MOSFET-Based Protection (Page 2 of 3) .......................................................... 122
Figure 3-36. ESD Design Rules for MOSFET-Based Protection (Page 3 of 3) .......................................................... 123
Figure 3-37. ESD Design Rules for CDM Protection .................................................................................................. 124
Figure 3-38. WIRE_ESD ENDPT Text Label (Example) ............................................................................................ 125
Figure 3-39. ED Design Rules .................................................................................................................................... 126
Figure 3-40. Design Rule 203e .................................................................................................................................. 129
Figure 3-41. Design Rule 203f ................................................................................................................................... 129
Figure 3-42. M1_LE and M1_LS for 503_or ............................................................................................................... 132
Figure 3-43. 1x Metal and Via Design Rules (Page 1 of 4) ....................................................................................... 134
Figure 3-43. 1x Metal and Via Design Rules (Page 2 of 4)......................................................................................... 135
Figure 3-43. 1x Metal and Via Design Rules (Page 3 of 4)......................................................................................... 136
Figure 3-43. 1x Metal and Via Design Rules (Page 4 of 4)......................................................................................... 137
Figure 3-44. Mx_LE and Mx_LS for 603_or ............................................................................................................... 141
Figure 3-45. Explanation of exact configurations applied to 613 ............................................................................... 141
Figure 3-46. Explanation of 614 ................................................................................................................................. 142
Figure 3-47. Groundrule 615 Exemption 1 and 2. ...................................................................................................... 143
Figure 3-48. Groundrule 615 Exemption 3. ................................................................................................................. 144
Figure 3-49. Wide-Metal Via Design Rules ................................................................................................................ 145
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Figure 3-50. 2x Metal and Via Design Rules .............................................................................................................. 153


Figure 3-51. 6x Metal and Via Design Rules .............................................................................................................. 158
Figure 3-52. LB and VV Design Rules ........................................................................................................................ 160
Figure 3-53. HCVNCAP Cross Section ....................................................................................................................... 161
Figure 3-54. HCVNCAP top view ................................................................................................................................ 161
Figure 3-55. HCVNCAP connection design rule ......................................................................................................... 163
Figure 3-53a. APMOM Capacitor Cross Section ........................................................................................................ 164
Figure 3-54a. APMOM Capacitor Topview ................................................................................................................. 165
Figure 3-56. VNCAP_PARM and VNCAP_COUNT Layout Example ......................................................................... 166
Figure 3-57. Inductor Design Rules ............................................................................................................................ 168
Figure 3-58. Electrical Fuse Design Rules .................................................................................................................. 170
Figure 3-59. Active Flip Chip Terminal Structure ........................................................................................................ 173
Figure 3-60. Octagon Dimensions for LV and LVDUMMY Shapes (Need to update below table) ............................. 174
Figure 3-61. Flip Chip Terminal Design Rules ............................................................................................................ 175
Figure 3-62. Flip Chip Terminal LB or LV Pad Design ................................................................................................ 176
Figure 3-63. Dummy Flip ChipTerminal Structure ...................................................................................................... 177
Figure 3-64. Flip Chip LB Level ................................................................................................................................... 178
Figure 3-65. DV Wire-Bond Pad Design Rules ........................................................................................................... 179
Figure 3-66. Inline Wire-Bond Pad Design Rules ....................................................................................................... 180
Figure 3-67. Inline Dual Wire-Bond/Probe Pad Design Rules .................................................................................... 181
Figure 3-68. Staggered Wire-Bond Pad Design Rules ............................................................................................... 183
Figure 3-69. Inline Corner PAD Design Rules ............................................................................................................ 184
Figure 3-70. Staggered Corner PAD Design Rules .................................................................................................... 184
Figure 3-71. LB Wide Metal Slot Guidelines ............................................................................................................... 185
Figure 3-72. Chip Guard Ring Example Cross Section .............................................................................................. 188
Figure 3-73. CHIPEDGE Chamfer Requirement ........................................................................................................ 188
Figure 3-74. Product Label Placement Example ........................................................................................................ 192
Figure 3-75. Combined Mask Work and Copyright Notice .......................................................................................... 193
Figure 3-76. Placement of MACROACLV near CHIPEDGE ....................................................................................... 197
Figure 5-1. Well Edge-Proximity Effect Due to Dopant Atom Scattering .................................................................... 205
Figure 5-2. Device Length and Width.......................................................................................................................... 207
Figure 5-3. eFUSE Programming Transistor .............................................................................................................. 230
Figure 5-4. Capacitance Calculation Model ................................................................................................................ 236
Figure 5-5. Extraction Parameters .............................................................................................................................. 238
Figure 5-6. Common Centroid ..................................................................................................................................... 240
Figure 6-1. Overshoot and Undershoot....................................................................................................................... 257
Figure 6-2. Example of flip chip / LB ........................................................................................................................... 268
Figure 7-1. Single Port SRAM Device ......................................................................................................................... 273
Figure 7-2. Dual Port SRAM Device ........................................................................................................................... 273
Figure 7-3. Layout for 0.299cell (GF299) .................................................................................................................... 276
Figure 7-4. Layout for 0.374 cell (GF374) ................................................................................................................... 277
Figure 7-5. Layout for 0.589 cell (GF589) ................................................................................................................... 278
Figure 7-6. SRAM design rules ................................................................................................................................... 285
Figure 8-1. Cross section of MIM capacitor ................................................................................................................ 305
Figure 8-2. MIM capacitor Design Rules ..................................................................................................................... 307
Figure 8-3. Recommended MIM cell layout ................................................................................................................ 308
Figure 8-4. UTM18x Metal and Via Design Rule ........................................................................................................ 310

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List of Tables
Table 1-1. Optional Features ...................................................................................................................................... 16
Table 2-1. Mask Levels, Design Levels and Graphic Design System II (GDSII) Stream Layers .......................... 20
Table 2-2. Nondesign Mask Levels and GDS Stream Layers ................................................................................. 25
Table 2-3. Design Levels, Utility Levels, and GDS Stream Layers ......................................................................... 26
Table 2-4. Design Services and Data Preparation Levels ....................................................................................... 32
Table 2-5. Kerf Design Levels .................................................................................................................................... 33
Table 2-6. Reference Levels ....................................................................................................................................... 33
Table 2-7. Design Kit Metallization Options (Page 1 of 2) ....................................................................................... 35
Table 2-7. Design Kit Metallization Options (Page 2 of 2) ....................................................................................... 36
Table 2-9. Design Truth Table .................................................................................................................................... 40
Table 2-10. Data Preparation Truth Table ................................................................................................................. 50
Table 3-1. Design Rule Checking Abbreviations ..................................................................................................... 64
Table 3-2. Geometry Restriction Design Rules ........................................................................................................ 66
Table 3-5. RX Design Rules ........................................................................................................................................ 67
Table 3-6. PC Design Rules ........................................................................................................................................ 68
Table 3-7. Short Edge Design Rules .......................................................................................................................... 72
Table 3-8. Antenna Design Rules .............................................................................................................................. 75
Table 3-9. 1.8 V, 2.5 V, or 3.3 V I/O Device Design Rules ........................................................................................ 77
Table 3-10. High-Speed I/O Device Design Rules .................................................................................................... 78
Table 3-11. N-Well and Latchup Design Rules ......................................................................................................... 79
Table 3-12. Alternative Triple-Well and Latchup Design Rules .............................................................................. 80
Table 3-13. BFMOAT Design Rules ........................................................................................................................... 81
Table 3-14. Zero-Vt NFET Design Rules .................................................................................................................... 82
Table 3-15a. Low-Vt Device Design Rules................................................................................................................. 84
Table 3-15b. Superlow-Vt Device Design Rules ....................................................................................................... 85
Table 3-16. High-Vt Device Design Rules ................................................................................................................. 86
Table 3-17. JX Design Rules ...................................................................................................................................... 87
Table 3-18. JZ Design Rules ....................................................................................................................................... 88
Table 3-19. Butted-Junction Design Rules ............................................................................................................... 89
Table 3-20. BIPOLAR Design Rules........................................................................................................................... 90
Table 3-21a. Vertical PNP Bipolar Transistor Design Rules ................................................................................... 91
Table 3-21b. Vertical NPN Bipolar Transistor Design Rules ................................................................................... 91
Table 3-22. LDNMOS Design Rules .......................................................................................................................... 92
Table 3-23. 2.5V and 3.3V Thick-oxide LDMOS Design Rules ............................................................................... 93
Table 3-24. Medium-oxide LDMOS Design Rules ................................................................................................... 93
Table 3-25. NCAP Design Rules ................................................................................................................................. 97
Table 3-26. PCAP Design Rules ................................................................................................................................. 98
Table 3-27. OP Resistor Design Rules ...................................................................................................................... 99
Table 3-30. Salicided Resistor Design Rules ......................................................................................................... 102
Table 3-31a. N-Well under STI Resistor Design Rules .......................................................................................... 104
Table 3-31b. N-Well Over Active Resistor Design Rules ....................................................................................... 106
Table 3-32. Internal Latchup Design Rules ............................................................................................................. 107
Table 3-33. ESD Silicide-Blocking Design Rules ................................................................................................... 111
Table 3-34. ESD Design Rule Assumptions ........................................................................................................... 114
Table 3-35. ESD Design Rules ................................................................................................................................. 115
Table 3-36. Backend ESD Design guidelines ......................................................................................................... 119
Table 3-37. ED Design Rules .................................................................................................................................... 126
Table 3-38. CA Design Rules .................................................................................................................................... 127
Table 3-39. M1 Design Rules .................................................................................................................................... 130
Table 3-40. V1 Design Rules .................................................................................................................................... 133
Table 3-41. Mx and Vx Design Rules ....................................................................................................................... 138
Table 3-42. 2x Metal Design Rules in Low-K Dielectric ......................................................................................... 146
Table 3-43. 2x Via Design Rules in Low-K Dielectric ............................................................................................. 148
Table 3-44. 2x Metal Design Rules in FTEOS Dielectric ........................................................................................ 150
Table 3-45. 2x Via Design Rules in FTEOS Dielectric ............................................................................................ 151
Table 3-46. 1x to 6x Transitional Via Design Rules ............................................................................................... 154
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Table 3-47. 2x to 6x Transitional Via Design Rules ............................................................................................... 155


Table 3-48. 6x Metal and Via Design Rules ............................................................................................................. 156
Table 3-49. LB and VV Design Rules ....................................................................................................................... 159
Table 3-50. HCVNCAP Design Rules ....................................................................................................................... 162
Table 3-50a. APMOM Design Rules ......................................................................................................................... 164
Table 3-51. VNCAP Starting Level According to VNCAP_PARM ......................................................................... 165
Table 3-52. HCVNCAP and APMOM metal scheme list for available BEOL option ............................................ 166
Table 3-53. Inductor Design Rules .......................................................................................................................... 167
Table 3-54. Electrical Fuse Design Rules ............................................................................................................... 169
Table 3-55. DV Design Rules .................................................................................................................................... 171
Table 3-56. RZ Design Rules .................................................................................................................................... 171
Table 3-57. Design Mask Levels .............................................................................................................................. 172
Table 3-58. Nondesign Mask Levels ........................................................................................................................ 172
Table 3-59. Shape Manipulation Performed Prior to Writing the Mask ................................................................ 172
Table 3-60. Flip Chip Terminal (Active and Dummy) Design Rules ..................................................................... 174
Table 3-61. Flip Chip Terminal LB or LV Pad Design Rules.................................................................................. 176
Table 3-62. Design Rules for Flip Chip Terminals at 110C for Ceramic Packages ........................................... 177
Table 3-63. Common Wire-Bond Pad Design Rules .............................................................................................. 179
Table 3-64. Inline Wire-Bond Pad Design Rules .................................................................................................... 180
Table 3-65. Inline Dual Wire-Bond/Probe Pad Design Rules ................................................................................ 181
Table 3-66. Staggered Wire-Bond Pad Design Rules 25 m Pitch ....................................................................... 182
Table 3-67. Staggered Wire-Bond Pad Design Rules 30 m Pitch ....................................................................... 182
Table 3-68. Chip Guard Ring and PROTECT Design Rules .................................................................................. 186
Table 3-69. CHIPEDGE Design Rules ...................................................................................................................... 189
Table 3-70. xxING Design Rules for PCI Target Cells ............................................................................................ 190
Table 3-71. Reserved Level Checking Design Rules ............................................................................................. 191
Table 3-72. Special LOGOBND Design Rules ......................................................................................................... 192
Table 3-73. RXFILL, PCFILL Design Rules ............................................................................................................. 194
Table 3-74. MxFILL Design Rules ............................................................................................................................ 195
Table 3-75. NOHALO and NOSD Design Rules ...................................................................................................... 196
Table 3-76. ACLV Macro Design Rules ................................................................................................................... 197
Table 3-77. General guidelines on number of MACROACLV cells drop-in for different PRIME die sizes ....... 197
Table 4-1. Priority for Primary Recommended Rules ............................................................................................ 199
Table 5-1. Available Field-Effect Transistors ......................................................................................................... 200
Table 5-2. Other Available Devices .......................................................................................................................... 201
Table 5-3. Operating Voltages .................................................................................................................................. 206
Table 5-4. Thin-Oxide Gate Leakage for Different Models at 25C ....................................................................... 208
Table 5-5a. Electrical Parameters for Low-Vt FET Devices .................................................................................. 209
Table 5-5b. Electrical Parameters for Superlow-Vt FET Devices ......................................................................... 210
Table 5-6. Electrical Parameters for Regular-Vt FET Devices .............................................................................. 211
Table 5-7. Electrical Parameters for High-Vt FET Devices .................................................................................... 212
Table 5-8. Electrical Parameters for Medium-Oxide 1.5V I/O FET Devices ......................................................... 213
Table 5-9. Electrical Parameters for Medium-Oxide 1.8V I/O FET Devices ......................................................... 214
Table 5-10. Electrical Parameters for Thick-Oxide 1.8V I/O FET Devices............................................................ 215
Table 5-11. Electrical Parameters for Thick-Oxide 2.5V I/O FET Devices............................................................ 216
Table 5-12. Electrical Parameters for Thick-Oxide 3.3V I/O FET Devices............................................................ 217
Table 5-13. Electrical Parameters for Thin-Oxide Native NFET Devices ............................................................. 218
Table 5-14. Electrical Parameters for Medium-Oxide Native NFET Devices ....................................................... 219
Table 5-15. Electrical Parameters for Thick-Oxide Native NFET Devices ........................................................... 220
Table 5-16. Electrical parameters for 2.5V_DG 5V LDMOS transistor devices ................................................... 221
Table 5-17. Electrical parameters for 3.3V_DG 5V LDMOS transistor devices ................................................... 221
Table 5-18. Electrical parameters for 1.8V_EG 5V LDMOS transistor devices ................................................... 222
Table 5-19. Reverse-Bias Breakdown Voltage ....................................................................................................... 222
2
Table 5-20. Electrical Parameters for the Vertical PNP Bipolar Transistor (Emitter area=3.2x3.2m ) ............ 223
Table 5-21. Electrical parameters of Precision P+ Poly resistor device .............................................................. 223
Table 5-22a. Electrical Parameters for Silicide-Blocked Resistors ...................................................................... 224
Table 5-22b. Electrical Parameters for Silicided Resistors .................................................................................. 224
Table 5-22c. Electrical Parameters for N-well Resistors ....................................................................................... 224
Table 5-23. Summary of HCVNCAP DC data .......................................................................................................... 226
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Table 5-24. Electrical Parameters for the NFET in N-Well Capacitors ................................................................. 227
Table 5-25. Electrical Parameters for the PFET in P-Well Capacitors (PCAPs) .................................................. 229
Table 5-26. Electrical Parameters for the eFUSE ................................................................................................... 230
Table 5-27. Contact and Via Resistance ................................................................................................................. 231
Table 5-28. FEOL Sheet Resistance and Film Thickness ..................................................................................... 232
Table 5-29. Resistance of Minimum Width, Minimum Space Wires at 25C ....................................................... 232
Table 5-30. BEOL Sheet Resistance and Film Thickness ..................................................................................... 233
Table 5-31. WOPC ...................................................................................................................................................... 234
Table 5-32. Systematic Variation Correction Parameters ..................................................................................... 234
Table 5-33. Interlevel Capacitances......................................................................................................................... 237
Table 5-34. Transistor Matching Characterization ................................................................................................. 242
Table 5-35. Regular FET 1 Threshold Voltage and Gm Mismatch Distribution ............................................... 243
Table 5-36. NW Proximity Effect .............................................................................................................................. 243
Table 5-37. Resistor Pair Matching Constants ....................................................................................................... 244
Table 6-1. NFET Conducting Hot Carrier Model Parameters ................................................................................ 250
Table 6-2a. Thin-Oxide (SG) RVT NFET Hot Carrier Duty Factor ......................................................................... 251
Table 6-2b. Medium-Oxide (EG) NFET Hot Carrier Duty Factor ........................................................................... 251
Table 6-3. PFET Conducting Hot Carrier Model Paramaters ................................................................................ 253
Table 6-4. Thin-oxide (SG) RVT PFET Duty Cycle Factor...................................................................................... 254
Table 6-4b. Medium-oxide (EG) PFET Duty Cycle Factor...................................................................................... 255
Table 6-5. Maximum Voltage Parameters for 1.8 nm, 2.8 nm and 5,2 nm Gate Dielectrics ............................... 258
Table 6-6. End-of-Life Vt shifts (100 000 Power-On Hours) .................................................................................. 260
Table 6-7. General Idc Current Limits at 110C ....................................................................................................... 265
Table 6-8. Maximum Idc Current Limit for Vias at 110C ........................................................................................ 266
Table 6-9. Maximum Idc Current Limit for Short Length Application.................................................................... 266
Table 6-10. Examples of Contacts (CA/M1) at 110C ............................................................................................. 267
Table 6-11. Design Rules for flip chip Terminals at 110C for Ceramic Packages ............................................. 268
Table 6-12. Electromigration and Redundancy for flipchip Terminals at a 110C Operating Temperature ..... 269
Table 6-13. Flip chip Redundancy Example ........................................................................................................... 269
Table 6-14. Adjustment Factors for Idc Only for Temperature and Time ............................................................. 270
Table 6-15. Idc Temperature Adjustment Factors ................................................................................................... 271
Table 6-16. Idc Time Adjustment Factors ................................................................................................................. 271
Table 7-1. GLOBALFOUNDRIES 40LP SRAM Device Dimensions ....................................................................... 272
Table 7-2. Mask Levels, Design Levels, and Graphic Design System II (GDSII) Stream Layers ....................... 274
Table 7-3. Design Levels, Utility Levels, and GDS Stream Layers ....................................................................... 274
Table 7-4. GLOBALFOUNDRIES 40LP Truth Table ................................................................................................ 279
Table 7-5. Design Rule Checking Abbreviations ................................................................................................... 280
Table 7-6. SRAM Ground-rule Waivers ................................................................................................................... 280
Table 7-7. Additional SRAM Design Rules ............................................................................................................. 283
Table 7-8. Available Field-Effect Transistors in the GF299 SRAM Cell ............................................................... 286
Table 7-9. Electrical Parameters for SRAM NFET / PFET Devices in the GF299 SRAM Cell ............................. 287
Table 7-10. GF299 1 Vt Matching within Cell ...................................................................................................... 287
Table 7-11. Available Field-Effect Transistors in the GF374 SRAM Cell ............................................................. 288
Table 7-12. Electrical Parameters for SRAM NFET / PFET Devices in the GF374 SRAM Cell at nominal Vdd 288
Table 7-13. GF374 1 Vt Matching within Cell ...................................................................................................... 289
Table 7-14. Available Field-Effect Transistors in the GF589 SRAM Cell ............................................................. 290
Table 7-15. Electrical Parameters for SRAM NFET / PFET Devices in the GF589 SRAM Cell at nominal VDD291
Table 7-16. GF589 1 Vt Matching within Cell ...................................................................................................... 291
Table 8-1. Design Truth Table .................................................................................................................................. 295
Table 8-2. Data preparation Truth Table ................................................................................................................. 300
Table 8-3. MIM scheme ............................................................................................................................................. 305
Table 8-4. MIM capacitor Design Rules ................................................................................................................... 306
Table 8-5. 3A and 3T Design Rules .......................................................................................................................... 309
Table 8-6. Available RF Field-Effect Transistors .................................................................................................... 312
Table 8-7. Other Available Devices .......................................................................................................................... 313
Table 8-8. Electrical Parameters for MIM capacitor ............................................................................................... 315
Table 8-9. Via resistances ........................................................................................................................................ 316
Table 8-10. Wire resistances in an Array of Minimum Width, Minimum Space wires at 25C........................... 316
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Table 8-11. BEOL sheet resistance and film thickness ......................................................................................... 316
Table C-1. RXFILL and PCFILL Rules ...................................................................................................................... 323
Table C-2. Metal Fill Rules ........................................................................................................................................ 324
Table C-3. Via Fill Rules ............................................................................................................................................ 326
Table C-4. Local Pattern Density Rules .................................................................................................................. 326
Table F-5. Predicted Density (Page 1 of 3) ............................................................................................................. 327
Table F-5. Predicted Density (Page 2 of 3) ............................................................................................................. 328
Table F-5. Predicted Density (Page 3 of 3) ............................................................................................................. 329

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1. Technology Introduction
1.1 Features
CMOS Process
VDD of 1.1 V (thin-oxide) or 1.2V (thin-oxide)
Twin- or triple-well (NFET in isolated p-well) CMOS technology on nonepitaxial p-substrate
Shallow trench isolation
Stress-engineered and optimized devices
Three gate oxides permitted, 1.8 nm (thin),
2.8 nm (medium) and 5.2 nm (thick)
Minimum drawn gate length of 0.040 m
Low-resistance nickel-silicided n+ and p+doped polysilicon and diffusion
Tungsten stud contact connecting polysilicon or diffusion to the first metal level

Device Options

Six to eight copper metal levels, including up to seven 1x, 1 relaxed-pitch 2x and two 6x metal level(s)
Planarized passivation and interlevel low-k dielectrics
Wire-bond pads
Optional electrically programmable fuse
2

Thin-oxide surface channel NFETs and PFETs with a minimum polysilicon gate length, Lp 0.035
0.0075 m
Two I/O application options: 1.5 V and 1.8 V devices with medium oxide and 1.8 V, 2.5 V, and 3.3 V
devices with thick oxide
Medium-oxide and Thick-oxide 5V LDMOS
Zero-Vt NFET devices offered with medium and thick gate oxides
Vertical PNP and Vertical NPN bipolar transistor
N+ diffusion, P+ diffusion, P+ polysilicon and N+ polysilicon OP resistors
Salicided N+ diffusion, P+ diffusion, P+ polysilicon and N+ polysilicon resistors
N-well resistor under STI and N-well resistor under Active
NFET in n-well capacitors
PFET in p-well capacitor
Hierarchal VNCAP (HCVNCAP)
Inductors on various metal levels
3
RF MIM capacitor build below 3um Cu wiring layer
3
RF Ultra Thick Metal (18x) Inductor (3um thickness copper layer)
All devices require the appropriate marker
4

Voltage and Temperature Range


Nominal power supply voltage of 1.1 V, 1.2V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V, and maximum power supply
voltage of 1.1 times nominal supply voltage
Maximum burn-in voltage of 1.5 times nominal voltage, and maximum burn-in temperature of 140C
Operating junction temperature range of -40C to 125C
Restricted-use operating junction temperature range of -55C to 150C
Notes:
1.
2.
3.
4.

For copper metal level thickness, see Table 5-8 BEOL Sheet Resistance and Film Thickness.
The total polysilicon gate length (Lp) tolerance is the sum of the 3 chip mean variation (0.0035 m) and the across-chip line-width
variation (0.0040 m).
Above Analog and RF Device Options is Plug-in module, it does not affect baseline process. Contact your GLOBALFOUNDRIES
technical representative before including them in your design.
For a summary of thin-, medium-, and thick-oxide device voltages, see Table 5-3 Operating Voltages.

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1.2 Description
40nm-LP is a 45nm CMOS application-specific integrated circuit (ASIC) and foundry technology developed for
static random access memory (SRAM), logic, mixed-signal, and mixed-voltage input/output (I/O) applications.

1.3 Ordering Information


Designers can use Table 1-1 to compile the list of optional features and part numbers required by
GLOBALFOUNDRIES manufacturing (contact your GLOBALFOUNDRIES technical representative for more
information). Feature availability and use restrictions are for reference only and might change. Requested features
will be evaluated on current information as part of the ordering process.
Table 1-1. Optional Features
Feature Group

Feature Description

Additional Masks

Always included

Base features for 40nm-LP

Well option

N-well and isolated p-well

N3

Thin oxide only

Thin + medium oxide

DG

Thin + thick oxide

DG

Thin-oxide zero-Vt NFET

BV

Medium-oxide zero-Vt NFET

DG

Thick-oxide zero-Vt NFET

DG

Regular-Vt + low-Vt NFET + superlow-Vt NFET


Regular-Vt + low-Vt PFET + superlow-Vt PFET

BV, XW, GY
CV, LW, IY

Regular-Vt + high-Vt NFET


Regular-Vt + high-Vt PFET

BV, NR
CV, PR

Regular-Vt + medium-oxide I/O NFET


Regular-Vt + medium-oxide I/O PFET

BV, DG , IN, GN
4
CV, DG , IP, GP

Oxide options
(Select one)

Zero-Vt options

FET option
(Select one)

Regular-Vt + medium-oxide I/O + low-Vt NFET +


superlow-Vt NFET
Regular-Vt + medium-oxide I/O + low-Vt PFET +
superlow-Vt PFET
superlow-Vt NFET + Low-Vt + medium-oxide I/O NFET
superlow-Vt PFET + Low-Vt + medium-oxide I/O PFET
superlow-Vt NFET + Low-Vt + regular-Vt + high-Vt +
medium-oxide I/O NFET
superlow-Vt NFET + Low-Vt + regular-Vt + high-Vt +
medium-oxide I/O PFET
Regular-Vt + thick-oxide I/O NFET
Regular-Vt + thick-oxide I/O PFET
Regular-Vt + thick-oxide I/O + low-Vt NFET +
superlow-Vt NFET
Regular-Vt + thick-oxide I/O + low-Vt PFET +
superlow-Vt PFET
superlow-Vt NFET + Low-Vt + thick-oxide I/O NFET
superlow-Vt PFET + Low-Vt + thick-oxide I/O PFET
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1, 2

DG , BV, XW, IN, GN, GY


4

DG , CV, LW, IP, GP, IY


4

DG , XW, IN, GN, GY


4
DG , LW, IP, GP, IY
4

DG , XW, BV, NR, IN, GN, GY


4

DG , LW, CV, PR, IP, GP, IY


BV, DG, JN, DE
CV, DG, JP, DF
DG, BV, XW, JN, DE, GY
DG, CV, LW, JP, DF, IY
DG, XW, JN, DE, GY
DG, LW, JP, DF, IY

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Feature Group

Capacitor
options

Resistor options
(Select any)

BEOL VNCAP
option
ESD option
Bipolar option

High Voltage
FET option

Inductor option

SRAM options

Wiring options
(select one)

Feature Description
superlow-Vt NFET + Low-Vt + regular-Vt + high-Vt +
thick-oxide I/O NFET
superlow-Vt PFET + Low-Vt + regular-Vt + high-Vt +
thick-oxide I/O PFET
Thin-oxide PCAP
Medium-oxide PCAP
Thick-oxide PCAP

Additional Masks

Thin-Oxide NCAP
Medium-oxide NCAP
Thick-oxide NCAP

4
DG
DG

P+ diffusion OP resistor

OP

N+ diffusion OP resistor
P+ polysilicon OP resistor
N+ polysilicon OP resistor
P+ diffusion resistor

OP
OP
OP

N+ diffusion resistor
P+ polysilicon resistor
N+ polysilicon resistor
N-well resistor under STI
N-well resistor under Active
Hierarchal VNCAP (HCVNCAP)

Alternate Polarity MOM (APMOM)


Electrostatic discharge (ESD) devices
Vertical PNP bipolar transistor and Vertical NPN bipolar
transistor
2.5V/3.3V Thick-oxide 5V LDNMOS
2.5V/3.3V Thick-oxide 5V LDPMOS
1.8V Medium-oxide 5V LDNMOS
1.8V Medium-oxide 5V LDPMOS
Native, thick wire inductor
Native, thick wire metal (2X)
Native, thick wire metal (6X)
Native, thick wire metal (10X)
Analog UTM 3um metal
Dense SRAM Cell Type CH299
Standard SRAM Cell Type CH374

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1, 2

DG, XW, BV, NR, JN, DE, GY


DG, LW, CV, PR, JP, DF, IY
N3
4
N3, DG
N3, DG

OP
OP
JN, DG, DE
N3, JP, DG, DF
4
IN, DG , GN
4
N3, IP, DG , GP

NV, PV, AD
NV, PV, AD

Dual Port SRAM Cell Type CH589


Dual Port SRAM Cell Type CH741
No static random access memory (SRAM)
Two 6x wiring with LB

NV, PV, AD
NV, PV, AD

OT, FA, JR, FB, VV, LB

Two 2x low-k and two 6x wiring with LB

J0, L1, J1, L2, GM, FA, JR, FB,


VV, LB

One 2x low-k and one 6x wiring with LB

J0, L1, GM, FA, VV, LB

One 2x low-k and two 6x wiring with LB

J0, L1, GM, FA, JR, FB, VV, LB

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Feature Group

Levels of metal
(select one)

Final Protection
Mask

Bonding scheme
Fuse option
MIM Capacitor
option
Inductor option

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1, 2

Feature Description

Additional Masks

One 6x wiring with LB


One 2x TEOS wiring with LB
Two 2x TEOS wiring with LB
6LM
7LM
8LM
9LM
10LM
DV (Wirebond with Polyimide)
LV (Flipchip with Polyimide)

OT, FA, VV, LB


WT, BA, VV, LB
WT, BA, WA, BB, VV, LB

RS, DV
RS, LV
This option requires RS mask
instead of (not in addditon to)
DV
VV, LB, DV
VV, LB, LV, TM

QT, HT, QE

RZ (Wirebond without Polyimide)


Aluminum wire bond (LB is always present for wire bond)
Flip Chip
Electrically programmable eFUSE
Build in the TEOS/FTEOS dielectric below the final
copper wiring layer
Ultra Thick Metal (3um) Inductor

3A

1. Additional masks required beyond the base feature-required levels (that is, RX, NW, BF, ZP, PC, BN, BP,
and CA).
2. BEOL masks are dependent on the metal stack. Refer to Table 2-1 Mask Levels, Design Levels, and
Graphic Design System II (GDSII) Stream Layers and Table 2-7 Design Kit Metallization Options for
BEOL masks.
3. Contact your GLOBALFOUNDRIES representative before ordering.
4. EG design level will use DG at mask level.

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1.4 Chip Design Checklist


The following checklist is required to be completed prior to design data submission:
1. The design passes design rule checking (DRC).
2. The design passes layout versus schematic (LVS) checking.
3. Simulation results of all circuits are satisfactory across the entire operating range and process variation
range and across modeled wear out mechanisms, including burn-in and total use conditions through the
product lifetime:

No hot carrier or negative bias temperature instability (NBTI) shifts result in loss of circuit function
due to changes in timing, skew, performance, or standby current.
No contacts or metal lines carry more than their rated currents.
All circuits operate at the reliability screen conditions and/or at burn-in conditions.

4.
5.
6.
7.

Electrostatic discharge (ESD) and latchup layout and design requirements are met.
No floating wells are present.
Internal power bus networks minimize local power supply drops and deviations.
Power supply network test probe and package lead impedances match those expected to ensure functionality and testability.
8. The recommendations listed in Appendix A Design Hierarchy Guidelines have been considered.
Note: A design kit is available through your GLOBALFOUNDRIES technical representative.

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2. Physical Design Information


2.1 Design Scale and Grid
40nm-LP designs must be laid out on a 0.001m grid.

2.2 Mask and Design Levels


The design levels RX, NW, PC, JX, JZ and CA must be present in 40nm-LP design. The appropriate metal and via
levels discussed in Section 2.7 Reference Levels must also be present in the design. This table is not for MEBES
review reference.
Note: To prevent mask- and/or design-level name conflicts during design, data preparation and kerf merge
procedures; do not use the reserved levels in Table 2-4 Design Services and Data Preparation Levels and
Table 2-5 Kerf Design Levels.
Table 2-1. Mask Levels, Design Levels and Graphic Design System II (GDSII) Stream Layers
Mask
Level

Design
Level

GDSII
Layer
No.

GDSII
Data
Type

Minimu
m Line
(m)

Minimum
Space
(m)

RX

RX

Gate oxide, and n+ and p+ diffused regions.

Blocked

0.060

0.080

NW

NW

N-well region.

Open

RX

0.340

0.340

GY

GY

212

104

Superlow-Vt NFET extension / halo implant

Open

RX

0.180

0.180

IY

IY

212

105

Superlow-Vt PFET extension / halo implant

Open

RX

0.180

0.180

XW

XW

12

low-Vt NFET extension / halo implant

Open

RX

0.180

0.180

LW

LW

12

low-Vt PFET extension / halo implant

Open

RX

0.180

0.180

NR

NR

12

High-Vt NFET extension / halo implant

Open

RX

0.180

0.180

PR

PR

12

High-Vt PFET extension / halo implant

Open

RX

0.180

0.180

ED

ED

12

35

Region receiving a special ESD implant.

Open

RX

0.500

0.500

43

Medium gate-oxide area.

0.340

0.340

Blocked

RX
0.340

0.340

EG
DG

Shape Description

12
DG

On Wafer

Aligns
to

Thick gate-oxide area.

BP

JX

212

137

N+ source or drain implant area.

Open

RX

0.180

0.180

BN

JZ

212

138

P+ source or drain implant area.

Open

RX

0.180

0.180

OP

OP.SBL
K

37

Area blocked from silicide formation over diffusion


and polysilicon/.

Blocked

RX

0.200

0.200

PC

PC

Polysilicon Line

Blocked

RX

0.040

0.100

NV9

NV

12

30

Vt adjustment for nFET halo.

Open

RX

0.140

0.140

PV

12

31

Vt adjustment for pFET halo.

Open

RX

0.140

0.140

AD

AD

12

100

Vt adjustment for p-well implant for the Access Nfet.

Open

RX

0.180

0.180

ZP9

SRAM_N
PRE

200

68

Memory Cell N Predope

Open

PC

0.460

0.360

PV

CA
CA

CABAR

0
14

CAREC
M1

M1

15

Square stud contact; CA connects either RX or PC to


M1
Rectangular stud contact; CABAR is used only in the
chip guard ring and part number /label field

88

SRAM-only contact

First-level metal line (for trench in low-k).

GLOBALFOUNDRIES Confidential

Open

Open

PC

CA

0.060

0.080

0.089

0.144

0.060

0.080

0.070

0.070

Spec ID:
Revision:
Page:
Mask
Level

Design
Level

GDSII
Layer
No.

V1
V1

M2

1
17

V2
V2

M3

19

V3
V3

M4

M4

21

V4
V4

M5

31

V5
V5

M6

44

V6
V6

M7

46

J0
J0

L1

225

J1
J1

L2

226

J2
J2

Third-level metal line (for trench in low-k).

Square via for connecting M3 to M4

L3

227

Aligns
to

Open

M1

Open

V1

Open

M2

Open

V2

Open

M3

Open

V3

Open

M4

Rectangular via for connecting M3 to M4.

Fourth-level metal line (for trench in low-k).

Square via for connecting M4 to M5.

Rectangular via for connecting M4 to M5.

Fifth-level metal line (for trench in low-k).

Square via for connecting M5 to M6.

Rectangular via for connecting M5 to M6.

Sixth-level metal line (for trench in low-k).

Square via for connecting M6 to M7.

Open

M4

Open

M5

Open

M5

Open

M6

Rectangular via for connecting M6 to M7.

Seventh-level metal line (for trench in low-k).

Open

M6

Transitional, square via for connecting last thin metal


M3M6 to the first 2x thick metal layer L1 in the low-k
dielectric.

Open

MLAST
3
1X

Rectangular via used in the chip guard ring and


inductor.

First-level 2x metal line in the low-k dielectric.

Square via for connecting the thick metal level L1 to


L2 in the low-k dielectric.

Rectangular via used in the chip guard ring and


inductor.

Second-level 2x metal line in the low-k dielectric.

Square via for connecting the thick metal level L2 to


L3 in the low-k dielectric.

245
J2BAR

L3

Rectangular via for connecting M2 to M3.

244
J1BAR

L2

243
J0BAR

L1

Square via for connecting M2 to M3.

45
V6BAR

M7

32
V5BAR

M6

Second-level metal line (for trench in low-k).

22
V4BAR

M5

Rectangular via for connecting M1 to M2.

20
V3BAR

On Wafer

Square via for connecting M1 to M2.

18
V2BAR

M3

Shape Description

16
V1BAR

M2

GDSII
Data
Type

[YI-DM00085]
[14]
21 of 330

Rectangular via used in the chip guard ring and


inductor.

Third-level 2x metal line in the low-k dielectric.

GLOBALFOUNDRIES Confidential

Open

MLAST
3
1X

Open

L1

Open

L1

Open

L2

Open

L2

Minimu
m Line
(m)

Minimum
Space
(m)

0.070

0.070

0.078

0.155

0.070

0.070

0.070

0.070

0.078

0.155

0.070

0.070

0.070

0.070

0.078

0.155

0.070

0.070

0.070

0.070

0.078

0.155

0.070

0.070

0.070

0.070

0.078

0.155

0.070

0.070

0.070

0.070

0.078

0.155

0.070

0.070

0.130

0.150

0.155

0.466

0.140

0.140

0.130

0.150

0.155

0.466

0.140

0.140

0.130

0.150

0.155

0.466

0.140

0.140

Spec ID:
Revision:
Page:
Mask
Level

Design
Level

GDSII
Layer
No.

J3
J3

L4

228

WT
WT

Square via for connecting the thick metal level L3 to


L4 in the low-k dielectric.

BA

89

WA

Open

L3

Transitional, square via for connecting the last thin


metal M3M6 to the first 2x thick metal level BA in the
TEOS/ FTEOS dielectric.

Open

MLAST
3
1X

101

Rectangular via used in the chip guard ring and


inductor.

100

First-level 2x metal line in the TEOS/FTEOS dielectric


(with a 1x low-k level below).

100

Square via for connecting the thick metal layer BA, or


B1 to BB in the TEOS/FTEOS dielectric.

101

Rectangular via used in the chip guard ring and


inductor.

91

100

WB

92

100

Square via for connecting the thick metal level BB or


B2 to BD in the TEOS/FTEOS dielectric.

WB

BD

BD

95

WD
WD

Rectangular via used in the chip guard ring and


inductor.

100

Third-level 2x metal line, either the third level in the


TEOS/ FTEOS dielectric (no 2x ultralow-k or low-k
level below), or the second level in oxide (one 2x
ultralow-k or low-k level below), or the first level in
oxide (two 2x ultralow-k or low-k levels below).

100

Square via for connecting the thick metal level BD or


B3 to BE in the TEOS/FTEOS dielectric.

96
WDBAR

BE

101

BE

97

WE
WE

101

Rectangular via used in the chip guard ring and


inductor.

100

Fourth-level 2x metal line, either the fourth level in the


TEOS/ FTEOS dielectric (no 2x ultralow-k or low-k
level below), or the third level in oxide (one 2x
ultralow-k or low-k level below), or the second level in
oxide (two 2x ultralow-k or low-k levels below), or the
first level in oxide (three 2x ultralow-k or low-k levels
below).

Square via for connecting the thick metal level BE or


B4 to BG in the TEOS/FTEOS dielectric.

157
WEBAR

Rectangular via used in the chip guard ring and


inductor.

GLOBALFOUNDRIES Confidential

Minimu
m Line
(m)

Minimum
Space
(m)

0.130

0.150

0.155

0.466

0.140

0.140

0.130

0.150

0.155

0.466

0.140

0.140

0.130

0.150

0.155

0.466

0.140

0.140

0.130

0.150

0.155

0.466

0.140

0.140

0.130

0.150

0.155

0.466

0.140

0.140

0.130

0.150

0.155

0.466

L3

Fourth-level 2x metal line in the low-k dielectric.

BB

92

Aligns
to

Second-level 2X metal line, either the second level in


the TEOS/FTEOS dielectric (no 2x ultra low-k or
low-k level below), or the first level in oxide (one 2x
ultralow-k or low-k level below).

WBBAR

Open

Rectangular via used in the chip guard ring and


inductor.

90
WABAR

On Wafer

88

WA

BB

100

WTBAR
BA

Shape Description

246
J3BAR

L4

GDSII
Data
Type

[YI-DM00085]
[14]
22 of 330

Open

MLAST
3
1X

Open

B1, L1,
BA

Open

B1, L1,
BA

Open

B2, L2,
BB

Open

B2, L2,
BB

Open

B3, L3,
BD

Open

B3, L3,
BD

Open

B4, L4,
BE

Spec ID:
Revision:
Page:
Mask
Level

BG

Design
Level

BG

GDSII
Layer
No.

152

OT
OT

Fifth-level 2x metal line, either the fifth level in the


TEOS/ FTEOS dielectric (no 2x ultralow-k or low-k
level below), or the fourth level in oxide (one 2x
ultralow-k or low-k level below), or the third level in
oxide (two 2x ultralow-k or low-k levels below), or the
second level in oxide (three 2x ultralow-k or low-k
levels below), or the first level in oxide (four 2x
ultralow-k or low-k levels below).

Square via for connecting the last 1x metal to FA


(transitional via in oxide).

OTBAR

Rectangular via used in the chip guard ring,


crackstop, and inductor.

GM

Square via for connecting the last 2x metal to FA


(transitional via in oxide).

229
GMBAR

FA

117

JR
JR

Rectangular via used in the chip guard ring,


crackstop, and inductor.

First-level 6x metal line in the TEOS/FTEOS


dielectric.

Square via for connecting the thick metal level FA to


FB in the TEOS/FTEOS dielectric.

242
JRBAR

FB

Shape Description

199

GM

FA

GDSII
Data
Type

FB

150

VV
VV

Rectangular via used in the chip guard ring and


inductor.

Second-level 6x metal line in the TEOS/FTEOS


dielectric.

Via for connecting the last copper metal to LB.

70
VVBAR

Rectangular via for connecting the last copper metal


to LB.

[YI-DM00085]
[14]
23 of 330
Aligns
to

Minimu
m Line
(m)

Minimum
Space
(m)

Open

B4, L4,
BE

0.140

0.140

MLAST
3
1X

0.360

0.340

Open

0.400

1.200

0.360

0.340

0.400

1.200

0.400

0.400

0.360

0.340

0.400

1.200

0.400

0.400

3.000 or
2.000

2.000

1.388

2.000

2.000

2.000

On Wafer

Open

LLAST2
X3
BLAST
2X3

Open

MLAST
1X3,
BLAST
2X3

Open

FA

Open

FA

Open

BB, BD,
BE, BG,
LLAST2
3
X

LB

LB

69

Aluminum wire level with oxide dielectric; uppermost


wiring level for every stack.

Blocked

VV

LV

LV

28

Opening in the final polyimide passivation; required


for flip chip terminals.

Open

LB

DV

DV

27

Open

LB

15.400

6.600

RZ

212

143

Open

LB

15.400

6.600

LV

28

Open

LB

DV

27

Open

LB

15.400

6.600

TM

26

LB

2 last
Cu layer

NA

NA

RS

TM

Opening in the final polyimide passivation; required


for designs that use wire-bond pads.
Opening in the final hard dielectric passivation;
required for designs that use wire-bond pads and no
polyimide
Opening in the final hard dielectric; required for
designs that use flip chip terminals and polyimide
process
Opening in the final hard dielectric; required for
designs that use wire-bond pads and polyimide
process
Plated terminal metal area.

Open

nd

QE7

30

10

MIM capacitor kerf alighment shape

Open

HT

HT

30

20

MIM capcacitor top plate

Blocked

QE

1.00

1.00

QT

QT

30

MIM capcacitor bottom plate

Blocked

QE

1.00

1.00

3A

3A

200

28

Wire level for thick copper inductor.

Open

MLAST
1X ,
MLAST

GLOBALFOUNDRIES Confidential

Spec ID:
Revision:
Page:
Mask
Level

Design
Level

GDSII
Layer
No.

GDSII
Data
Type

Shape Description

On Wafer

[YI-DM00085]
[14]
24 of 330
Aligns
to

Minimu
m Line
(m)

Minimum
Space
(m)

0.36

0.34

0.400

1.200

6X

3T
3T
3TBAR8
1.

2.
3.
4.
5.
6.
7.
8.
9.

35
200
36

Square via for connecting 3A to ELAST1X


Rectangular via used in the crackstop and IND over
ELAST1X

Open

MLAST
1X

Open = after exposure, the absence of resist covering the region where the level is drawn or generated.
Blocked = resist will be covering the regions after exposure, where the layer is drawn/generated.
On wafer is combinations of resist and mask tone.
Alignment must be measured to the primary level.
MLAST1X, BLAST2X, LLAST2X and ELAST4X as defined in Table 2-6.
BB transitions directly to BD without level BC because BC is already used in other technology FEOL processes.
BE transitions directly to BG without level BF because BF is already used in the FEOL process.
For the Mx layers, where x = 24, alignment is controlled to the Vx layer below, where x = 13. However, for these metal layers, the stepper
tool aligns to the Mx layer below, where x = 13
QE is alignenchance mask. It is not requirement to draw by designer
In LVS program code, rename 3A = U3A, 3T = U3T, 3TBAR = U3TBAR, the gds number and gds type of three layers keep same.
Required for the GLOBALFOUNDRIES 40LP cells.

GLOBALFOUNDRIES Confidential

Spec ID:
Revision:
Page:

[YI-DM00085]
[14]
25 of 330

2.3 Nondesign Mask Levels


The mask levels presented in Table 2-2 are generated; the designer does not have to draw them. Shapes drawn by
the designer on any of the mask levels listed in Table 2-2 will be discarded and replaced by generated shapes
during data preparation. This table is not for MEBES review reference.
All the dimensions (Line/ Space) in Table 2-2 are 90% (by shrunk) of design.
Table 2-2. Nondesign Mask Levels and GDS Stream Layers
Mask
Level

GDSII
Layer
No.

GDSII
Data
Type

On
Wafer1

Aligns
to

Minimum
Line (m)

Minimum
Space
(m)

BF

Complement of the p-well implant.

Blocked

RX

0.306

0.306

NW

BV

12

245

Regular-Vt NFET adjustment.

Blocked

RX

0.162

0.162

CV

12

246

Regular-Vt PFET adjustment.

Open

RX

0.162

0.162

IN

12

125

P-well region for the high-speed I/O NFET.

Open

RX

0.306

0.306

EG

IP

12

126

N-well region for the high-speed I/O PFET.

Open

RX

0.306

0.306

EG

JN

12

127

P-well region for the regular-I/O NFET.

Open

RX

0.306

0.306

DG

JP

12

128

N-well region for the regular-I/O PFET.

Open

RX

0.306

0.306

DG

ZP

12

154

Complement of the NFET polysilicon


pre-doping region.

Open

RX

0.162

0.162

NFETs

DE

12

DG NFET extension and halo implants.

Open

RX

0.162

0.162

DG

DF

12

12

DG PFET extension and halo implants.

Open

RX

0.162

0.162

DG

GN

12

195

EG NFET extension and halo implants.

Open

RX

0.162

0.162

EG

GP

12

196

EG PFET extension and halo implants.

Open

RX

0.162

0.162

EG

SM

12

218

Area open to the removal of stress nitride.

Open

RX

0.243

0.243

NFETs

NV

12

30

High-Vt adjustment for SRAM NFETs.

Open

RX

0.162

0.162

SRAM

PV

12

31

High-Vt adjustment for SRAM PFETs.

Open

RX

0.162

0.162

SRAM

N3

115

Isolated p-well region for triple-well NFETs.

Open

RX

0.468

0.720

T3

Shape Description

1. Open = after exposure, the absence of resist covering the region where the level is drawn or generated.
Blocked = resist will be covering the regions after exposure, where the layer is drawn/generated.
On wafer is combinations of resist and mask tone.

GLOBALFOUNDRIES Confidential

Associated with

Spec ID:
Revision:
Page:

[YI-DM00085]
[14]
26 of 330

2.4 Design and Utility Levels


The designer draws the design levels presented in Table 2-3. All designs require the CHIPEDGE level.
Table 2-3. Design Levels, Utility Levels, and GDS Stream Layers

Design Level

GDSII
Layer
No.

GDSII
Data
Type

Description

Associated with

Optional level placed over specific areas of the chip


at the customers discretion to prevent the
generation of MxFILL shapes during
GLOBALFOUNDRIES Design Service

MxFILL exclusion for


copper wiring levels

Used to fill empty space on Mx to meet the


manufacturing process pattern density
requirements.

Pattern density

Optional level placed over specific areas of the chip


at the customers discretion to prevent the
generation of Via FILL shapes.

Via FILL exclusion

Back-End-of-Line (BEOL) Utility Levels


MxEXCLUD,
Mx = M1
Mx = M2
Mx = M3
Mx = M4
Mx = M5
Mx = M6
Mx = M7
Mx = BA
Mx = BB
Mx = BD
Mx = BE
Mx = BG
Mx = FA
Mx = FB
Mx = 3A1

15
17
19
21
31
44
46
89
91
95
97
152
117
150
200

2
2
2
2
2
2
2
102
102
102
102
2
2
2
30

15
17
19
21
31
44
46
89
91
95
97
152
117
150
200

35
35
35
35
35
35
35
135
135
135
135
35
35
35
31

16
18
20
22
32
45
243
244
245
246

3
3
3
3
3
3
3
3
3
3

MxFILL,
Mx = M1
Mx = M2
Mx = M3
Mx = M4
Mx = M5
Mx = M6
Mx = M7
Mx = BA
Mx = BB
Mx = BD
Mx = BE
Mx = BG
Mx = FA
Mx = FB
Mx = 3A
VxEXCLUD
Vx = V1
Vx = V2
Vx = V3
Vx = V4
Vx = V5
Vx = V6
Vx = J0
Vx = J1
Vx = J2
Vx = J3

Device Design and Utility Levels


BIPOLAR

12

54

Placed over PNP and NPN emitters. It is used to


generate PH and eliminate halos to improve bipolar
performance.

PNP/NPN structures

EGV

12

44

Marking layer for 1.5 V high-speed I/O devices.

High-speed I/O rules

DGV

12

21

Marking layer for 1.8 V DG devices.

DG

DRES

12

222

Marking layer for unsilicided diffusion resistors.

Diffusion resistors

HVT

12

106

Marking layer for high-Vt devices.

High-Vt devices

GLOBALFOUNDRIES Confidential

Spec ID:
Revision:
Page:

[YI-DM00085]
[14]
27 of 330

GDSII
Layer
No.

GDSII
Data
Type

IND

12

38

Marking layer for inductors.

Inductor rules

LVT

12

50

Marking layer for low-Vt devices.

Low-Vt devices

NOHALO

12

114

Marking layer to exclude LDD/halo implant

Customized devices

NOSD

12

115

Marking layer to exclude S/D implant

Customized devices

SLVT

212

51

Marking layer for superlow-Vt devices

Superlow-Vt devices

NCAP

12

47

Marking layer for NFET in n-well capacitors.

NCAP rules

NWRES

61

Marking layer for n-well resistors.

N-well resistors

BPNWR

200

52

Marking layer for Nwell over Active Resistor

POLY_SAL

200

53

Marking layer for Salicide Poly Resistor.

DIFF_SAL

200

54

Marking layer for Salicide Diffusion Resistor.

OUTLINE_RF

62

65

Marking layer for RF devices.

RF devices

OVERDRIVE

12

163

Marking layer for 3.3 V DG devices.

Thick-oxide devices

PCAP

12

86

Marking layer for PFET in p-well capacitors.

PCAP rules

PRES

12

201

Marking layer for unsilicided polysilicon resistors.

Polysilicon resistors

TIEDOWN

12

200

Marking layer for Tie Down diodes

Tie Down Diodes

5VHVFET2

62

23

Marking layer for 5V LDMOS

LDNMOS, LDPMOS
NCAP/PCAP
Hierarchal Vncap

Design Level

Description

Associated with

Nwell over Active


Resistor
Salicide N+/P+ Poly
Resistor
Salicide N+/P+
Diffusion Resistor

VAR

12

24

Marking layer for MOSCAP varactars (either NCAP


or PCAP)

HCVNCAP

12

255

Marking layer for Hierarchal Vncap

VNCAPHV

61

110

Marking layer for Alternate polarity MOM

APMOM

VNCAP2

212

Marking layer in BEOL capacitor for RF LVS.

HCVNCAP/APMOM

VNCAP

62

120

VNCAP_COUNT

63

105

VNCAP_PARM

63

104

Marking layer for the vertical natural capacitor.


Normal wiring is permitted above the last metal
level used in the capacitor stack.
Marking layer for the vertical natural capacitor. It is
used in design checking to indicate the number of
metal levels in the capacitor design.
Marking layer for the vertical natural capacitor. It is
used in design checking to indicate the capacitor
starting metal level.

VN/VPP BEOL
capacitor rules
VN/VPP BEOL
capacitor rules
VN/VPP BEOL
capacitor rules

VNCAP_Mx,
x=1
x=2
x=3
x=4
x=5
x=6
x=7
VNCAP_By,

15
17
19
21
31
44
46

By = BA
By = BB
By = L1
By = L2

89
91
225
226

180
180
80
80

ZVT

12

VPNP

212

Marking layer for the vertical natural capacitor. It is


used in design checking to validate correct
capacitor construction

VN/VPP BEOL
capacitor rules

Marking layer for the vertical natural capacitor. It is


used in design checking to validate correct
capacitor construction

VN/VPP BEOL
capacitor rules

105

Used to block tailored-surface implants from


zero-Vt devices.

Zero-Vt device

148

Marking layer for vertical PNP devices

Vertical PNP

103

Marking layer for SRAM design rule checking and


denotes stepping periodicity of SRAM cells in array.

SRAM

80

SRAM Design and Utility Levels


CELLSNR

63

GLOBALFOUNDRIES Confidential

Spec ID:
Revision:
Page:

[YI-DM00085]
[14]
28 of 330

GDSII
Layer
No.

GDSII
Data
Type

CAREC

14

88

Rectangular CA contact.

SRAM

CAMINI

14

188

Mini contact

SRAM

DNS_SRAM

12

230

DPR_SRAM

12

232

LRG_SRAM

212

38

RF_SRAM

212

64

OUTLINE_NCELL0

62

67

Optional marker shape needed to create Array


Descriptor File (ADF) rules for bitfail mapping.

SRAM

OUTLINE_RCELL0

62

69

Optional marker shape needed to create Array


Descriptor File (ADF) rules for bitfail mapping.

SRAM

OUTLINE

62

21

Marker shape to define the edge of cell.

SRAMHVT

12

142

Marker shape to allow LVS to identify HVT SRAM


cells.

SRAM

CHRT_STRAP

200

13

Marker shape used by DRC tool for SRAM strap


cell related waiver handling.

SRAM

ESD_CDM

12

88

ESD_CLAMP

12

227

ESD_HBM

12

94

ESD_HBMSP

12

97

ESDSCR_HBM

212

16

ESDSH_STK_DEVMARK

200

220

ESDSH_SIN_DEVMARK

200

221

LBESD

69

60

ESD_DRAINMARK

200

222

Marking Layer to mark drain side of ESD device

ESD rules

SBLK

12

48

Silicide-blocking layer for ESD

ESD rules

15
17
19
21
31
44
46
225
226
227
228
89
91
95
97
152
117

60
60
60
60
60
60
60
60
60
60
60
160
160
160
160
60
60

Marking layer used to identify metal levels in


ESD/antenna DRC decks.

ESD rules

Design Level

Description

Marker shape to allow LVS to identify CH299


SRAM cells.
Marker shape to allow LVS to identify CH589
dual-port SRAM cell.
Marker shape to allow LVS to identify CH374
SRAM cells.
Marker shape to allow LVS to identify CH741
SRAM cells.

Associated with

SRAM
SRAM
SRAM
SRAM

ESD Design and Utility Levels


Placed over ESD charged-device model (CDM)
structures connected to a pad and used for
checking.
Placed over ESD RC-triggered power clamp
structures connected to a power supply pad and
used for checking.
Placed over ESD Human Body Model (HBM)
structures connected to a pad and used for
checking.
Placed over ESD Human Body Model (HBM)
structures connected to a pad and used for
checking.
Placed over ESD HBM SCR structures connected
to a pad and used for checking.
Marking layer to mark ESD stack shell device. Used
for LVS purpose only.
Marking layer to mark ESD non-stack shell device.
Used for LVS purpose only.
Marking layer used to identify chip pads in
ESD/antenna DRC decks.

ESD rules

ESD rules

ESD rules

ESD rules
ESD rules
ESD rules
ESD rules
Chip pads

xxESD
xx = M1
xx = M2
xx = M3
xx = M4
xx = M5
xx = M6
xx = M7
xx = L1
xx = L2
xx = L3
xx = L4
xx = BA
xx = BB
xx = BD
xx = BE
xx = BG
xx = FA

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Design Level

GDSII
Layer
No.

GDSII
Data
Type

150

60

xx = FB

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Description

Associated with

Far BEOL Design and Utility Levels


CLVS

12

144

LBEXCLUD

69

LBFILL

69

35

PROBE

12

62

LVDUMMY

28

12

98

Optional level used in wire-bond pad design to


identify the area between staggered pads as
CLVS-like during checking.
Optional level placed over specific areas of the chip
at the customers discretion to prevent the
generation of LBFILL shapes.
Used to fill empty space on LB to meet the
manufacturing process pattern density
requirements.
Used to mark final polyimide passivation probe pad
openings.
Marking layer to specify the area for C4 ball
placement, but not open to LV etch.

Wire-bond pads

LBFILL exclusion

Pattern density
Probe pads
-

Fuse Design and Utility Levels


EFUSE
PCFUSE
LVS2

44

200

202

Marking layer for an electrical fuse.


Marking layer for the rectangular PC shape
connecting the cathode end and anode end.
Used to mark the P terminal (in) of the efuse, drawn
in the anode side of the efuse

eFUSE
eFUSE
eFUSE

General Design and Utility Levels


OUTLINE

62

21

CHIPEDGE

62

GUARDRNG

12

71

LOGOBND

62

WVR

62

2
3
4
7
15
17
19
21
31
44
46
61
69
89
91
95
97
117
150
152
200
225
226
227
228

20
20
20
20
20
20
20
20
20
20
20
31
20
120
120
120
120
20
20
20
40
20
20
20
20

102

18

Marker shape to define the edge of cell.


A rectangular shape with chamfered corners
enclosing all chip design shapes, including the chip
guard ring. It is used for merging kerf data.
Marking layer for the chip guard ring drawn to
exactly cover the widest metal in the chip guard
ring. It is used to control the placement of MxHOLE
shapes within the chip guard ring.
Placed over product labels to assist in design rule
checking (DRC).
Marking layer for the waived design rule values
verified during DRC.

Chip guard ring,


chamfer, kerf

Chip guard ring

Labels
Design waivers

xx_NET
xx = RX
xx = T3
xx = NW
xx = PC
xx = M1
xx = M2
xx = M3
xx = M4
xx = M5
xx = M6
xx = M7
xx = SXCUT
xx = LB
xx = BA
xx = BB
xx = BD
xx = BE
xx = FA
xx = FB
xx = BG
xx = 3A
xx = L1
xx = L2
xx = L3
xx = L4

Levels used to label nets.

LVS

Kerf Design and Utility Levels


PROTECT

Used during the automatic kerf merge process


during mask assembly of CP masks; associated

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Kerf design and mask


merge

Spec ID:
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Design Level

GDSII
Layer
No.

GDSII
Data
Type

Description

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Associated with

with preventing mask background overwrite.


PC/RX Design and Utility Levels
Optional level placed over specific areas of the chip
at the customers discretion to prevent the
generation of PCFILL shapes during
GLOBALFOUNDRIES Design Service
Optional level placed over specific areas of the chip
at the customers discretion to prevent the
generation of RXFILL shapes during
GLOBALFOUNDRIES Design Service
Used to fill empty space on PC to meet the
manufacturing process pattern density
requirements.
Used to fill empty space on RX to meet the
manufacturing process pattern density
requirements.

PCEXCLUD

PCFILL exclusion

RXEXCLUD

PCFILL

35

RXFILL

35

BFMOAT

Used to block p-well implants from BFMOAT


regions that isolate regions to create a resistive
path.

BFMOAT devices

T3

Used for triple-well designs (insulated p-well).

Triple wells

84

Design level used in mask process control images


(PCIs) to facilitate mask manufacturing. This level
is merged onto the PC reticle. Used for assist
feature control.

Mask manufacturing

2
7
14
16
18
20
22
32
45
15
17
19
21
31
44
46
89
91
95
97
152
88
90
92
96
157
225
226
227
228
243
244
245
246

84
4
84
84
84
84
84
84
84
84
84
84
84
84
84
84
184
184
184
184
84
184
184
184
184
84
84
84
84
84
84
84
84
84

Design level used in mask PCIs to facilitate mask


manufacturing. Shapes on this level are replaced
with mask PCIs in data preparation. The mask PCIs
are then merged onto the xx reticle.

Mask manufacturing

Design level for ACLV macro holder. Shapes on


this level are replaced with actual ACLV macros in
data preparation

ACLV

RXFILL exclusion

Pattern density

Pattern density

PCI Design and Utility Levels

PCINGAST
xxING,
xx = RX
xx = PC
xx = CA
xx = V1
xx = V2
xx = V3
xx = V4
xx = V5
xx = V6
xx = M1
xx = M2
xx = M3
xx = M4
xx = M5
xx = M6
xx = M7
xx = BA
xx = BB
xx = BD
xx = BE
xx = BG
xx = WT
xx = WA
xx = WB
xx = WD
xx = WE
xx = L1
xx = L2
xx = L3
xx = L4
xx = J0
xx = J1
xx = J2
xx = J3

ACLV macro Design and Utility Levels


MACROACLV

212

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GDSII
Layer
No.

GDSII
Data
Type

Alpha IP

63

63

IP tagging layer for royalty tracking

IP

PADNR

62

20

Reserved for all general texting purpose

Texting

34

Mx blockage layer (x: 1-7)

IP

Design Level

Description

Associated with

IP Design and Utility Level

MxOBS
x=1
x=2
x=3
x=4
x=5
x=6
x=7

15
17
19
21
31
44
46

RF LVS Design and Utility Level


M1_BLKPEX

15

200

Marking layer on RF transistor for LVS purpose

RF transistor

M2_BLKPEX

17

200

Marking layer on RF transistor for LVS purpose

RF transistor

MIM_NI

61

50

Marking layer on MIM for LVS purpose

MIM

DIODE

62

Marking layer on RF well diode for LVS purpose

All RF device

OUTLINE_RF

62

65

Marking layer for RF devices

ALL RF Devices

Marking out inductors outline shape for property


calculation
Shape identifies LB to be modeled ad rflines for
LVS
For marking out drain side of RF transistors whose
source and drain cannot swap
Marking out inductors terminal shape for property
calculation

ALL Inductors and


Transformer

OUTLINE_SPIND

62

123

LBTRANS

69

18

CHRT_RFFET

200

3A_PIN1

200

39

3A_NET1

200

40

Marking out text of inductors label

TRANSMIS

212

21

Shape used to identify transmission lines for LVS

Transformer
RFFET
ALL Inductors and
Transformer
ALL Inductors and
Transformer
Transmission Lines

Notes:
1.
2.

Please add pre- U in layer name which start with a digital in order to meet requirement of some LVS tool environment.
In LVS program code, rename 5VHVFET = U5VHVFET, the gds number and gds type of this layer keep same.

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2.5 Data Preparation Levels


The levels presented in Table 2-4 are generated during data preparation and must not be used by the designer.
Table 2-4. Design Services and Data Preparation Levels
Design Level

Description

Associated with

DIR

Reserved. Used to designate regions for mask inspection.

Mask merge

DNIRxx

Reserved. Used to exclude xx regions from mask inspection.

Mask merge

DNORC

Reserved. Used to prevent optical rule checking.

MxCHEXCL (Mx =
M1-M7, B1-B4, BA,
BB, BD, BE, BG,
L1-L4, EA, EB, FA,
FB, UA, UB, 3A)

Reserved. Used by GLOBALFOUNDRIES Design Services to exclude metal hole shapes


from specific structures on copper wiring levels.

MxHOLE exclusion

MxPLANE (Mx = any


copper metal level)

Reserved. Used by GLOBALFOUNDRIES Design Services to identify very wide copper


lines.

Metal pattern density

NIXxx

Reserved. Custom level removed during Boolean data preparation.

Boolean data
preparation

NONIAGxx

Reserved. Prevents data preparation on xx shapes touching NONIAGxx.

Data preparation

WxEXCLUD (Wx =
W0-W3)

Reserved. Used to inhibit via fill generation from specific regions.

Vias in low-k

VxFILL (Vx = V1-V6,


J0-J3, W0-W3)

Reserved. Used to add via fill shapes to via levels in the low-k dielectric.

Vias in low-k

xxANCHOR

Reserved.

OPC

xxCUS

Reserved. Custom level added during Boolean data preparation.

Boolean data
preparation

xxHOLE (xx = any


copper metal or
copper via level)

Reserved. Used by GLOBALFOUNDRIES Design Services.

Pattern density

xxNOTCH

Reserved.

OPC

xxOPC

Reserved.

OPC

xxOPCHOLE

Reserved.

OPC

Note: xx can be any 40nm-LP defined alphanumeric character combination unless otherwise noted.

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2.6 Kerf Design Levels


Designers must not use the design levels presented in Table 2-5.
Table 2-5. Kerf Design Levels
Design Level

Description

Associated with

FRAME

Reserved. Used during the correct positive (CP) mask assembly automatic kerf merge
associated with shutter blade positioning.

Kerf design and mask


merge

KERFEXCL

Reserved. Used to inhibit pattern fill generation inside certain optical and alignment
structures

Kerf design

KERFxx1

Reserved. Used in the kerf design and merged during mask assembly.

Kerf design

KV

Reserved. Used to open kerf alignment marks.

Kerf design

NEGMKS

Reserved. Used during the correct negative (CN) mask assembly automatic kerf merge
process associated with data extremes.

Kerf design and mask


merge

POSMKS

Reserved. Used during the CP mask assembly automatic kerf merge process associated
with data extremes.

Kerf design and mask


merge

1. xx can be any 40nm-LP defined alphanumeric character combination.

2.7 Reference Levels


The levels presented in Table 2-6 can be used to reference specific metal and via levels within the various
40nm-LP BEOL metallization options. Note that these levels are for reference only and are not to be used for
drawing design elements.
Table 2-6. Reference Levels
Reference Level

Description

LM

Last copper metal level.

LLAST2X

Last 2x metal level (low-k material and TEOS/ FTEOS) in the selected BEOL metallization option (L1-L4 and BA-BG)

MLAST1X

Last 1x (thin) metal level in the selected BEOL metallization option (M3-M7).

MLAST6X

Last 6x metal level in the selected BEOL metallization option (FA, FB)

VLAST1X

Last 1x (thin) via level in the selected BEOL metallization option (V2-V6).

WLAST2X

Last 2x via level (TEOS/FTEOS or low-k material) in the selected BEOL metallization option (WA-WE; J1-J3).

UTM18x

Last ultra thickness 18x metal level (3um) in the selected BEOL metallization option (3A)

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2.8 Mask Alignment Sequence and Metallization Options


See Table 2-1 Mask Levels, Design Levels, and Graphic Design System II (GDSII) Stream Layers and Table 2-2
Nondesign Mask Levels and GDS Stream Layers for alignment options.

2.8.1 General Remarks on BEOL Metallization Options


The 40nm-LP technology permits combinations of 1x (thin), 2x (thick) and 6x (thick) metal layers with the
restrictions listed below. Contact your GLOBALFOUNDRIES technical representative for more information.

There must be three to eight 1x (thin) wiring levels in low-k dielectric.


There can be up to four 2x thick levels low-k and up to five 2x (thick) wiring levels in TEOS/FTEOS, with a
maximum of five (total) 2x (thick) levels. Each via level must be in the same material as the metal level above
it. All ultra low-k and low-k must be under TEOS/FTEOS.
There can be up to two 6x (thick) metal levels
A 2x low-k level can transition to another 2x low-k level or a 6x TEOS/FTEOS level.
The last copper wiring levels must be either a 2x (TEOS/FTEOS) level or a 6x (TEOS/FTEOS) level.
There may be a maximum of ten copper wiring levels.
There must be additional aluminum terminating levels VV (via) and LB (wiring).

2.8.2 BEOL Stack Designation Convention


This stack designation scheme uses some additional characters to denote the thickness and type (low-k,
ultralow-k, and so on) and is limited only to those materials present in the stack. The scheme uses the following
convention:
xBa_yDc__LM
Where:
x = number of metal layers of thickness a, of type B
y = number of metal layers of thickness c, of type D
LM = last metal layer (for technologies that have multiple last metal possibilities)
Thicknesses are represented by 1x, 2x, 6x and so on. Material types in 40nm-LP technologies are Note that
additional options can be created as needed.

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2.8.3 BEOL Metallization Options


Current GLOBALFOUNDRIES 40nm-LP back-end-of-line (BEOL) metallization options are presented in Table 2-7.
Contact your GLOBALFOUNDRIES technical representative with specific questions about metallization options.
Table 2-7. Design Kit Metallization Options (Page 1 of 2)
1

10

11

12

Stack Designation

5L1x_1T6x_LB

5L1x_1T2x_LB

5L1x_2T6x_LB

6L1x_1T6x_LB

6L1x_1T2x_LB

6L1x_2T6x_LB

6L1x_1L2x_1T6x_LB

7L1x_1T6x_LB

7L1x_1T2x_LB

5L1x_1T18x_LB

5L1x_1T6x_1T18x_L
B

6L1x_1T6x_1T18x_L
B

Metallization Option

Total 1x(thin) metal levels in low-k dielectric

Total 2x(thick) metal levels in low-k dielectric

Total 2x(thick) metal levels in TEOS/FTEOS

Total 6x(thick) metal levels in TEOS/FTEOS

Total 18x (3um Thick) metal levels in


TEOS/FTEOS
Total copper metal levels

DV/LV

LB

VV

QT

HT

QE

Electrical fuse
Wire Bond
(Inline and staggered/ flip-chip)

3um Inductor level (in


TEOS/FTEOS)
Metal Insulator Matle (MIM)
Capacitor Option

6x wiring levels
(In TEOS/ FTEOS)

3A
3T

FB

JR

FA
Transitional via from 2x to 6x wiring

GM

Transitional via from 1x to 6x wiring

OT

x
x

BG
WE
BE
WD
2x wiring levels

BD

(In TEOS/ FTEOS)

WB
BB
WA
BA

WT

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Table 2-7. Design Kit Metallization Options (Page 2 of 2)


Metallization Option

M7

V6

10

11

12

L4
J3
L3
2x wiring levels

J2

(In low-k dielectric)

L2
J1
L1

J0

M6
V5

1x wiring levels

M5

V4

M4

V3

M3

V2

M2

V1

M1

Notes: 1. 3A and 3T design rules will be covered in RF devices

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2.8.4 40nm-LP Cross Section


Figure 2-1a and Figure 2-1b show a cross section of one of the 40nm-LP BEOL metallization options:

Five 1x (thin) metal levels and one 6x (thick) metal level in TEOS/FTEOS dielectric.

Figure 2-1a. 40nm-LP Technology Example Cross Section

OT

M5

V4

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Figure 2-1b. 40nm-LP Technology Example Cross Section (including RF design)

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2.9 Design Preparation (Boolean Level Generation)


This section describes one part of the GLOBALFOUNDRIES data preparation operation required for mask build.
The information is for reference only; contact your GLOBALFOUNDRIES technical representative for data
preparation and biasing application details.

2.10 Truth Tables


The truth values presented in Tables 2-9 and 2-10 are provided as a physical design aid for the listed structures.
The truth table values are defined as follows:
0

The design or generated level must not touch the structure.

The design or generated level must cover or match the structure.

The design level does not affect the structure (Table 2-9) or the generated level
might not be present depending on the design levels (Table 2-10)

Note: The listed structures are the only structures permitted in this technology. Use of other structures requires
written approval from the 40nm-LP Device and Characterization Department prior to design submission. Contact
your GLOBALFOUNDRIES technical representative to request approval.
Note: In Table 2-9, the EGC FET entries only apply to 45nm-LP technology. For 40nm-LP, the EGH FET devices
are the only supported EG FETs.

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PC dummy

Medium Oxide

Thick Oxide

Zero-Vt

Medium-Oxide Voltage

Thick-Oxide Voltage

Overdrive Voltage

Vertical PNP Devices

N+

P+

NFET-in-N-Well Capacitor

PFET-in-P-Well Capacitor

Highly-Resistive Substrate

Electrical PC Fuse

Bipolar Transistor

ESD Implant

N-Well Resistor

Nwell over Active Resistor


unsilicided Polysilicon
Resistor
unsilicided Diffusion Resistor

Salicide Poly Resistor

Salicide Diffusion Resistor

Tie Down Diode Marker

SRAM Cell Marker

SRAM Marker

Pass Gate

ESD Marker

HCVNCAP Marker

APMOM Marker

5V LDMOS

PCFILL

EG

DG

ZVT

EGV

DGV

OVERDRIVE

VPNP

JX

JZ

OP

SBLK

NCAP_OR VAR3

PCAP_OR VAR3

BFMOAT

EFUSE

BIPOLAR

ED

NWRES

BPNWR

PRES

DRES

POLY_SAL

DIFF_SAL

TIEDOWN

CELLSNR

RF_SRAM

AD

ESD_xxx1

ESDSCR_HBM

RXEXCLUD

HCVNCAP

VNCAPHV

5VHVFET

NOHALO

NOSD

Silicide Block

Polysilicon
PC

PR

NR

HVT_OR2

High-Vt

Superlow-Vt
IY

GY

SLVT_OR2

Low-Vt
LW

XW

N-Well
N-band for isolated P-well
(triple well)
NW

LVT_OR2

RX dummy
RXFILL

T3

Active Area
RX

Structure

Table 2-9. Design Truth Table

Superlow-V
1 0 0 x 0 0 0 1 1 0 0 0 0 1 0 0
t NFET

Superlow-V
1 0 1 x 0 0 0 1 0 1 0 0 0 1 0 0
t PFET

Low-Vt
NFET

1 0 0 x 1 1 0 0 0 0 0 0 0 1 0 0

Low-Vt
PFET H

1 0 1 x 1 0 1 0 0 0 0 0 0 1 0 0

Regular-Vt
1 0 0 x 0 0 0 0 0 0 0 0 0 1 0 0
NFET

Regular-Vt
1 0 1 x 0 0 0 0 0 0 0 0 0 1 0 0
PFET

High-Vt
NFET

1 0 0 x 0 0 0 0 0 0 1 1 0 1 0 0

High-Vt
PFET

1 0 1 x 0 0 0 0 0 0 1 0 1 1 0 0

1.8 V HSIO
1 0 0 x 0 0 0 0 0 0 0 0 0 1 0 1
NFET

1.8 V HSIO
1 0 1 x 0 0 0 0 0 0 0 0 0 1 0 1
PFET

1.5 V HSIO
1 0 0 x 0 0 0 0 0 0 0 0 0 1 0 1
NFET

1.5 V HSIO
1 0 1 x 0 0 0 0 0 0 0 0 0 1 0 1
PFET

1.8 V DG
I/O NFET

1 0 0 x 0 0 0 0 0 0 0 0 0 1 0 0

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PC dummy

Medium Oxide

Thick Oxide

Zero-Vt

Medium-Oxide Voltage

Thick-Oxide Voltage

Overdrive Voltage

Vertical PNP Devices

N+

P+

NFET-in-N-Well Capacitor

PFET-in-P-Well Capacitor

Highly-Resistive Substrate

Electrical PC Fuse

Bipolar Transistor

ESD Implant

N-Well Resistor

Nwell over Active Resistor


unsilicided Polysilicon
Resistor
unsilicided Diffusion Resistor

Salicide Poly Resistor

Salicide Diffusion Resistor

Tie Down Diode Marker

SRAM Cell Marker

SRAM Marker

Pass Gate

ESD Marker

HCVNCAP Marker

APMOM Marker

5V LDMOS

EG

DG

ZVT

EGV

DGV

OVERDRIVE

VPNP

JX

JZ

OP

SBLK

NCAP_OR VAR3

PCAP_OR VAR3

BFMOAT

EFUSE

BIPOLAR

ED

NWRES

BPNWR

PRES

DRES

POLY_SAL

DIFF_SAL

TIEDOWN

CELLSNR

RF_SRAM

AD

ESD_xxx1

ESDSCR_HBM

RXEXCLUD

HCVNCAP

VNCAPHV

5VHVFET

NOHALO

NOSD

Silicide Block

Polysilicon

PCFILL

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PC

PR

NR

HVT_OR2

High-Vt

Superlow-Vt
IY

GY

SLVT_OR2

Low-Vt
LW

XW

N-Well
N-band for isolated P-well
(triple well)
NW

LVT_OR2

RX dummy
RXFILL

T3

Active Area
RX

Structure

Spec ID:
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1.8 V DG
I/O PFET

1 0 1 x 0 0 0 0 0 0 0 0 0 1 0 0

2.5 V DG
I/O NFET

1 0 0 x 0 0 0 0 0 0 0 0 0 1 0 0

2.5 V DG
I/O PFET

1 0 1 x 0 0 0 0 0 0 0 0 0 1 0 0

3.3 V DG
I/O NFET

1 0 0 x 0 0 0 0 0 0 0 0 0 1 0 0

3.3 V DG
I/O PFET

1 0 1 x 0 0 0 0 0 0 0 0 0 1 0 0

Triple-well
NFET T3
H/V

1 0 0 1 x x x x x x x x x 1 0 x

Thin-oxide
zero-Vt
NFET

1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

Medium-oxi
de zero-Vt 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
NFET

Thick-oxide
zero-Vt
1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
NFET

1.8V
Medium-Ox
1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1
ide 5V
LDNMOS

GLOBALFOUNDRIES Confidential

N-Well
N-band for isolated P-well
(triple well)

NW

0
0
0
0
x
x
1
0
0

3.3V
Thick-Oxid
1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0
e 5V
LDNMOS
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
1
0
0

3.3V
Thick-Oxid
1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
e 5V
LDPMOS
1
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
1
0
0

N+ junction 1 0 0 0 x x x x x x x x x 0 0 x
0
x
x
x
x
x
1
0
0
x
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
0
x
x
x
0
0
0

N+ junction
1 0 0 1 x x x x x x x x x 0 0 x
T3
x
x
x
x
x
x
1
0
0
x
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
0
x
x
x
0
0
0

N+junction
1 0 0 0 x x x x x x x x x 0 0 0
DG
1
x
x
x
x
x
1
0
0
x
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
0
x
x
x
0
0
0

High-Vt

Superlow-Vt

0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
1
0
0

Silicide Block

NOSD

5V LDMOS

NOHALO

APMOM Marker

5VHVFET

HCVNCAP Marker

VNCAPHV

HCVNCAP

RXEXCLUD

ESDSCR_HBM

ESD Marker

Pass Gate

ESD_xxx1

SRAM Marker

AD

RF_SRAM

SRAM Cell Marker

Tie Down Diode Marker

CELLSNR

Salicide Diffusion Resistor

TIEDOWN

DIFF_SAL

Salicide Poly Resistor

POLY_SAL

DRES

Nwell over Active Resistor


unsilicided Polysilicon
Resistor
unsilicided Diffusion Resistor

2.5V
Thick-Oxid
1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
e 5V
LDPMOS
PRES

N-Well Resistor

BPNWR

NWRES

ESD Implant

Bipolar Transistor

ED

Electrical PC Fuse

BIPOLAR

EFUSE

Highly-Resistive Substrate

PFET-in-P-Well Capacitor

BFMOAT

NFET-in-N-Well Capacitor

PCAP_OR VAR3

NCAP_OR VAR3

SBLK

OP

P+

N+

JZ

Vertical PNP Devices

JX

VPNP

Overdrive Voltage

Thick-Oxide Voltage

OVERDRIVE

DGV

Medium-Oxide Voltage

Zero-Vt

EGV

Thick Oxide

ZVT

Medium Oxide

DG

2.5V
Thick-Oxid
1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0
e 5V
LDNMOS
PC dummy

EG

Polysilicon

PCFILL

1.8V
Medium-Ox
1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1
ide 5V
LDPMOS
PC

PR

NR

HVT_OR2

IY

GY

SLVT_OR2

LW

XW

LVT_OR2

Low-Vt

RX dummy

RXFILL
T3

Active Area

RX

Structure

Spec ID:
Revision:
Page:
[YI-DM00085]
[14]
42 of 330

GLOBALFOUNDRIES Confidential

N-Well
N-band for isolated P-well
(triple well)

NW

x
x
0
x
x
x
0
0
0

N-well
contact
1 0 1 0 x x x x x x x x x 0 0 x
x
x
x
x
x
0
1
0
0
0
x
0
0
0
x
0
0
0
0
0
0
0
0
x
x
0
0
0
x
x
x
0
0
0

Substrate
contact
1 0 0 0 x x x x x x x x x 0 0 x
x
x
x
x
x
x
0
1
0
0
0
x
0
0
x
0
0
0
0
0
0
0
0
x
x
0
0
0
x
x
x
0
0
0

P+ junction 1 0 1 0 x x x x x x x x x 0 0 x
0
x
x
x
x
0
0
1
0
x
0
0
0
0
x
0
0
0
0
0
0
0
0
x
x
x
x
0
x
x
x
0
0
0

P+junction
1 0 1 0 x x x x x x x x x 0 0 0
DG
1
x
x
x
x
0
0
1
0
x
0
0
0
0
x
0
0
0
0
0
0
0
0
x
x
x
x
0
x
x
x
0
0
0

P+ tie down
1 0 1 0 x x x x x x x x x 0 0 x
diode
0
x
x
x
x
0
0
1
0
x
0
0
0
0
x
0
0
0
0
0
0
0
1
x
x
x
x
0
x
x
x
0
0
0

High-Vt

Superlow-Vt

x
x
x
1
0
0
x
0
0
0
0
0
0
0
0
0
0
0
0
1
x
x
x
x
0
x
x
x
0
0
0

Silicide Block

NOSD

5V LDMOS

NOHALO

APMOM Marker

5VHVFET

HCVNCAP Marker

VNCAPHV

HCVNCAP

RXEXCLUD

ESDSCR_HBM

ESD Marker

Pass Gate

ESD_xxx1

SRAM Marker

AD

RF_SRAM

SRAM Cell Marker

Tie Down Diode Marker

CELLSNR

Salicide Diffusion Resistor

TIEDOWN

DIFF_SAL

Salicide Poly Resistor

POLY_SAL

DRES

Nwell over Active Resistor


unsilicided Polysilicon
Resistor
unsilicided Diffusion Resistor

N+ tie down
1 0 0 0 x x x x x x x x x 0 0 0
diode DG
PRES

N-Well Resistor

BPNWR

NWRES

ESD Implant

Bipolar Transistor

ED

Electrical PC Fuse

BIPOLAR

EFUSE

Highly-Resistive Substrate

PFET-in-P-Well Capacitor

BFMOAT

NFET-in-N-Well Capacitor

PCAP_OR VAR3

NCAP_OR VAR3

SBLK

OP

P+

N+

JZ

Vertical PNP Devices

JX

VPNP

Overdrive Voltage

Thick-Oxide Voltage

OVERDRIVE

DGV

Medium-Oxide Voltage

Zero-Vt

EGV

Thick Oxide

ZVT

Medium Oxide

DG

N+ tie down
1 0 0 1 x x x x x x x x x 0 0 x
diode T3
PC dummy

EG

Polysilicon

PCFILL

N+ tie down
1 0 0 0 x x x x x x x x x 0 0 x
diode
PC

PR

NR

HVT_OR2

IY

GY

SLVT_OR2

LW

XW

LVT_OR2

Low-Vt

RX dummy

RXFILL
T3

Active Area

RX

Structure

Spec ID:
Revision:
Page:
[YI-DM00085]
[14]
43 of 330

GLOBALFOUNDRIES Confidential

N-Well
N-band for isolated P-well
(triple well)

NW

x
x
0
x
x
x
x
0
0

Nwell-psub x x 1 0 x x x x x x x x x x x x
x
x
x
x
x
0
x
x
x
x
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
0
0
x
x
x
x
0
0

Pwell-dnwe
x x 0 1 x x x x x x x x x x x x
ll
x
x
x
x
x
0
x
x
x
x
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
0
0
x
x
x
x
0
0

N-well
resistor
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
x
0
1
x
x
0
0
0

N-well
resistor
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
over Active
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0

Unsalicided
P+ poly
0 0 x x 0 0 0 0 0 0 0 0 0 1 0 x
resistor
x
0
x
x
x
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
x
0
x
x
x
0
0
0

High-Vt

Superlow-Vt

x
x
0
0
1
0
x
0
0
0
0
x
0
0
0
0
0
0
0
1
x
x
x
x
0
x
x
x
0
0
0

Silicide Block

NOSD

5V LDMOS

NOHALO

APMOM Marker

5VHVFET

HCVNCAP Marker

VNCAPHV

HCVNCAP

RXEXCLUD

ESDSCR_HBM

ESD Marker

Pass Gate

ESD_xxx1

SRAM Marker

AD

RF_SRAM

SRAM Cell Marker

Tie Down Diode Marker

CELLSNR

Salicide Diffusion Resistor

TIEDOWN

DIFF_SAL

Salicide Poly Resistor

POLY_SAL

DRES

Nwell over Active Resistor


unsilicided Polysilicon
Resistor
unsilicided Diffusion Resistor

Dnwell-psu
x x x 1 x x x x x x x x x x x x
b
PRES

N-Well Resistor

BPNWR

NWRES

ESD Implant

Bipolar Transistor

ED

Electrical PC Fuse

BIPOLAR

EFUSE

Highly-Resistive Substrate

PFET-in-P-Well Capacitor

BFMOAT

NFET-in-N-Well Capacitor

PCAP_OR VAR3

NCAP_OR VAR3

SBLK

OP

P+

N+

JZ

Vertical PNP Devices

JX

VPNP

Overdrive Voltage

Thick-Oxide Voltage

OVERDRIVE

DGV

Medium-Oxide Voltage

Zero-Vt

EGV

Thick Oxide

ZVT

Medium Oxide

DG

Triple-well
1 0 0 1 x x x x x x x x x 0 0 x
contact T3
PC dummy

EG

Polysilicon

PCFILL

P+ tie down
1 0 1 0 x x x x x x x x x 0 0 0
diode DG
PC

PR

NR

HVT_OR2

IY

GY

SLVT_OR2

LW

XW

LVT_OR2

Low-Vt

RX dummy

RXFILL
T3

Active Area

RX

Structure

Spec ID:
Revision:
Page:
[YI-DM00085]
[14]
44 of 330

GLOBALFOUNDRIES Confidential

PC dummy

Medium Oxide

Thick Oxide

Zero-Vt

Medium-Oxide Voltage

Thick-Oxide Voltage

Overdrive Voltage

Vertical PNP Devices

N+

P+

NFET-in-N-Well Capacitor

PFET-in-P-Well Capacitor

Highly-Resistive Substrate

Electrical PC Fuse

Bipolar Transistor

ESD Implant

N-Well Resistor

Nwell over Active Resistor


unsilicided Polysilicon
Resistor
unsilicided Diffusion Resistor

Salicide Poly Resistor

Salicide Diffusion Resistor

Tie Down Diode Marker

SRAM Cell Marker

SRAM Marker

Pass Gate

ESD Marker

HCVNCAP Marker

APMOM Marker

5V LDMOS

EG

DG

ZVT

EGV

DGV

OVERDRIVE

VPNP

JX

JZ

OP

SBLK

NCAP_OR VAR3

PCAP_OR VAR3

BFMOAT

EFUSE

BIPOLAR

ED

NWRES

BPNWR

PRES

DRES

POLY_SAL

DIFF_SAL

TIEDOWN

CELLSNR

RF_SRAM

AD

ESD_xxx1

ESDSCR_HBM

RXEXCLUD

HCVNCAP

VNCAPHV

5VHVFET

NOHALO

NOSD

Silicide Block

Polysilicon

PCFILL

[YI-DM00085]
[14]
45 of 330

PC

PR

NR

HVT_OR2

High-Vt

Superlow-Vt
IY

GY

SLVT_OR2

Low-Vt
LW

XW

N-Well
N-band for isolated P-well
(triple well)
NW

LVT_OR2

RX dummy
RXFILL

T3

Active Area
RX

Structure

Spec ID:
Revision:
Page:

Unsalicided
N+ poly
0 0 x x 0 0 0 0 0 0 0 0 0 1 0 x
resistor

Unsalicided
P+ diff
1 0 1 x 0 0 0 0 0 0 0 0 0 0 0 0
resistor

Unsalicided
N+ diff
1 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0
resistor

Unsalicided
N+ diff
1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
resistor T3

Precision
P+ poly
resistor

0 0 x x 0 0 0 0 0 0 0 0 0 1 0 x

BFMOAT

0 0 0 0 x x x x x x x x x 0 0 x

Salicided
P+ Poly
resistor

0 0 x x 0 0 0 0 0 0 0 0 0 1 0 x

Salicided
N+ Poly
resistor

0 0 x x 0 0 0 0 0 0 0 0 0 1 0 x

Salicided
P+ diff
resistor

1 0 1 x 0 0 0 0 0 0 0 0 0 0 0 0

GLOBALFOUNDRIES Confidential

N-Well
N-band for isolated P-well
(triple well)

NW

0
0
0
0
0
0
x
x
x
0
0
0

Medium-oxi
1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1
de NCAP
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0

Thick-oxide
1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0
NCAP
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0

Thin-oxide
PCAP
1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0

Medium-oxi
1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1
de PCAP
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0

Thick-oxide
1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0
PCAP
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0

High-Vt

Superlow-Vt

0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
x
0
x
x
x
0
0
0

Silicide Block

NOSD

5V LDMOS

NOHALO

APMOM Marker

5VHVFET

HCVNCAP Marker

VNCAPHV

HCVNCAP

RXEXCLUD

ESDSCR_HBM

ESD Marker

Pass Gate

ESD_xxx1

SRAM Marker

AD

RF_SRAM

SRAM Cell Marker

Tie Down Diode Marker

CELLSNR

Salicide Diffusion Resistor

TIEDOWN

DIFF_SAL

Salicide Poly Resistor

1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0
POLY_SAL

Thin-oxide
NCAP
DRES

Nwell over Active Resistor


unsilicided Polysilicon
Resistor
unsilicided Diffusion Resistor

PRES

N-Well Resistor

BPNWR

NWRES

ESD Implant

Bipolar Transistor

ED

Electrical PC Fuse

BIPOLAR

EFUSE

Highly-Resistive Substrate

PFET-in-P-Well Capacitor

BFMOAT

NFET-in-N-Well Capacitor

PCAP_OR VAR3

NCAP_OR VAR3

SBLK

OP

P+

N+

JZ

Vertical PNP Devices

JX

VPNP

Overdrive Voltage

Thick-Oxide Voltage

OVERDRIVE

DGV

Medium-Oxide Voltage

Zero-Vt

EGV

Thick Oxide

ZVT

1 0 1 0 x x x x x x x x x 0 0 x
Medium Oxide

N-well
substrate
cap
DG

PC dummy

EG

Polysilicon

1 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0
PCFILL

Salicided
N+ diff
resistor
PC

PR

NR

HVT_OR2

IY

GY

SLVT_OR2

LW

XW

LVT_OR2

Low-Vt

RX dummy

RXFILL
T3

Active Area

RX

Structure

Spec ID:
Revision:
Page:
[YI-DM00085]
[14]
46 of 330

GLOBALFOUNDRIES Confidential

N-Well
N-band for isolated P-well
(triple well)

NW

0
0
0
x
0
0
x
0
0
0
0
0

HCVNCAP x x x x x x x x x x x x x x x x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
0
0
x
0
0
x
1
0
x
0
0

APMOM
x x x x x x x x x x x x x x x x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
0
0
x
0
0
x
0
1
x
0
0

eFuse
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
0
0
0
0
0
x
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
0

ESD NFET 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x
x
0
x
x
x
x
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
x
0
0
0
0
0

ESD NFET
w/ ESD
1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x
IMPLANT
x
0
x
x
x
x
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
x
0
0
0
0
0

High-Vt

Superlow-Vt

0
0
1
0
1
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0

Silicide Block

NOSD

5V LDMOS

NOHALO

APMOM Marker

5VHVFET

HCVNCAP Marker

VNCAPHV

HCVNCAP

RXEXCLUD

ESDSCR_HBM

ESD Marker

Pass Gate

ESD_xxx1

SRAM Marker

AD

RF_SRAM

SRAM Cell Marker

Tie Down Diode Marker

CELLSNR

Salicide Diffusion Resistor

TIEDOWN

DIFF_SAL

Salicide Poly Resistor

x x x x x x x x x x x x x x x x
POLY_SAL

Inductor
DRES

Nwell over Active Resistor


unsilicided Polysilicon
Resistor
unsilicided Diffusion Resistor

PRES

N-Well Resistor

BPNWR

NWRES

ESD Implant

Bipolar Transistor

ED

Electrical PC Fuse

BIPOLAR

EFUSE

Highly-Resistive Substrate

PFET-in-P-Well Capacitor

BFMOAT

NFET-in-N-Well Capacitor

PCAP_OR VAR3

NCAP_OR VAR3

SBLK

OP

P+

N+

JZ

Vertical PNP Devices

JX

VPNP

Overdrive Voltage

Thick-Oxide Voltage

OVERDRIVE

DGV

Medium-Oxide Voltage

Zero-Vt

EGV

Thick Oxide

ZVT

1 0 0 1 0 0 0 0 0 0 0 0 0 0 x 0
Medium Oxide

Vertical
NPN
bipolar
DG

PC dummy

EG

Polysilicon

1 0 1 0 0 0 0 0 0 0 0 0 0 0 x 0
PCFILL

Vertical
PNP
bipolar
PC

PR

NR

HVT_OR2

IY

GY

SLVT_OR2

LW

XW

LVT_OR2

Low-Vt

RX dummy

RXFILL
T3

Active Area

RX

Structure

Spec ID:
Revision:
Page:
[YI-DM00085]
[14]
47 of 330

GLOBALFOUNDRIES Confidential

N-Well
N-band for isolated P-well
(triple well)

NW

0
0
0
1
0
x
0
0
0
0
0

ESD
N+/PW
diode
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
x
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
x
0
0
0
0
0

ESD SCR
1 x 1 0 0 0 0 0 0 0 0 0 0 0 x 0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
0
0
0
0
0

ESD SCR
T3
1 x 0 1 0 0 0 0 0 0 0 0 0 0 x 0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
0
0
0
0
0

ESD
vertical
PNP
bipolar
1 x 1 0 0 0 0 0 0 0 0 0 0 0 x 0
0
0
0
0
0
x
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
x
0
0
0
0
0

ESD
vertical
NPN
bipolar T3
1 x 0 1 0 0 0 0 0 0 0 0 0 0 x 0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
x
0
0
0
0
0

High-Vt

Superlow-Vt

x
x
x
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
x
0
0
0
0
0

Silicide Block

NOSD

5V LDMOS

NOHALO

APMOM Marker

5VHVFET

HCVNCAP Marker

VNCAPHV

HCVNCAP

RXEXCLUD

ESDSCR_HBM

ESD Marker

Pass Gate

ESD_xxx1

SRAM Marker

AD

RF_SRAM

SRAM Cell Marker

Tie Down Diode Marker

CELLSNR

Salicide Diffusion Resistor

TIEDOWN

DIFF_SAL

Salicide Poly Resistor

POLY_SAL

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRES

ESD N+
junction
Nwell over Active Resistor
unsilicided Polysilicon
Resistor
unsilicided Diffusion Resistor

PRES

N-Well Resistor

BPNWR

NWRES

ESD Implant

Bipolar Transistor

ED

Electrical PC Fuse

BIPOLAR

EFUSE

Highly-Resistive Substrate

PFET-in-P-Well Capacitor

BFMOAT

NFET-in-N-Well Capacitor

PCAP_OR VAR3

NCAP_OR VAR3

SBLK

OP

P+

N+

JZ

Vertical PNP Devices

JX

VPNP

Overdrive Voltage

Thick-Oxide Voltage

OVERDRIVE

DGV

Medium-Oxide Voltage

Zero-Vt

EGV

Thick Oxide

ZVT

Medium Oxide

1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 x
DG

ESD
triple-well
NFET T3
PC dummy

EG

Polysilicon

PCFILL

ESD PFET 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 x
PC

PR

NR

HVT_OR2

IY

GY

SLVT_OR2

LW

XW

LVT_OR2

Low-Vt

RX dummy

RXFILL
T3

Active Area

RX

Structure

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PC dummy

Medium Oxide

Thick Oxide

Zero-Vt

Medium-Oxide Voltage

Thick-Oxide Voltage

Overdrive Voltage

Vertical PNP Devices

N+

P+

NFET-in-N-Well Capacitor

PFET-in-P-Well Capacitor

Highly-Resistive Substrate

Electrical PC Fuse

Bipolar Transistor

ESD Implant

N-Well Resistor

Nwell over Active Resistor


unsilicided Polysilicon
Resistor
unsilicided Diffusion Resistor

Salicide Poly Resistor

Salicide Diffusion Resistor

Tie Down Diode Marker

SRAM Cell Marker

SRAM Marker

Pass Gate

ESD Marker

HCVNCAP Marker

APMOM Marker

5V LDMOS

EG

DG

ZVT

EGV

DGV

OVERDRIVE

VPNP

JX

JZ

OP

SBLK

NCAP_OR VAR3

PCAP_OR VAR3

BFMOAT

EFUSE

BIPOLAR

ED

NWRES

BPNWR

PRES

DRES

POLY_SAL

DIFF_SAL

TIEDOWN

CELLSNR

RF_SRAM

AD

ESD_xxx1

ESDSCR_HBM

RXEXCLUD

HCVNCAP

VNCAPHV

5VHVFET

NOHALO

NOSD

Silicide Block

Polysilicon

PCFILL

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PC

PR

NR

HVT_OR2

High-Vt

Superlow-Vt
IY

GY

SLVT_OR2

Low-Vt
LW

XW

N-Well
N-band for isolated P-well
(triple well)
NW

LVT_OR2

RX dummy
RXFILL

T3

Active Area
RX

Structure

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SBLK n
resistor4

1 0 0 x 0 0 0 0 0 0 0 0 0 x x x

SBLK n
resistor w/
ESD
implant4

1 0 0 x 0 0 0 0 0 0 0 0 0 x x x

SBLK p
resistor4

1 0 1 0 0 0 0 0 0 0 0 0 0 x x x

Notes:
Use ESD_HBM for Human Body Model (HBM) structures and ESD_CDM for charged-device model (CDM) structures. In Cadence, the purpose layer for ESD is dev.
Either LVT or XW/LW can be used, either HVT or NR/PR design can be used, and either SLVT or GY/IY design can be used. Either or both can appear in a given design, but should not coincide
or overlap.
3. Either NCAP/PCAP or VAR can be used as the marker. Either or both can appear in a given design, but should not coincide or overlap.
These devices should not interact with layers ESDSH_STK_DEVMARK and ESDSH_SIN_DEVMARK
1.
2.

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Table 2-10. Data Preparation Truth Table

SMT Strain
Open
SM

NFET

Open
ZP

NFET

Polysilcon

DG/IO + well implant


Open
JP

PFET

Open
JN

NFET

EG/IO + well implant


Open
IP

PFET

Open
IN

NFET

Open
DF

PFET

Open
DE

NFET

Thick-oxide

Medium-oxide
Open
GP

PFET

Open
GN

NFET

Open
PV

PFET H

Open
NV

NFET
H

SRAM

Regular-Vt
Open
CV

PFET

Blocked
BV

NFET

Regular-Vt

Well Implant
NFET
Open
N3

NFET
Blocked
BF

Device

Halo/Extension Implant

Superlow-Vt NFET

Superlow-Vt PFET

Low-Vt NFET

Low-Vt PFET

Regular-Vt NFET

Regular-Vt PFET

High-Vt NFET

High-Vt PFET

1.8 V HSIO NFET

1.8 V HSIO PFET

1.5 V HSIO NFET

1.5 V HSIO PFET

1.8 V DG I/O NFET

1.8 V DG I/O PFET

2.5 V DG I/O NFET

2.5 V DG I/O PFET

3.3 V DG I/O NFET

3.3 V DG I/O PFET

Thin-oxide zero-Vt NFET

Medium-oxide zero-Vt
NFET

Thick-oxide zero-Vt NFET

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SMT Strain
Open
SM

NFET

Open
ZP

NFET

Polysilcon

DG/IO + well implant


Open
JP

PFET

Open
JN

NFET

EG/IO + well implant


Open
IP

PFET

Open
IN

NFET

Open
DF

PFET

Open
DE

NFET

Thick-oxide

Medium-oxide
Open
GP

PFET

Open
GN

NFET

Open
PV

PFET H

Open
NV

NFET
H

SRAM

Regular-Vt
Open
CV

PFET

Blocked
BV

NFET

Regular-Vt

Well Implant
NFET
Open
N3

NFET
Blocked
BF

Device

Halo/Extension Implant

Triple-well NFET T3 H/V

1.8V Medium-Oxide 5V
LDNMOS

1.8V Medium-Oxide 5V
LDPMOS

2.5V Thick-Oxide 5V
LDNMOS

2.5V Thick-Oxide 5V
LDPMOS

3.3V Thick-Oxide 5V
LDNMOS

3.3V Thick-Oxide 5V
LDPMOS

N+ junction

N+ junction T3

N+ junction DG

N+ tie down diode

N+ tie down diode T3

N+ tie down diode DG

N-well contact

Substrate contact

P+ junction

P+ junction DG

P+ tie down diode

P+ tie down diode DG

Triple-well contact T3

Dnwell-psub

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SMT Strain
Open
SM

NFET

Open
ZP

NFET

Polysilcon

DG/IO + well implant


Open
JP

PFET

Open
JN

NFET

EG/IO + well implant


Open
IP

PFET

Open
IN

NFET

Open
DF

PFET

Open
DE

NFET

Thick-oxide

Medium-oxide
Open
GP

PFET

Open
GN

NFET

Open
PV

PFET H

Open
NV

NFET
H

SRAM

Regular-Vt
Open
CV

PFET

Blocked
BV

NFET

Regular-Vt

Well Implant
NFET
Open
N3

NFET
Blocked
BF

Device

Halo/Extension Implant

Nwell-psub

Pwell-dnwell

N-well resistor

Nwell resistor over Active

OP N+ poly resistor

OP P+ poly resistor

OP N+ diff resistor

OP N+ diff resistor T3

OP P+diff resistor

Precision P+ poly resistor

BFMOAT

Salicided P+Poly resistor

Salicided N+Poly resistor

Salicided N+diff resistor

Salicided P+diff resistor

N-well substrate cap

Thin-oxide NCAP

Medium-oxide NCAP

Thick-oxide NCAP

Thin-oxide PCAP

Medium-oxide PCAP T3

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SMT Strain
Open
SM

NFET

Open
ZP

NFET

Polysilcon

DG/IO + well implant


Open
JP

PFET

Open
JN

NFET

EG/IO + well implant


Open
IP

PFET

Open
IN

NFET

Open
DF

PFET

Open
DE

NFET

Thick-oxide

Medium-oxide
Open
GP

PFET

Open
GN

NFET

Open
PV

PFET H

Open
NV

NFET
H

SRAM

Regular-Vt
Open
CV

PFET

Blocked
BV

NFET

Regular-Vt

Well Implant
NFET
Open
N3

NFET
Blocked
BF

Device

Halo/Extension Implant

Thick-oxide PCAP T3

Vertical PNP Bipolar

Vertical NPN bipolar

Inductor

HCVNCAP

APMOM

eFuse

ESD NFET

ESD NFET w/ ESD


IMPLANT

ESD PFET

ESD Triple-Well NFET T3

ESD N+ junction

ESD N+/PW Diode

ESD SCR

ESD SCR T3

ESD vertical PNP bipolar

ESD vertical NPN bipolar


T3

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3. Physical Design Rules


The following notes apply to physical design rule Tables 3-4 through, beginning:
1. All design rule values are given in microns (m) unless otherwise specified.
2. GLOBALFOUNDRIES recommended design rules end with the letter R (for example, Rule 41R); designers
are strongly encouraged to follow the recommended rules. In addition, designers should use design
dimensions greater than the stated minimum when possible, unless they result in increased chip size or
decreased performance. Note that recommended design rules are not verified in default design rule checking
(DRC), but they can be verified using design for manufacturability (DFM) DRC. See 40nm-LP Section 4 Design
for Manufacturability for more information.
3. Design rules ending with _or (for example, Rule 507_or) are described as a set of rules in which only one of
the rules must be followed.
4. In the design rule descriptions that follow, RX denotes the active silicon region (that is, source, drain,
field-effect transistor [FET] channel, capacitor, and so forth), also known as the diffusion region.

3.1 Design Rule Syntax


In Sections 3.1.1 through 3.1.5, the single-letter abbreviation denoted in boldfaced type represents a shape on the
corresponding design level. For example, A refers to a shape on design level A. Many of these syntax definitions
are illustrated in Figures 3-1 through 3-10, beginning.
The following design rule description structure is used when possible: first level or levels (condition A, B, and so
forth), measurement, second level or levels (condition A, B, and so forth). Mandatory elements are in boldfaced
type.
Note: Exact, exempt, intersect, permitted, prohibited, abutting, parallel edges, and opposite or remaining sides are
presumed to be understood through common use and are not defined.

3.1.1 Multiple Levels per Rule


A operator (B1, B2, B3)

Assigns level A to every level B: (A operator B1), (A operator B2), (A operator


B3).

(A1, A2, A3) operator B

Assigns every level A to level B: (A1 operator B), (A2 operator B), (A3 operator
B).

(A1, A2, A3) operator (B1,


B2, B3)
or (A1A3) operator (B1B3)

Assigns the rule on a one-to-one basis: (A1 operator B1), (A2 operator B2),
(A3 operator B3).

3.1.2 Electrical Selection Functions


Different or same net

Electrically based connectivity using all levels.

Different or same net using


(A, B, C, and so forth)

Shape-based connectivity checked using (A, B, C, and so forth).

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3.1.3 Unary Operators


3.1.3.1 Dimension
A length

The distance between the inside edges of an individual shape. Length is the
longer side of the shape measured between parallel edges or edges that form an
angle of less than 90.

A width

The distance between the inside edges of an individual shape. Width is the
shorter side of the shape measured between parallel edges or edges that form an
angle of less than 90.

A width with run length

A length and width

The distance between two inside edges running in parallel; used for measuring
the width between two parallel edges. This syntax applies to one or two shapes
only (see Figure 3-1).
Shape A is a square with equal length and width.

A gate length

The distance from (PC edge to PC edge) over RX (see Figure 3-1).

A gate width

The distance from (RX edge to RX edge) over PC (see Figure 3-1).

A gate end

Either RX edge of a gate (see Figure 3-1).

A gate side

Either PC edge of a gate (see Figure 3-1).

B edge with span X


C notch

The internal distance X from the inside of an edge segment B to the inside of the
opposite edge. (See Figure 3-1.)
The distance between the outside edges of an individual shape.

C notch between parallel

The distance between parallel outside edges of an individual shape.

C space and notch

The distance between all outside edges of all shapes on level C.

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Figure 3-1. Design Rule Syntax Dimension Definitions

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3.1.3.2 Area
A area

The area of each individual shape.

B enclosed area

The space between the outside edges of one or more individual shapes (see
white area in Figure 3-2).

Figure 3-2. Design Rule Syntax Area Definitions

3.1.3.3 Density
A density

The ratio of the area of all shapes on level A within a window divided by the area of the
window.

A density with tiling


within B

Pattern density checks use the following tiling components:

Box size. The dimensions of the tile.


Step increment. Tiles are stepped in increments equal to half the tile
dimension.
Step-back requirement. For (least-enclosing rectangle B) width box size,
incomplete tiles at the edge of B must be stepped back within the
least-enclosing rectangle B. For (least-enclosing rectangle B) width < box
size, the density must be calculated as the ratio of the total area of A within
the intersection of the checking box and B divided by the area of the
intersection of the checking box and B.
Irregular edges. For checking boxes not completely covered by B that meet
the step-back requirement, the density must be calculated as the ratio of the
total area of A within the intersection of the checking box and B divided by the
area of the intersection of the checking box and B.

3.1.3.4 Geometry and Orientation


A must be centered

The center point of a shape; most commonly used in the center of a circle or
octagon.

A must be orthogonal

All edges of shapes on level A must be parallel to the x and y-axes.

A must be an orthogonal
rectangle

Shape A is a rectangle with all edges parallel to the x and y-axes.

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3.1.4 Binary Operators


3.1.4.1 Spacing
C distance to D

P space to Q

The distance from any portion of C to D. Used for latchup checks only (see
Figure 3-3).
Distance between all outside edges of shape P and outside edges of shape Q;
abutting is prohibited.
Note: Space to does not prevent shapes P and Q from intersecting;
prohibited over prevents this.

R space to S run length

C space to D with
abutting permitted when
run length is n m
P space to adjacent Q

The distance between two outside edges running in parallel; used for
measuring the space between two parallel edges. This applies even if the
shapes turn, as long as the minimum space between them does not effectively
change. An unbent common run refers to the distance of run segments that
do not turn. This syntax applies to one or two shapes only (see Figure 3-3).
See P space to Q above; zero spacing is permitted. Abutting of outside edges
is permitted if the run length is greater than or equal to n m.

The distance between all outside edges of shapes on level P and outside
edges of shapes on level Q. This distance is only checked between
nonintersecting shapes on levels P and Q.

Figure 3-3. Design Rule Syntax Spacing Definitions

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3.1.4.2 Overlap
L overlap of M

The distance from all inside edges of shape L to the inside edges of M when L
intersects M.

J overlap past K

The spacing of all inside edges of shapes on level J to the outside edges of
shapes on level K if the shapes intersect; coinciding of inside and outside edges
is prohibited.

J overlap past K with


coinciding permitted

See J overlap past K above; zero spacing (coinciding of inside and outside
edges) is also permitted (see Figure 3-4).

Figure 3-4. Design Rule Syntax Overlap Definitions

3.1.4.3 Containment
G must be within H

All shapes on level G must be completely covered by shapes on level H. In addition, all outside facing edges of shapes on level G must have a minimum
spacing greater than zero (unless the checked value is zero) to all inside facing
edges of shapes on level H; G straddling H is prohibited.

G within H

Same as G must be within H if G can exist outside of H with straddling


prohibited.

G within H with
coinciding permitted

See G within H above; zero spacing (coinciding of inside and outside edges) is
also permitted.

B must surround A

B does not touch A, but the enclosed area formed by B covers A.

Figure 3-5. Design Rule Syntax Containment Definition

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3.1.4.4 Condition
C must abut D

Shapes on level C must abut shapes on level D. Abutting is defined as


sharing
the same edges without having a common area greater than zero.

M must cover L

All vertices of shape L must be completely contained within the inside


edges of
shape M, and every shape M must contain every shape L.

C must touch D

Shapes on level C must intersect or abut shapes on level D. Shapes on


level D
are not required to touch shapes on level C.

C must not straddle D

Shapes on level C must be either completely inside or outside shapes on


level D. Coincident edges are permitted.

C can only straddle D


at 90

Edges of shapes on level C can only intersect edges of shapes on level D


at a
90 angle.

C prohibited over D

Shapes on level C must not intersect shapes on level D. Abutting is


permitted.

Figure 3-6. Design Rule Syntax Condition Definition

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3.1.5 Design Rule Conditions


3.1.5.1 Logical Function
E union F

The geometrical Boolean-logic OR union of shapes on level E and shapes on


level F (see Figure 3-7).

C over D

The geometrical Boolean-logic AND intersection of shapes on level C and


shapes on level D. Same as intersection (C, D), D under C, or (C and D).

C not D

The geometrical Boolean-logic NOT intersection of shapes on level C with the


complement of shapes on level D. Same as difference (C, D).

Figure 3-7. Design Rule Syntax Logical Function Definitions

3.1.5.2 Sizing Function


C sized by n m

All shapes on level C sized by n m per edge, where n is either positive (expanded) or
negative (shrunk).

Figure 3-8. Design Rule Syntax Sizing Function Definition

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3.1.5.3 Relational Selection Function


C coinciding with D

Shape C having inside or outside edges in common with shape D.

C touching vertex

Points where either two inside or two outside corners touch.

C straddling D
Shape C crossing the border of shape D. For example, C straddling D means that
part of shape C overlaps D and part of shape C extends beyond the edge of D.
C touching D
C not touching D

C incurring D

All shapes on level C that are abutting or intersecting shapes on level D.


All shapes on level C that do not have a common area with any shapes on level D.
Shapes on level C that have common edges with shapes on level D are not
included in the result.
All shapes on level C that do have a common area with any shapes on level D.

Figure 3-9. Design Rule Syntax Relational Selection Definitions

3.1.5.4 Geometrical Selection Function


A with width = n m,
A with width > n m,
A with width > n m
and m m

All shapes on level A that has widths in the valid range.

C vertex

The points at which shape edges on level C form an angle.

C inner vertex

All vertices that have angles greater than 180 when measured from inside the
shape (concave). Same as inner corner.

C outer vertex

All vertices that have angles less than 180 when measured from inside the
shape (convex). Same as outer corner.

C at 45

All shapes on level C that have edges at a 45 angle with respect to the x or y
axis.

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Figure 3-10. Design Rule Syntax Geometrical Selection Function Definitions

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3.2 Design Rule Abbreviations


The abbreviations in Table 3-1 are used to simplify the rule descriptions in the design rule tables that follow. They
also aid in DRC implementation.
Table 3-1. Design Rule Checking Abbreviations
Abbreviation

Definition

CAREC End

Edge of CAREC that is 0.09 um long, see Figure 3-11

CAREC Side

Edge of CAREC that is 0.22 um long, see Figure 3-11

RX butted n-well contact

(RX n-well contact) butting (RX over JZ)

RX butted p-well contact

(RX p-well contact) butting (RX over JX)

DV probe pad

DV over PROBE.

DV wire-bond pad

DV not over PROBE.

Gate

PC over RX.

Gate side

The edge of the gate that is abutting (RX not over PC).

Gate end

The edge of the gate that is abutting (PC not over RX).

Isolated P-Well

(T3 not NW) coinciding with NW enclosed area.

NFET gate

(Gate over JX) not over NW.

PFET gate

(Gate over JZ) over NW.

P-well

(CHIPEDGE/ Bounding box extending to all data) not (NW or BFMOAT or ZVT).

RX butted n-well contact

(RX n-well contact) butting (RX over JX).

RX butted p-well contact

(RX p-well contact) butting (RX not over JX).

RX n+ diffusion

RX n+ junction not over PC.

RX n+ junction

(RX over JX) not over NW.

RX n-well contact

(RX over JX) over NW.

RX p+ diffusion

RX p+ junction not over PC.

RX p+ junction

(RX over JZ) over NW.

RX p-well contact

(RX substrate contact) or (RX triple-well contact).

RX substrate contact

(RX over JZ) not over (NW or Isolated P-Well).

RX triple-well contact

(RX over JZ) over (Isolated P-Well).

VV pad contact

VV over (LB touching DV).

LDMOS NFET channel gate

(NFET gate over 5VHVFET) not NW

LDMOS PFET channel gate

(PFET gate over 5VHVFET) over NW

LDMOS RX n-well drain

((RX n-well contact over (DG or EG)) over 5VHVFET) not PC

LDMOS RX triple-well drain

((RX triple-well contact over (DG or EG)) over 5VHVFET) not PC

LDMOS RX n+ source

((RX n+ junction over (DG or EG)) over 5VHVFET) not PC

LDMOS RX p+ source

((RX p+ junction over (DG or EG)) over 5VHVFET) not PC

LDMOS RX substrate guard ring

RX substrate contact over 5VHVFET

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Abbreviation

Definition

LDMOS RX n-well guard ring

RX n-well contact over 5VHVFET

Figure 3-11. Illustration for CAREC end and CAREC side

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3.4 Geometry Restriction Design Rules


The physical design rules described in Table 3-2 are verified during design rule checking (DRC)
Table 3-2. Geometry Restriction Design Rules
Rule

Notes

S1

The design grid must be an integer multiple of 0.0010 m.

S2

Shapes with acute angles are prohibited. (Except for PROTECT layer)

S3

Shapes that intersect and overlap themselves are prohibited, but shapes that abut themselves
are permitted.

S4

Shapes that cross over themselves (known as bow ties and reentrant shapes) are prohibited.

S5

Shapes with zero area are prohibited.

S6

Only orthogonal shapes or shapes on a 45 angle are permitted, except in alphanumeric


labels.

S7

Shapes formed with two nonintersecting lines (known as inside-outside shapes) are prohibited.

S8

1,2

Shapes formed with line or path operation codes must not have 45 bends.

S9

Line end segments formed with line or path operation codes must have a length-to-width ratio
greater than 0.5000

S10

Text (alpha opcode) data is prohibited on any mask build level. Use polygon letters instead.

1.
2.

Description

These shapes do not occur during GDS conversions.


This rule is not checkable in all DRC code systems.

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3.5 Polysilicon and Isolation Design Rules


Table 3-5. RX Design Rules
Rule

Notes

Description

Design

NFET gate minimum gate length.

0.04

PFET gate minimum gate length.

0.04

10

NFET gate minimum gate width.

0.115

10R

NFET gate minimum gate width.

0.15

11

PFET gate minimum gate width.

0.12

11R

PFET gate minimum gate width.

0.15

40

(RX OR RXFILL) minimum density (%) with 150.000 m tiling within RXEXCLUD.

20

40a

(RX OR RXFILL) maximum density (%) with 150.000 m tiling within RXEXCLUD.

90

40b

(RX OR RXFILL) minimum density (%) with 150.000 m tiling within CHIPEDGE.

25

41

(RX OR RXFILL) maximum density (%) with 150.000 m tiling within CHIPEDGE.

75

41a

[(RX OR RXFILL) not over DG] maximum density (%) with 150.000 um tiling within
RXEXCLUD.

80

41R

(RX OR RXFILL) maximum local density (%) with 300.000 m tiling within CHIPEDGE.

65

42

(PC OR PCFILL) minimum density (%) with 25.000 m tiling within PCEXCLUD.

14

50

RX minimum width.

0.06

50R

RX minimum width.

0.08

50b

RX maximum width.

72

50t

(RX at 45) minimum space to RX (run length > 0 m)

0.17

50w

(RX at 45) minimum width (run length > 0 m)

0.17

50l

(RX at 45) minimum length (run length > 0 0 m)

0.50

51

RX minimum area (m2).

0.031

51R

RX minimum area (m2).

0.050

51a

RX minimum area (with all the inner RX edge length <0.21 m) (m2).

0.055

51b

RX minimum enclosed area (m2).

0.04

51c

RX minimum enclosed area (with all the inner RX edge length < 0.21 m) (m2).

0.077

52

RX minimum space and notch.

0.08

52R

RX minimum space and notch.

0.100

52a

RX minimum space to (RX with area > 4000000 m2)

0.350

52b

(RX with width>0.12 m) minimum space with run length 0.14 m

0.10

52u

RX minimum notch.

0.115

55

(RX edge not over GUARDRING) must be orthogonal.

1.

This rule does not apply to dummy RX.

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Table 3-6. PC Design Rules


Rule

Notes

100

PC minimum width.

0.04

100R

(PC not over RX) minimum width (see footnotes and illustration in DM).

0.07

101a

PC minimum area (m2). (this check does not include PC of rectangular area with any
side with length 0.3 m)

0.022

101ab

PC minimum area (with all edge length <0.21 m) (m2).

0.055

101b

PC minimum enclosed area (m2).

0.04

101c

PC minimum enclosed area (with all edge length <0.21 m) (m2).

0.077

102

PC minimum space and notch.

0.10

102R

PC minimum space and notch.

0.12

102d

(PC with width > 0.120 m) minimum space to PC (run length > 0.14 m).

0.160

102e

[(PC at 45) not over RX] minimum width.

0.17

102f

[(PC at 45) not over RX] minimum space to PC (run length > 0 m)

0.17

102g

[(PC at 45) not over RX] minimum length.

0.26

For (PC_end with length < 0.07 m), the PC_end must meet rule 102ha or 102hb

102h_or

2,3

Description

Design

102ha

PC_LE minimum space to PC for run length > 0 m

0.110

102hb

PC_LS minimum space to PC for run length > 0 m.

0.110

102i

[PC with area > 630 m touching (PC density > 70% with 30 m tiling)] minimum space to
(gate with length 0.08 m)

1.000

103

(PC over RX) must be orthogonal.

104a

NFET gate minimum space (run length > 0.000 m) over RX.

0.14

104b

PFET gate minimum space (run length > 0.000 m) over RX.

0.13

104c

[(Gate not covered by EG or DG or ESD_HBM or ESD_CDM) with gate length >0.08 m]


maximum space (run length > 0.000 m) over RX.

0.32

104d

(Gate with gate length >0.06 m) minimum space (run length > 0.000 m) over RX

0.14

104e

(Gate_side for gates with channel length < 0.08 m) minimum space to PC (run length >
0.000 m.

0.12

110

RX minimum overlap past PC.

0.06

110R

RX minimum overlap past PC.

0.13

110a

RX maximum overlap past [Gate_side for (Gate not covered by EG or DG or ESD_HBM or


ESDF_CDM) with channel length 0.08 m]

0.32

111

PC minimum overlap past RX.

0.07

111R

PC minimum overlap past RX.

0.11

111a

PC minimum overlap past RX when PC to RX inner vertex distance 0.100 m. (PC and
RX in the same MOS).

0.09

113

PC minimum space to RX.

0.030

114R

Gate minimum space to RX inner vertex.

0.100

115a

Gate minimum space to PC inner vertex when E1 is less than or equal to 0.06um

0.040

115b

Gate minimum space to PC inner vertex when E1 is greater than 0.06um but less than or
equal to 0.1um

0.050

115R

Gate minimum space to PC inner vertex.

0.070

119a

PC over RX vertex is prohibited.

120

PC vertices over RX are prohibited.

121

PC can straddle RX only at 90.000-deg.

125

PC over RX must divide RX into two or more diffusion regions.

199

PC line-end must be rectangle.

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Notes

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Description

Design

PDPCa

[Summed (PC OR PCFILL) area across full chip] / (CHIPEDGE area) maximum density.

0.40

PDPCb

[Summed (PC OR PCFILL)area across full chip] / (CHIPEDGE area) minimum density.

0.14

PDRXa

[Summed (RX OR RXFILL)area across full chip]/ (CHIPEDGE area) maximum density.

0.75

PDRXb

[Summed (RX OR RXFILL)area across full chip]/ (CHIPEDGE area) minimum density.

0.25

1.

2.
3.
4.
5.
6.
7.
8.
9.

The following regions are excluded from this check:


(1) Gate end extensions up to 0.14 m beyond the RX edge (see Figure 3-13)
(2) (PC not over RX) regions with an area 0.0056 m2
(3) EFUSE
In situations where the PC_end is not connected to two (outer vertices connected to edges of lengths > 0.070m), 102h_or is not
checked for that line end. (see figure titled Design Rule 102h)
PC_end = (PC edge with length 0.070 m) between two (outer vertices connected to edges of length > 0.015m). Any other PC is
defined as a PC side.
PC_LE corresponds to PC_end extended out by 0.035m off each end. (see figure titled Design Rule 102h)
PC_LS corresponds to the 0.070m PC side extended out beyond the PC_end by 0.035m. (see figure titled Design Rule
102h)
This rule is not DRC checked.
This rule does not apply to PC fuse element.
This rule does not cover 5VHVFET
LDMOS is excluded from checking

Figure 3-12. Gate Extension Area to Exclude from Rule 100R

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RX
52a

Area > 4000000 m2

Gate Length > 0.06 m

Figure 3-13. Polysilicon and Isolation Design Rules

111R
104aR
104bR

104m

PC

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E1
PC

PC

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Figure 3-14. Design Rule 102h

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3.6 Short Edge Design Rules


Table 3-7. Short Edge Design Rules
Rule

Description

Design

SE1R

RX vertex must not be connected to two short edges with length < 0.070 um.

SE2

PC vertex must not be connected to two short edges with length < 0.040 m.

SE2R

PC vertex must not be connected to 2 short edges with length < 0.07 m.

0.070

SE2aR

PC edge with length < 0.070 m must have at least one neighboring edge with length 0.070 m.

SE3

JX vertex must not be connected to two short edges with length < 0.140 m.

SE4

M1 vertex must not be connected to two short edges with lengths < 0.070 m.

SE4R

Any M1 vertex touching an M1 edge 0.070 m must connect to an M1 edge.

0.135

SE5

Mx vertex must not be connected to two short edges with lengths < 0.070 m, where x = 1-8.

SE5R

Any Mx vertex touching an Mx edge 0.070 m must connect to an Mx edge, where x=1-8.

0.135

SE6

Bx vertex must not be connected to two short edges with length < 0.140 m, where Bx = B1-B5, L1-L4,
BA, BB, BD, BE, or BG.

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3.7 Antenna Design Rules


Charging is a process caused by reactive ion etching and other plasma-assisted manufacturing steps. While inside
the plasma chamber, the wafer is exposed to electron and ion currents from the plasma to the surface. In a
well-behaved uniform plasma, the electron and ion currents are balanced through the radio-frequency cycle and no
net charge buildup takes place. When irregularities such as surface topography, sporadic plasma collapse, or
lateral plasma non-uniformity are introduced, the electron and ion currents are no longer balanced and currents
can flow from the wafer surface to the bulk silicon and then back to the plasma. The direction of current flow and the
amount of charge depends on the plasma composition and temperature and potential distributions. The direction of
current might be different depending on the position on the wafer.
When the current flows through the gate oxide, it causes irreversible damage and, thus, early reliability failures, Vt
shifts, and gamma/sub-Vt swing degradation as well as increased distributions.Vt mismatches in differential pairs
and other circuits in excess of 15 mV have been observed when antenna ratios are unbalanced. It has also been
observed that nested features experience more charging than isolated features.
In Figure 3-15, the gate is exposed to any charging induced by the right CA, the right M1, the right two V1s, and M2.
For every metal and via above M2, this gate is tied to the substrate through the left CA/M1/V1/M2, and charging
restrictions do not apply. The diode carries the current that would otherwise pass through the gate and must be
large enough to adequately conduct the current.
Figure 3-15. Charging Mechanism

The diode is often reverse-biased. High temperatures during the plasma-assisted manufacturing steps change the
electrical behavior of the diode to that of a resistor. When the diode area is larger, the resistance is smaller and
more current can be carried. In normal circuit operation, the diode is reverse-biased and, therefore, does not short.
x

The antenna for a given gate is the sum of the areas, A , of all shapes on a specific level, x, that are electrically
connected to the gate. For example, an M2 antenna for a gate is defined as all shapes connected to that gate
through the PC/CA/M1/V1 network.

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3.7.1 Definitions
Floating-gate device

Gate oxide area


Metal antenna ratio

Any device where PC (polysilicon) touches RX (diffusion) but is not electrically


connected to RX.
(PC over RX) area.
Defined at each metal level as the ratio of the metal area to the connected
gate-oxide area at which the gate has not yet been electrically connected to RX. For
example, the ratio for an M1 region would be the M1 area divided by the gate oxide
area of the gate to which M1 is connected.

Polysilicon antenna ratio The ratio of the total PC area to the gate oxide area in each PC that intersects RX.

3.7.2 Design Rule Assumptions


TBD

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3.7.3 Design Rules


Table 3-8. Antenna Design Rules
Rule

Notes

Description

Design

130a

PC - gate antenna: Maximum ratio of (PC area) / (gate area).

<

250

130b

PC - thick gate antenna: For gate touching EG or DG, the maximum ratio of (PC area) / (gate
area).

10

131

1,2

1000

131a

1,2

131b

1,2

20

131c

131eR

150

131f

300

131h

150

131i

<

131j

<

131k

<

131x

150

131xa_or

[(NFET gate over NCAP) touching (DG, EG)] must meet rule 131xb, 131xc, or 131xd.

131xb

[(NFET gate over NCAP) touching (DG, EG)] must be electrically connected to [RX over (any
NW that is electrically connected to the NW touching the NFET gate)] with a ratio of [VV area
/ (2 RX area)].

150

131xc

[(NFET gate over NCAP) touching (DG, EG)] must be electrically connected to RX with a ratio
of [VV area / (2 x RX area)].

0.100

131xd

150

131y

150

131z

{[NFET gate not over (NCAP, isolated p-well)] touching (DG, EG)} must be electrically
connected to [RX not over (NW, T3)] with a ratio of [VV area / (2 x RX area)].

150

134a

(Mx area electrically connected to NW touching {gate elec trically connected by Mx to [RX not
over (NW or T3)]} or {T3 touching gate}) / ({NW + [T3 not NW] area} + {700 x RX area that is
electrically connected to [RX not over (NW or T3)] byMx}) is < 0.4.

135a

Triple well tie-down rule: (isolated p-well touching gate) must touch RX, which is electrically
connected to [RX over NW] through M1.

Metal - gate antenna (general rule): For nets connected to gate, the ratio of [metal area] /
[(gate area) + (2 x RX area)], where the metal area is the noncumulative level-specific metal
area electrically connected to any gate and, optionally, to the RX area.
Via - medium/thick gate antenna: For nets connected to (gate over EG or DG), the ratio of [via
area] / [(gate area) + (5 x RX area)], where the via area is the noncumulative level-specific via
area electrically connected to any gate and, optionally, to the RX area.
Via - gate antenna (general rule): For nets connected to (gate with a gate area > 0 m2), the
ratio of [via area] / [(gate area) + (5 x RX area)], where the via area is the noncumulative
level-specific via area electrically connected to any gate and, optionally, to the RX area.
CA - gate antenna: Ratio of (CA area) / (gate area).
Metal thick gate antenna: For nets connected to (gate over DG), the ratio of (metal area) / (2 x
RX area), where the metal area is the noncumulative level-specific metal area electrically
connected to any gate and the RX area. Floating (gate over DG) is prohibited.
Metal - medium gate antenna: For nets connected to (gate over EG or DG), the ratio of [metal
area] / [(gate area) + (2 x RX area)], where the metal area is the noncumulative level-specific
metal area electrically connected to any gate and, optionally, to the RX area.
VV - gate antenna (general rule): For nets electrically connected to (gate and VV), the ratio of
(VV area) / (2 x RX area).
PFET gate connected to [LB touching (DV or LV) labeled with ("TEST_PAD_NOESD" on
LBESD)] must be connected to (RX in the same electrical n-well as the gate) with a ratio of
(DV or LV area) / (20 x RX area).
{NFET gate over (T3 not over NW)} connected to [LB touching (DV or LV) labeled with
("TEST_PAD_NOSED" on LBESD)] must be connected to (RX in the same electrical triple
well as the gate) with a ratio of (DV or LV area) / (20 x RX area).
{NFET gate not over [(T3 not over NW) or NW]} connected to [LB touching (DV or LV) labeled
with ("TEST_PAD_NOSED" on LBESD)] must be connected to {RX not over [(T3 not over
NW) or NW]} with ratio of (DV or LV area) / (20 x RX area).
[PFET gate touching (DG, EG)] must be electrically connected to [RX over (any NW that is
electrically connected to the NW touching the PFET gate)] with a ratio of [VV area / (2 x RX
area)]

[(NFET gate over NCAP) touching (DG, EG)] must be electrically connected to {(RX not over
NW) or [RX over (isolated p-well that is connected to substrate)]} with a ratio of [VV area / (2 x
RX area)].
{[(NFET gate not over NCAP) over isolated p-well] touching (DG, EG)} must be electrically
connected to [RX over (any isolated p-well that is electrically connected to the isolated p-well
touching the NFET gate)] with a ratio of [VV area / (2 x RX area)].

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Notes

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Design

1. The gate area is the sum of all connected gate types.


2. Nets tied to an RX substrate, n-well, or triple-well contact satisfies this rule.
3. This rule does not cover 5VHVFET

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3.8 1.8 V, 2.5 V, or 3.3 V I/O Device Design Rules


Table 3-9. 1.8 V, 2.5 V, or 3.3 V I/O Device Design Rules
Rule

Notes

DG1

[(NFET gate over DG) not over DGV] minimum gate length for 2.5V nominal supply voltage operation.

0.27

DG1a

[(NFET gate over DG) over DGV] minimum gate length for 1.8 V nominal supply voltage operations.

0.25

DG1b

[(NFET gate over DG) over OVERDRIVE] minimum gate length for 3.3V nominal supply voltage

0.55

DG2

[(PFET gate over DG) not over DGV] minimum gate length for 2.5V nominal supply voltage operations

0.27

DG2a

[(PFET gate over DG) over DGV] minimum gate length for 1.8 V normal supply voltage operations.

0.25

DG2b

[(PFET gate over DG) over OVERDRIVE] minimum gate length for 3.3V nominal supply voltage

0.44

DG10

(Gate over DG) minimum gate width.

0.320

DG15

Gate minimum within DGV.

0.000

DG17

DGV must be within DG.

DG20

DG shapes must be orthogonal.

DG21

DG minimum width.

0.34

DG22

DG minimum space and notch.

0.34

DG24

Gate minimum within DG.

0.20

DG24a

Gate side minimum within DG (run length > 0.000 m).

0.25

DG25

Gate minimum space to DG.

0.20

DG25b

Gate_side for (Gate not covered by EG or DG) minimum space to DG ((run length > 0.000 m).

0.25

DG30

DG minimum overlap past NW with abutting permitted. (Overlap= 0 is allowed)

0.34

DG34

DG minimum overlap of NW with abutting permitted. (Overlap=0 is allowed)

0.34

DG36

NW minimum overlap past DG with abutting permitted. (Overlap=0 is allowed)

0.34

DG37

NW minimum space to DG with abutting permitted. (Space = 0 is allowed)

0.34

DG52a

RX minimum space within DG

0.15

DG52b

DG overlap past RX

0.20

DG52cR

RX minimum space to DG.

0.20

DG102

PC minimum space to (PC over DG).

0.16

DG104

(Gate over DG) minimum space (run length > 0 m) in the same RX.

0.22

DG110

(RX over DG) overlap past PC.

0.15

DG207

(CA over RX) minimum space to (gate over DG).

0.080

DG252

(NW touching DG) minimum space to NW on different potential.

1.000

DG252a

(NW touching DG) minimum space to (NW touching DG) on different potential.

1.000

DG260

[(RX p+ junction) touching DG] minimum within NW.

0.220

DG265a

[(RX n+ junction) touching DG] minimum space to NW.

0.220

DG265b

RX n+ junction minimum space to (NW touching DG).

0.20

DG268a

{[(RX p+ junction not covered by ESD_HBM or ESD_CDM) touching DG] maximum distance to a RX
n-well contact} over NW for preventing latchup.

30

Design

30

[((RX n+ junction not over isolated p-well) not covered by ESD_HBM or ESD_CDM) touching DG]
maximum distance to RX substrate contact for preventing latchup.
This rule does not apply to (RX n-well contact) and (RX p-well contact). The RX not touching GUARDRNG
This rule does not cover 5VHVFET

DG268b
1.
2.

Description

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3.9 High-Speed I/O Device Design Rules


Table 3-10. High-Speed I/O Device Design Rules
Rule

Notes

Description

Design

EG1

[(NFET gate over EG) not over EGV] minimum gate length for 1.8 V device channel length.

0.150

EG1a

[(NFET gate over EG) over EGV] minimum gate length for 1.5 V nominal supply voltage operations.

0.100

EG2

[(PFET gate over EG) not over EGV] minimum gate length for 1.8 V device channel length.

0.150

EG2a

[(PFET gate over EG) over EGV] minimum gate length for 1.5 V nominal supply voltage operations.

0.100

EG10

(Gate over EG) minimum gate width..

0.320

EG15

Gate minimum within EGV.

0.000

EG17

EGV must be within EG.

0.000

EG20

EG shapes must be orthogonal.

EG21

EG minimum width.

0.340

EG22

EG minimum space and notch.

0.340

EG24

Gate minimum within EG.

0.200

EG24a

Gate side minimum within EG

0.250

EG25

Gate minimum space to EG.

0.200

EG25b

Gate side (not over DG,EG) minimum space to EG

0.25

EG30

EG overlap past (NW not over T3). (Overlap=0 is allowed)

0.340

EG32

EG over (DG, OP, SLVT, LVT, RVT, or HVT) is prohibited.

EG34

EG overlap of NW. (Overlap=0 is allowed)

0.340

NW minimum overlap past EG.


(Overlap=0 is allowed)
NW minimum space to EG with abutting permitted.
(Space=0 is allowed)

0.340

0.340

EG36

EG37

EG52a

RX minimum space within EG.

0.150

EG52b

RX minimum within EG.

0.200

EG52cR

RX minimum space to EG.

0.20

EG102

PC minimum space to [PC over (EG not over EGV)].

0.160

EG104

(Gate over EG) minimum space (run length > 0 m) in the same RX.

0.220

EG110

(RX over EG) overlap past PC

0.150

EG207

(CA over RX) minimum space to (gate over EG).

0.080

EG252

(NW touching EG) minimum space to NW.

1.000

EG252a

(NW touching EG) minimum space to (NW touching EG)

1.000

EG260

[(RX p+ junction) touching EG] minimum within NW.

0.220

EG265a

[(RX n+ junction) touching EG] minimum space to NW.

0.220

EG265b

RX n+ junction minimum space to (NW touching EG).

0.200

EG268a

{[(RX p+ junction not covered by ESD_HBM or ESD_CDM) touching EG] maximum distance to RX
N-well Contact} over NW for preventing latchup.

30

EG268b

[((RX n+ junction not over isolated p-well) not covered by ESD_HBM or ESD_CDM) touching EG]
maximum distance to RX substrate contact for preventing latchup.

30

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3.10 N-Well and Latchup Design Rules


Table 3-11. N-Well and Latchup Design Rules
Rule

Notes

250

NW minimum width.

250a

NW shapes must be orthogonal.

252a

NW minimum space and notch.

0.34

252b

NW minimum space to NW for different nets.

0.800

253a

NW minimum area (m2).

0.640

253b

NW minimum enclosed area (m2).

0.640

260

RX p+ junction minimum within NW.

0.08

261a

(RX not touching (NWRES or BPNWR)) n-well contact within NW.

0.080

265

(RX not touching (NWRES or BPNWR)) n+ junction minimum space to NW.

0.08

265a

(RX not touching NWRES) n+ junction minimum space to NW with at least one edge at each
NW inner vertex.

0.160

266

RX substrate contact minimum space to NW.

0.080

268a

[((RX not touching DRES) p+ junction not covered by ESD_HBM or ESD_CMD) maximum
distance to the RX n-well contact] over NW for preventing latchup.

30

268b

[(((RX not touching (DRES or BPNWR)) n+ junction not over isolated p-well) not covered by
ESD_HBM or ESD_CDM) maximum distance to a RX substrate contact] not over NW for
preventing latchup.

30

1.
2.

Description

Design

At least one edge is checked using keep out regions of 0.16m x 0.16m for corners and 0.16m x jog height for jogs.
This rule does not cover 5VHVFET

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3.11 Triple-Well and Latchup Design Rules


The triple-well option offers a separate p-well (marked by level T3) isolated from the substrate by a buried n-band
implant. The p-well is embedded in the n-well to isolate it laterally from the substrate.

3.11.1 T3 Design Approach


All n-wells within an NW ring or T3 triple wells are shorted by the buried n-band implant and are all at the same
potential.
Table 3-12. Alternative Triple-Well and Latchup Design Rules
Rule

Notes

3T00

N3 is prohibited

3T01

T3 shapes must be orthogonal.

3T02

T3 minimum width.

3.000

3T03

T3 minimum space and notch.

3.500

3T05

(T3 edges) must be within NW.

3T05b

T3 overlap of NW.

0.400

3T06a

T3 minimum space to (NW at different net using (NW, T3)).

2.500

3T07

(RX n+ junction over T3) minimum space to NW.

0.080

3T08

(RX triple-well contact over T3) minimum space to NW.

0.080

3T09

(RX p+ junction over T3) minimum within NW.

0.080

3T10

(RX n-well contact over T3) minimum within NW.

0.080

3T13

BFMOAT over T3 is prohibited.

3T17

T3 minimum space to RX n+ junction

1.650

3T18

Isolated p-well minimum space to p-well (isolated or substrate) for different nets.

0.800

3T18b

[Isolated p-well touching (EG or DG)] minimum space to p-well (isolated or substrate) for
different nets.

1.000

3T21

RX n+ junction minimum within T3

0.480

3T22

T3 minimum space to (Gate_side over NW)

1.000

3T23

Gate_side minimum within T3

0.400

3T24

NW overlap past T3.

0.410

3T68b

((RX n+ junction over isolated p-well) not covered by ESD_HBM or ESD_CDM) maximum
distance to the RX triple-well contact for preventing latchup.

30

3T68c

[((RX n+ junction over isolated p-well) not covered by ESD_HBM or ESD_CDM) touching DG]
maximum distance to the RX triple-well contact for preventing latchup.

30

3T68d

{[((RX n+ junction over isolated p-well) not covered by ESD_HBM or ESD_CDM)] touching EG}
maximum distance to the RX triple-well contact for preventing latchup.

30

1.

Description

Design

This rule does not cover 5VHVFET

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Figure 3-16. Design Rule 3T02

3.12 Moat Design Rules


The BFMOAT level can be used to design a resistive substrate ring to reducing substrate noise coupling between
regions on the same chip.
Table 3-13. BFMOAT Design Rules
Rule

Notes

Description

Design

790

BFMOAT minimum width.

5.000

791

BFMOAT must be orthogonal.

792

BFMOAT minimum space and notch.

5.000

793

BFMOAT minimum space to NW.

1.000

795

BFMOAT minimum space to RX.

0.500

796

BFMOAT minimum space to ZVT.

1.000

799a

(RX, NW, JZ, PC, BIPOLAR, SLVT, GY, IY, LVT, XW, LW, HVT, NR, PR, RVT, NCAP, T3,
ZVT) over BFMOAT is prohib-ited. [(RX, PC) over IND] shapes are exempt from this rule.

1. This rule is for BF derivation.

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3.13 Zero-Vt NFET Design Rules


40nm-LP offers two different zero-Vt devices: thin and thick (DG) gate oxide. Zero-Vt devices receive a double
asymmetric implant with a halo to be blocked on both sides of the gate. The ZVT drawing layer is used to mark
zero-Vt FET devices.
Table 3-14. Zero-Vt NFET Design Rules
Rule

Notes

Description

Design

ZVT1

ZVT minimum width.

0.340

ZVT2

ZVT minimum space and notch.

0.340

ZVT3

ZVT shapes must be orthogonal.

ZVT4

(ZVT over RX) over NW, JZ, SLVT, GY, IY, LVT, XW, LW, HVT, NR, PR or RVT is prohibited.

ZVT5a

ZVT minimum space to NW with touching prohibited.

1.000

ZVT8

(RX touching PC) minimum space to ZVT.

0.380

ZVT9

(RX touching JX) minimum within ZVT.

0.260

ZVT10

(Gate over ZVT) minimum gate width.

0.500

ZVT12

Gate touching ZVT minimum gate length.

0.300

ZVT13

(Gate over DG) touching ZVT minimum gate length.

1.200

ZVT13a

(Gate over EG) touching ZVT minimum gate length.

0.800

[(Gate over DG) over OVERDRIVE] touching ZVT minimum gate length for 3.3V nominal
supply voltage.
[(Gate over DG) over DGV] touching ZVT minimum gate length for 1.8V nominal supply
voltage.

1.200

1.200

ZVT14a

ZVT14b

ZVT15

PC minimum overlap past (RX over ZVT)

0.350

ZVT16

ZVT minimum area.

0.640

ZVT17

ZVT minimum enclosed area.

0.640

ZVT18

ZVT over T3 is prohibited.

ZVT19

Only one RX is permitted over ZVT.

1. RX on the same net is exempt from this rule.

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Figure 3-17. Zero-Vt Device Design Rules

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3.14 Low-Vt / Superlow-Vt Device Design Rules


This device is a standard FET device with a different well implant and, hence, a lower threshold voltage. This
device receives the standard source/drain implant and FET extension implants. The LVT & SLVT drawing layer is
used to mark low-Vt FET & Superlow-Vt devices.
Table 3-15a. Low-Vt Device Design Rules
Rule

Description

Design

LW01

(LVT, LW) minimum width with run length > 0 m and with touching vertex permitted.

0.180

LW02

(LVT, LW) minimum space and notch with run length > 0 m and touching vertices are permitted.

0.180

LW03

(LVT, LW) shapes must be orthogonal.

LW04

LW is prohibited over EG, DG, RX n+junction, SLVT,GY, IY, HVT, NR, PR, ZVT, NCAP, PCAP and
VAR.

LW08R

Gate minimum space to (LVT, LW).

0.100

LW08a

Gate side minimum space to (LVT, LW) for run length > 0 m.

0.140

LW08b

Gate minimum space to (LVT, LW) (PC endcap direction).

0.080

LW09R

Gate minimum within (LVT, LW).

0.100

LW09a

Gate side minimum within (LVT, LW) for run length > 0 m.

0.140

LW09b

Gate minimum within (LVT, LW) (PC endcap direction).

0.080

LW10

(LVT, LW) minimum area (m2)

0.190

LW11

(LVT, LW) minimum enclosed area (m2)

0.190

LW12

(LVT, LW) minimum space to [(RX or PC) over OP]

0.180

LW13

(LVT, LW) minimum space to [(RX or PC) over SBLK]

0.180

XW01

(LVT, XW) minimum width with run length > 0 m and with touching vertex permitted.

0.180

XW02

(LVT, XW) minimum space and notch with run length > 0 m and touching vertices are permitted.

0.180

XW03

(LVT, XW) shapes must be orthogonal.

XW04a

LVT is prohibited over EG, DG, SLVT,GY, IY, HVT, NR, PR, ZVT, NCAP, PCAP, XW and LW

XW04b

XW is prohibited over EG, DG, RX p+junction, SLVT, GY, IY, HVT, NR, PR, ZVT, NCAP, PCAP and
VAR.

XW08R

Gate minimum space to (LVT, XW)

0.100

XW08a

Gate side minimum space to (LVT, XW) for run length > 0 m.

0.140

XW08b

Gate minimum space to (LVT, XW) (PC endcap direction).

0.080

XW09R

Gate minimum within (LVT, XW)

0.100

XW09a

Gate side minimum within (LVT, XW) for run length > 0 m.

0.140

XW09b

Gate minimum within (LVT, XW) (PC endcap direction).

0.080

XW10

(LVT, XW) Minimum area (m2)

0.190

XW11

(LVT, XW) Minimum enclosed area (m2)

0.190

XW12

(LVT, XW) minimum space to [(RX or PC) over OP]

0.180

XW13

(LVT, XW) minimum space to [(RX or PC) over SBLK]

0.180

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Table 3-15b. Superlow-Vt Device Design Rules


Rule

Description

Design

IY01

(SLVT, IY) minimum width with run length > 0 m and with touching vertex permitted.

0.180

IY02

(SLVT, IY) minimum space and notch with run length > 0 m and touching vertices are permitted.

0.180

IY03

(SLVT, IY) shapes must be orthogonal.

IY04

IY is prohibited over EG, DG, RX n+junction, GY, LVT, XW, LW, HVT, NR, PR, ZVT, NCAP, PCAP and
VAR.

IY08R

Gate minimum space to (SLVT, IY).

0.100

IY08a

Gate side minimum space to (SLVT, IY) for run length > 0 m.

0.140

IY08b

Gate minimum space to (SLVT, IY) (PC endcap direction).

0.080

IY09R

Gate minimum within (SLVT, IY).

0.100

IY09a

Gate side minimum within (SLVT, IY) for run length > 0 m.

0.140

IY09b

Gate minimum within (SLVT, IY) (PC endcap direction).

0.080

IY10

(SLVT, IY) minimum area (m2)

0.190

IY11

(SLVT, IY) minimum enclosed area (m2)

0.190

IY12

(SLVT, IY) minimum space to [(RX or PC) over OP]

0.180

IY13

(SLVT, IY) minimum space to [(RX or PC) over SBLK]

0.180

GY01

(SLVT, GY) minimum width with run length > 0 m and with touching vertex permitted.

0.180

GY02

(SLVT, GY) minimum space and notch with run length > 0 m and touching vertices are permitted.

0.180

GY03

(SLVT, GY) shapes must be orthogonal.

GY04a

SLVT is prohibited over EG, DG, LVT, XW, LW , HVT, NR, PR, ZVT, NCAP, PCAP, IY, GY

GY04b

GY is prohibited over EG, DG, RX p+junction, IY, LVT, XW, LW, HVT, NR, PR, ZVT, NCAP, PCAP and
VAR.

GY08R

Gate minimum space to (SLVT, GY)

0.100

GY08a

Gate side minimum space to (SLVT, GY) for run length > 0 m.

0.140

GY08b

Gate minimum space to (SLVT, GY) (PC endcap direction).

0.080

GY09R

Gate minimum within (SLVT, GY)

0.100

GY09a

Gate side minimum within (SLVT, GY) for run length > 0 m.

0.140

GY09b

Gate minimum within (SLVT, GY) (PC endcap direction).

0.080

GY10

(SLVT, GY) Minimum area (m2)

0.190

GY11

(SLVT, GY) Minimum enclosed area (m2)

0.190

GY12

(SLVT, GY) minimum space to [(RX or PC) over OP]

0.180

GY13

(SLVT, GY) minimum space to [(RX or PC) over SBLK]

0.180

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3.15 High-Vt Device Design Rules


This device is a standard FET device with a different well implant and, hence, a higher threshold voltage. This
device receives the standard source/drain implant and FET extension implants. The HVT drawing layer is used to
mark high-Vt FET devices.
Table 3-16. High-Vt Device Design Rules
Rule

Description

Design

NR01

(HVT, NR) minimum width with run length > 0 m and with touching vertex permitted.

0.180

NR02

(HVT, NR) minimum space and notch with run length > 0 m and with touching vertices permitted.

0.180

NR03

(HVT, NR) shapes must be orthogonal.

NR04a

HVT is prohibited over EG, DG, SLVT,GY, IY, LVT, XW, LW, ZVT, NCAP, PCAP, VAR, NR and PR.

NR04b

NR is prohibited over EG, DG, RX p+junction, SLVT, GY, IY, LVT, XW, LW, ZVT, PCAP, NCAP and
VAR.

NR08a

Gate side minimum space to(HVT, NR) for run length > 0 m.

0.140

NR08b

Gate minimum space to (HVT, NR). (PC endcap direction).

0.080

NR09a

Gate side minimum within (HVT, NR) for run length > 0 m.

0.140

NR09b

Gate minimum within (HVT, NR). (PC endcap direction).

0.080

NR10

(HVT, NR) minimum area (m2)

0.190

NR11

(HVT, NR) minimum enclosed area (m2)

0.190

NR12

(HVT, NR) minimum space to [(RX or PC) over OP]

0.180

NR13

(HVT, NR) minimum space to [(RX or PC) over SBLK]

0.180

PR01

(HVT, PR) minimum width with run length > 0 m and with touching vertex permitted.

0.180

PR02

(HVT, PR) minimum space and notch with run length > 0 m and with touching vertices permitted.

0.180

PR03

(HVT, PR) shapes must be orthogonal.

PR04

PR is prohibited over EG, DG, RX n+junction, SLVT, ,GY, IY, LVT, XW, LW, ZVT, PCAP, NCAP and
VAR.

PR08a

Gate side minimum space to (HVT, PR) for run length > 0 m.

0.140

PR08b

Gate minimum space to (HVT, PR). (PC endcap direction).

0.080

PR09a

Gate side minimum within (HVT, PR) for run length > 0 m.

0.140

PR09b

Gate minimum within (HVT, PR). (PC endcap direction).

0.080

PR10

(HVT, PR) minimum area (m2)

0.190

PR11

(HVT, PR) minimum enclosed area (m2)

0.190

PR12

(HVT, PR) minimum space to [(RX or PC) over OP]

0.180

PR13

(HVT, PR) minimum space to [(RX or PC) over SBLK]

0.180

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Figure 3-18. Low- and High-Vt Device Design Rules

3.16 JX Design Rules


Table 3-17. JX Design Rules
Rule

Notes

JX00

JX minimum width.

0.180

JX01

JX minimum area (m2).

0.110

JX01b

JX minimum enclosed area (m2).

0.110

JX02

JX minimum space and notch.

0.180

JX03

1,2

(RX n+ junction not touching BPNWR) minimum within JX.

0.070

JX03a

(RX touching JX) minimum overlap of JX.

0.100

JX04

1,2

(RX n-well contact not touching BPNWR) minimum within JX.

0.020

JX05

RX p+ junction minimum space to JX

0.070

JX06

RX p-well contact minimum space to JX

0.020

JX351c

JX (not butting PROTECT) must be orthogonal.

JX369a

(Gate over NW) is prohibited over [JX not over (NCAP or VAR)].

JX369b

(Gate not over NW) must touch (JX or PCAP or VAR).

JX370

(Gate not over JX) minimum space to JX.

0.080

JX371

Gate minimum within JX.

0.080

JX371aR

JX minimum overlap past PC.(except dummy PC)

0.110

1.
2.
3.
4.

Description

Design

If RX straddles a butted JX/JZ edge, the butted diffusion rules apply.


Rules JX03 and JX04 is not applicable is for N-Well Resistor (NW within RX).
This rule is not applicable for dummy PC.
This rule does not cover 5VHVFET

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3.17 JZ Design Rules


Table 3-18. JZ Design Rules
Rule

Notes

JZ00

JZ minimum width.

0.180

JZ01

JZ minimum area (m2).

0.110

JZ01b

JZ minimum enclosed area (m2).

0.110

JZ02

JZ minimum space and notch.

0.180

JZ03

RX p+ junction minimum within JZ.

0.070

JZ03a

(RX touching JZ) minimum overlap of JZ.

0.100

JZ04

RX p-well contact minimum within JZ.

0.020

JZ05

RX n+ junction minimum space to JZ.

0.070

JZ06

RX n-well contact minimum space to JZ.

0.020

JZ351c

(JZ not touch GUARDRNG) must be orthogonal.

JZ369a

(Gate not over NW) is prohibited over [JZ not over (PCAP or VAR)].

JZ369b

(Gate over NW) must touch (JZ or NCAP or VAR).

JZ370

(Gate not over JZ) minimum space to JZ.

0.080

JZ371

Gate minimum within JZ.

0.080

JZ371aR

JZ minimum overlap past PC.(except dummy PC)

0.110

JZ380

(RX not over NWRES or BPNWR) must be within (JX or JZ).

JZ381

JX is prohibited over JZ.

Design

[((PC over (SBLK or OP)) not over (EFUSE or LOGOBND)] must be covered by (JX union JZ).
(except PCFILL)
If RX straddles a butted JX/JZ edge, the butted diffusion rules apply.
This rule is not applicable for dummy PC.
This rule does not cover 5VHVFET

JZ382
1.
2.
3.

Description

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3.18 Butted-Junction Design Rules


Butted junctions are formed when RX diffusion abutting (RX over JZ) or (RX over JX). This intersection forms an
n+ junction and a p+ substrate contact or a p+ junction and an n+ n-well contact within the same RX shape.
Note: Butted junctions are not recommended in analog, matching, or performance-critical circuits because device
degradation can occur when a butted junction is in close proximity (0.5m) to a FET.
Table 3-19. Butted-Junction Design Rules
Rule

note

Description

Design

JX370a

Butted n+diffusion minimum space to PFET gate_side in the same RX.

0.230

JX372

RX butted n-well contact minimum overlap of JX.

0.080

JX372a

RX butted n-well minimum contact area (m2).

0.021

JZ370a

Butted p+diffusion minimum space to NFET gate_side in the same RX.

0.23

JZ372

RX butted p-well contact minimum overlap of JZ.

0.080

JZ372a

RX butted p-well minimum contact area (m2).

0.021

JZ391

Butted P-Well contact over {[(NET gate side touching butted n+diffusion) with 0.13 extensions] sized
by 0.23} is prohibited

JX392

Butted N-Well contact over {[(PFET gate side touching butted p+diffusion) with 0.13 extensions] sized
by 0.23} is prohibited.

JZ393

(Butted n+diffusion with width < 0.15 m) maximum length.

0.400

JX394

(Butted p+diffusion with width < 0.15 m) maximum length.

0.400

Butted n+diffusion minimum space to PC in the same RX (butted p+diffusion with extension 0 < E1 <
0.13 m)

0.23

0.23

JX395

Butted p+diffusion minimum space to PC in the same RX (butted n+diffusion with extension 0
<E1<0.13 m)
This rule does not check below condition

JZ395
1.

1
1

Figure 3-19. Butted Junction Design Rules

n+diff

PC

JZ395

E1

p+
diff

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3.19 Bipolar Transistor Design Rules


40nm-LP offers both vertical n-well/substrate PNP bipolar transistor and vertical n+/pwell/deep nwell NPN bipolar
transistor.
The BIPOLAR marking layer is drawn over the emitter, which excludes the extension implant (BH/PH) from the RX
area (emitter).
Table 3-20. BIPOLAR Design Rules
Rule

Notes

Description

Design

BT1

BIPOLAR must be an orthogonal rectangle.

BT2

BIPOLAR minimum width (for BH or PH generation).

0.360

BT3

BIPLOAR minimum space and notch (for BH or PH generation).

0.360

BT4

(EG, DG, PC, SLVT, GY, IY, LVT, XW, LW, RVT, HVT, NR, PR, NCAP) must not touch BIPOLAR.

BT5

BIPOLAR minimum space to (EG, DG). (For BH or PH generation).

0.360

BT6

BIPOLAR minimum space to gate.

0.350

BT7

RX minimum within BIPOLAR.

0.140

BT7a

BIPOLAR must touch RX.

BT8

(RX p+ junction over BIPOLAR) must be an orthogonal rectangle.

BT9a

[(RX touching SBLK) over BIPOLAR] minimum.

2.0

BT9b

[(RX touching SBLK) over BIPOLAR] maximum.

10.0

BT11

SBLK overlap of (RX over BIPOLAR).

0.125

BT12

[(RX p+ junction touching BIPOLAR) edges] must be covered by SBLK.

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3.19.1 Vertical PNP Bipolar Trasistor


Table 3-21a. Vertical PNP Bipolar Transistor Design Rules
Rule

Description

Design

PNP1

(RX p+ junction over BIPOLAR) must be covered by VPNP.

PNP3

Guard ring of grounded RX substrate contacts (p+ collector) must surround the entire mesh of RX n-well
contacts (n+ base).

PNP5

VPNP must not touch T3

PNP6a

[Guard ring of RX substrate contacts for (NW touching BIPOLAR)] minimum width.

0.480

Figure 3-20. Recommended Vertical PNP Bipolar Transistor Layout

3.19.2 Vertical NPN Bipolar Transistor


Table 3-21b. Vertical NPN Bipolar Transistor Design Rules
Rule

Description

Design

NPN3

Guard ring of RX n-well contacts (n+ collector) must surround the entire mesh of RX triple-well contacts
(p+ base).

NPN6a

[Guard ring of RX n-well contacts for (T3 touching BIPOLAR)] minimum width.

0.480

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3.20 Thick-Oxide / Medium-Oxide LDMOS Design Rules


40NM-LP offer Thick-oxide and Medium-oxide LDMOS device for high-Voltage power management design.
LDMOS device is plug in logic baseline process without additional mask step requirement. LDMOS design layout
must mark by 5VHVFET with special rule.
Table 3-22. LDNMOS Design Rules
Rule

Note(s)

Description

Design

LDM1

5VHVFET minimum width

LDM1a

5VHVFET minimum space and notch

1.7

LDM4

(PC over 5VHVFET) overlap past LDMOS NFET gate edge

0.15

LDM4a

(PC over 5VHVFET) overlap past LDMOS PFET gate edge

0.15

LDM5

(PC over 5VHVFET) space to LDMOS RX n-well drain

0.15

LDM5a

(PC over 5VHVFET) space to LDMOS RX triple-well drain

0.15

LDM6

NW overlap of LDMOS NFET gate PC edge

0.22

LDM6a

(T3 not NW) overlap of LDMOS PFET gate PC edge

0.22

LDM7

NW minimum overlap of LDMOS RX n-well drain (in width direction)

0.62

LDM7a

LDMOS RX n-well drain minimum space to RX substrate guard ring

LDM7aR

LDMOS RX n-well drain maximum space to RX substrate guard ring

15

LDM7c

LDMOS RX triple-well drain minimum space to NW (in width direction)

0.62

LDM7d

LDMOS RX triple-well drain minimum space to RX n-well guard ring

LDM7dR

LDMOS RX triple-well drain maximum space to RX n-well guard ring (RX n-well contact
over 5VHVFET)

15

LDM8

LDMOS n+ source minimum space to RX substrate guard ring, the butted source and
RX guard ring is allowed.

0.18

LDM8a

LDMOS p+ source minimum space to RX n-well guard ring, the butted source and RX
guard ring is allowed.

0.18

LDM11

LDMOS RX guard ring must be surround and continuous.

(DG or EG) must within medium-oxide 5VHVFET

0.0

RX guard ring M1 contact line recommend to be continuous, the maximum gap between
gaps if broken.

10

LDMOS RX substrate guard ring within 5VHVFET

0.11

LDM10
LDM11a

LDM11b
LDM11c

LDMOS RX n-well guard ring must be surround by RX substrate guard ring

LDM11d

LDMOS RX substrate guard ring space to (NW over 5VHVFET)

0.38

LDM12

5VHVFET minimum space to RX n+ junction

1.5

LDM12a

5VHVFET minimum space to RX P+ junction

1.5

DGLDM13

LDMOS unit cell should include two PC gate fingers, multi-cell LDMOS compose by
LDMOS unit cell array.

DGLDM13a

LDMOS layout shall have alternative source and drain.

1: RX substrate guard ring shall be connect to the lowest potential for better latch-up immunity;
2: LDPMOS must surround by RX substrate guard ring, it is important when NMOS and LDMOS are adjacent.
3. GLOBALFOUNDRIES strongly recommend following figure 3-23 and figure 3-25 for multi-finger layout. This requirement is not
checked by DRC.

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Table 3-23. 2.5V and 3.3V Thick-oxide LDMOS Design Rules


Rule

Note(s)

Description

Design

DGLDM2

(LDMOS NFET channel gate over DG) minimum gate length

0.28

DGLDM2c

[(LDMOS NFET channel gate over DG) over OVERDRIVE] minimum gate length

0.40

DGLDM2R

(LDMOS NFET change gate over DG) maximum gate length

10

DGLDM2a

(LDMOS NFET channel gate over DG) minimum gate width

0.8

DGLDM2aR

(LDMOS NFET change gate over DG) maximum gate width

25

DGLDM3

(LDMOS PFET channel gate over DG) minimum gate length

0.28

DGLDM3c

[(LDMOS PFET channel gate over DG) over OVERDRIVE)] minimum gate length

0.40

DGLDM3R

(LDMOS PFET change gate over DG) maximum gate length

10

DGLDM3a

(LDMOS PFET channel gate over DG) minimum gate width

0.8

DGLDM3aR

(LDMOS PFET change gate over DG) maximum gate width

25

Table 3-24. Medium-oxide LDMOS Design Rules


Rule

Note(s)

Description

Design

EGLDM2

(LDMOS NFET channel gate over EG) minimum gate length

0.28

EGLDM2R

(LDMOS NFET change gate over EG) maximum gate length

10

EGLDM2a

(LDMOS NFET channel gate over EG) minimum gate width

0.8

EGLDM2aR

(LDMOS NFET change gate over EG) maximum gate width

25

EGLDM3

(LDMOS PFET channel gate over EG) minimum gate length

0.28

EGLDM3R

(LDMOS PFET change gate over EG) maximum gate length

10

EGLDM3a

(LDMOS PFET channel gate over EG) minimum gate width

0.8

EGLDM3aR

(LDMOS PFET change gate over EG) maximum gate width

25

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5VHVFET

LDM10

LDM11a

M1

RX
substrate
guard ring

5VHVFET

RX
substrate
RX
guard ring
LDM7a

LDM11b
DG

JZ

LDM7

JZ
LDM8
RX

LDM12

RX
RX
substrate
guard ring

N+
RX

LDM6 LDM4 LDM5

LDM2

RX

RX
RX n-well
drain

PC
NW

RX

LDM12a

JX

DG

P+

LDM1

LDM1a

LDM1a
DG
NW

RX n-well
guard ring

Bend gate
are prohibited

RX

JX

LDM7d

3T05b
JX

LDM7c
LDM8a

52
RX

Gate PC
Edge

RX

RX n-well RX
guard
ring
JZ

5VHVFET

LDM3

LDM6a
RX

PC

RX triplewell drain
LDM11d

RX

PC

NW

5VHVFET

DG

T3

JX

JZ

5VHVFET

RX
substrate
guard ring

Figure 3-21. LDMOS Design Rules

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T3

JZ

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LDM2 LDM4 LDM5

gate

p+

n+

PW

LDM6

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LDM8

gate

n+

NW

n+

p+

PW

Figure 3-22. Cross section view of LDMOS NFET key design rule

Figure 3-23. Recommended Multiple-Cell LDMOS NFET layout

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LDM3 LDM4a LDM5a

gate

n+

LDM6a

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LDM8a

gate

p+

p+

PW

NW

p+

n+

NW

DeepNWell

Figure 3-24. Cross section view of LDMOS PFET key design rule

Figure 3-25. Recommended Multiple-Cell LDMOS PFET layout

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3.21 NFET in N-Well Capacitor Design Rules


The NFET in n-well capacitor (NCAP) is an n+doped gate over an n-well. Thin oxide NCAP, Medium-oxide NCAP
and Thick-oxide NCAP devices are supported. To verify NCAP design requirements, contact your
GLOBALFOUNDRIES technical representative.
Table 3-25. NCAP Design Rules
Rule

Description

NC1a

[Gate over (NCAP, VAR)] minimum gate length.

0.200

NC1b

{[Gate over (NCAP, VAR)] over (EG, DG)} minimum gate length.

0.400

NC10a

[Gate over (NCAP, VAR)] minimum gate width.

0.400

NC20

(NCAP, VAR) shape must be orthogonal.

NC21

(NCAP, VAR) minimum width.

0.400

NC22

(NCAP, VAR) minimum space and notch.

0.120

NC23

NCAP must be within NW with coinciding permitted.

0.400

NCAP over (OP, ZVT, SBLK, SLVT, GY, IY, LVT, XW, LW, HVT, NR, PR, BIPOLAR, PRES, DRES,
VAR) is prohibited.
(VAR over NW) is prohibited over BIPOLAR, SBLK, OP, HVT, NR, PR, LVT, XW, LW, SLVT, GY, IY,
PRES, DRES, PCAP and ZVT.

NC29

[Gate over (NCAP, VAR)] must be within (NCAP, VAR).

0.160

NC29b

{[Gate over (NCAP, VAR)] over EG} must be within EG.

0.220

NC29c

{[Gate over (NCAP, VAR)] over DG} must be within DG.

0.220

NC30

Gate minimum space to (NCAP, VAR).

0.500

NC32

(NCAP, VAR) minimum space to RX.

0.13

NC33

RX minimum within (NCAP, VAR).

0.16

NC101b

[Gate over (NCAP, VAR)] minimum area.

0.64

NC24
NC24a

Design

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3.22 PFET in P-Well Capacitor Design Rules


The PFET in p-well capacitor (PCAP) is a p+doped gate over a p-well (triple-well option only). Thin oxide PCAP
Medium-oxide PCAP and Thick-oxide PCAP devices are supported.
Table 3-26. PCAP Design Rules
Rule

Description

Design

PC1a

[Gate over (PCAP, VAR)] minimum gate length.

0.2

PC1b

{[Gate over (PCAP, VAR)] over (EG, DG)} minimum gate length.

0.4

PC10a

[Gate over (PCAP, VAR)] minimum gate width.

0.4

PC20

(PCAP, VAR) shapes must be orthogonal.

PC21

(PCAP, VAR) minimum width.

0.400

PC22

(PCAP, VAR) minimum space and notch.

0.120

PC23

PCAP must be within (T3 not over NW) with coinciding permitted.

0.400

PC24

PCAP over (NW, SLVT, GY, IY, LVT, XW, LW, HVT, NR, PR, OP, NCAP, SBLK, BIPOLAR, PRES,
DRES, NCAP, VAR and ZVT) is prohibited.

PC24a

(VAR not over NW) is prohibited over BIPOLAR, SBLK, OP, HVT, NR, PR, LVT, XW, LW, SLVT, GY, IY,
PRES, DRES, NCAP and ZVT.

PC28

{Gate over [(PCAP, VAR) not over NW]} must be within JZ.

0.170

PC29

[Gate over (PCAP, VAR)] must be within (PCAP, VAR)

0.160

PC29b

{[Gate over (PCAP, VAR)] over EG} must be within EG.

0.220

PC29c

{[Gate over (PCAP, VAR)] over DG} must be within DG.

0.220

PC30

Gate minimum space to (PCAP, VAR).

0.500

PC31

(RX touching PCAP) touching NFET gate is prohibited.

PC31a

[RX touching (VAR not over NW)] touching NFET gate is prohibited.

PC32

(PCAP, VAR) minimum space to RX.

0.13

PC33

RX minimum within (PCAP, VAR).

0.16

PC101b

[Gate over (PCAP, VAR)] minimum area.

0.64

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3.23 Silicide-Blocked OP Resistor Design Rules


The OP mask level blocks the formation of silicide, creating n+ diffusion and p+ polysilicon resistors. Table 3-27
presents the design rules used to form the diffusion and polysilicon OP resistors.
Note: For ESD designs, use the SBLK level instead of the OP level to avoid excessive data preparation (see
Section 3.27 ESD Silicide-Blocking Design Rules).
Table 3-27. OP Resistor Design Rules
Rule

Notes

Description

Design

700a

(PC over PRES) must be within PRES.

0.140

701

PRES minimum space to RX with touching prohibited.

0.230

701a

PRES minimum space to (PC not over PRES) with touching prohibited.

0.240

702

PRES minimum width.

0.200

703

PRES minimum space and notch.

0.200

704

PRES must be orthogonal.

705

((RX not touching BPNWR) touching OP) must be within DRES.

0.190

706

DRES minimum space to (RX not over DRES) with touching prohibited.

0.230

706a

DRES minimum space to PC with touching prohibited.

0.240

707

DRES minimum width.

0.200

708

DRES minimum space and notch.

0.200

709

DRES must be orthogonal.

710

(RX over OP) minimum resistor length.

0.400

711

(RX over OP) minimum resistor width.

0.400

712

(PC over OP) minimum resistor length.

0.400

713

(PC over OP) minimum resistor width.

0.120

716a

(RX touching OP) over (EG, DG) is prohibited.

724

OP must be orthogonal.

725

OP minimum width.

0.200

726

OP minimum space and notch.

0.200

727

OP overlap past RX.

0.220

727d

OP minimum overlap past RX (with OP width > 10 m)

0.300

727e

OP minimum overlap past RX (with OP width 0.43 m)

0.300

728

OP minimum space to RX.

0.220

729a

OP minimum area (m2).

1.000

729b

OP minimum enclosed area (m2).

1.000

730

OP minimum overlap past PC.

0.220

730d

OP minimum overlap past PC (with OP width > 10 m).

0.300

730e

OP minimum overlap past PC (with OP width 0.43 m).

0.300

731

OP minimum space to PC.

0.300

732

(OP not over NWRES) over CA is prohibited.

733

[CA touching (PC touching OP)] minimum space to OP.

0.220

733a

[[CA touching (RX touching OP)] not touching BPNWR] minimum space to OP.

0.220

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Rule

Notes

Description

Design

734a

[(PC over PRES) over JZ] minimum space to JX.

0.140

734b

[(RX over DRES) over JZ] minimum space to JX

0.140

734c

[(RX over DRES) over JX] minimum space to JZ.

0.140

734d

[(RX over DRES) over JX] must be within JX.

0.140

734e

[(RX over DRES) over JZ] must be within JZ.

0.140

735a

[(PC over PRES) over JZ] must be within JZ.

0.140

735b

[(PC over PRES) over JX] must be within JX.

0.140

735c

[(PC over PRES) over JX] minimum space to JZ.

0.140

736

(OP not over (ESD_HBM or ESD_CDM)) over gate is prohibited.

736a

OP minimum space to gate with touching prohibited.

0.380

737

RX over ((PC not over (ESD_BM or ESD_CDM)) touching OP) is prohibited.

738

[(OP not touching BPNWR) intersect (RX or PC)] must be an orthogonal rectangle.

738b

[(OP not touching NWRES) over RX over DRES] must divide RX into two diffusion regions.

738c

(OP over PC over PRES) must divide PC into two polysilicon regions.

739a

RX minimum overlap past OP.

0.22

739aR

(RX not touching BPNWR) exact overlap past OP.

0.430

739b

PC minimum overlap past OP.

0.310

739bR

PC exact overlap past OP.

0.400

OP102

(PC over OP) minimum space and notch

0.180

1. This rule is not applicable to RX n-well contact & RX p-well contact


2. For accurate modeling.

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Figure 3-26. OP Resistor Design Rules (Page 2 of 2)

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3.24 Salicided Resistor Design Rules


This section describes the rules for N+/P+ Salicided Polysilicon and N+/P+ Salicided Diffusion Resistor
Table 3-30. Salicided Resistor Design Rules
Rule

Notes

Description

Design

SAL1

(PC over POLY_SAL) minimum width

0.060

SAL2

(PC over POLY_SAL) minimum length

0.120

SAL3

(RX over DIFF_SAL) minimum width

0.120

SAL4

(RX over DIFF_SAL) minimum length

0.240

SAL5

POLY_SAL minimum overlap past PC

0.000

SAL5a

POLY_SAL exact space to CA while (PC over POLY_SAL) width 0.29

0.000

SAL5b

POLY_SAL exact space to CA while (PC over POLY_SAL) width < 0.29

0.050

SAL6

DIFF_SAL minimum over past RX

0.000

SAL6a

DIFF_SAL exact space to CA while (RX over DIFF_SAL) width 0.29

0.000

SAL6b

DIFF_SAL exact space to CA while (RX over DIFF_SAL) width < 0.29

0.060

SAL7

RX is prohibited over (PC touching POLY_SAL)

1. Narrow width salicided resistor with dog-bone design at two end, the resistor length equal body RX or PC length.

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Figure 3-28. Salicided Poly Resistor

POLY_SAL

Figure 3-29. Salicided Diffusion Resistor

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3.25 N-Well Resistor Design Rules


This section describes the rules for N-Well under STI resistor. The length of the resistor is defined by (RX touching
NWRES) minimum space.
Table 3-31a. N-Well under STI Resistor Design Rules
Rule

Notes

Description

Design

NWRSTI06a

NWRES must be within RXEXCLUD.

NWRSTI07a

NWRES must be an orthogonal rectangle.

NWRSTI08a

NWRES must be within NW.

NWRSTI09a

Only two RX shapes over NWRES are permitted.

NWRSTI10

(RX p+ junction,T3, EG, DG, SLVT, LVT, HVT, NCAP, PCAP, ZVT, BIPOLAR) over NWRES is
prohibited.

NWRSTI05

(CA over NWRES) within RX.

0.300

NWRSTI05R

(CA over NWRES) within RX.

0.300

NWRSTI06

(CA over NWRES) within NWRES

0.300

NWRSTI07

(RX touching NWRES) minimum width.

0.96

NWRSTI08

(RX touching NWRES) minimum space

10.000

NWRSTI09

(RX touching NWRES) minimum space to JZ with touching prohibited.

0.400

NWRSTI16

(RX touching NWRES) must be within JX

0.400

NWRSTI17

(RX touching NWRES) overlap past NW

0.300

NWRSTI250

(NW touching NWRES) minimum width.

1.800

NWRSTI252b

(NW touching NWRES) minimum space to [NW or(NW touching NWRES)]

1.000

1.

Rules applicable only for N-Well under STI resistor

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0.000

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Figure 3-30. N-Well under STI Resistor Design Rules

NWRSTI250

NWRSTI05

NWRSTI06

NWRSTI17

NW/NWRES

NWRSTI08

NWRSTI07

NWRSTI09

RX

NW

CA

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Table 3-31b. N-Well Over Active Resistor Design Rules


This section describes the rules for N-Well Over Active resistor. The length of the resistor is defined by BPNWR
over NW between the two heads.
Rule

Notes

Description

Design

NWRRX10

(RX p+ junction,T3, EG, DG, SLVT, GY, IY, LVT, XW, LW, HVT, NR, PR, NCAP, PCAP, ZVT,
BIPOLAR) over BPNWR is prohibited.

NWRRX250

(NW over BPNWR) minimum resistor width.

1.800

NWRRX251

(NW over BPNWR) minimum resistor length.

3.600

NWRRX252

BPNWR minimum overlap past RX

0.240

NWRRX252b

(NW over BPNWR) minimum space to [NW or (NW over BPNWR)]

NWRRX15

OP minimum overlap past RX.

0.240

NWRRX16

(NW touching BPNWR) overlap past OP.

0.66

NWRRX17

(NW touching BPNWR) space to OP.

0.300

NWRRX17R

(NW touching BPNWR) space to OP.

0.300

NWRRX18

(NW over BPNWR) within RX

1.000

NWRRX19

CA minimum within (NW touching BPNWR)

0.300

NWRRX20

(OP over RX) overlap past JX exact value.

0.400

NWRRX21

CA exact space to ((OP touching BPNWR) over NW)

0.300

1.

Rules applicable only for N-Well over Active Resistor

Figure 3-31. N-Well over Active Resistor Design Rules

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3.26 Latchup Design Rules


3.26.1 Internal Latchup Design Rules
Table 3-32. Internal Latchup Design Rules
Rule

Notes

Description

Design

LUP09a

1,2

{[RX substrate contact area] / (NFET gate not over isolated p-well) area} with (2.1 Rule
268b)2 m tiling not over isolated p-well. Limits the amount of vertical SX resistance seen by
thin-oxide NFETs in a given tile not inside isolated p-well.

0.0000781

LUP09aTW

1,2

((RX triple-well contact area) / {[NFET gate over isolated p-well] area}) with (2.1 Rule
3T68b)2 m tiling over isolated p-well. Limits the amount of vertical p-well resistance seen by
thin-oxide NFETs in a given tile inside isolated p-well.

0.0000802

LUP09b

1,3

{(RX substrate contact area) / [(NFET gate not over isolated p-well) area]} with (2.1 Rule
268b)2 m tiling not over T3. Limits the amount of vertical SX resistance seen by thin-oxide
NFETs in a given tile outside isolated p-well.

0.0000961

LUP09bTW

1,3

[(RX triple-well contact area) / ({NFET gate over isolated p-well} area)] with (2.1 Rule
3T68b)2 m tiling over isolated p-well. Limits the amount of vertical p-well resistance seen by
thin-oxide NFETs in a given tile inside isolated p-well.

0.0000993

LUP10a

[(RX n-well contact area) / (PFET gate area)] with (2.1 Rule 268a)2 m tiling over NW.
Limits the amount of vertical n-well resistance seen by thin-oxide PFETs in a given tile over
NW.

0.0000170

LUP10b

[(RX n-well contact area) / (PFET gate area)] with (2.1 Rule 268a)2 m tiling over NW. Limit
the amount of vertical n-well resistance seen by thin-oxide PFETs in a given tile over NW.

0.0000210

LUP11a

1,2

({RX substrate contact area} / {[(NFET gate over DG) area] not over isolated p-well}) with
(2.1 Rule 268b)2 m tiling not over isolated p-well. Limits the amount of vertical SX
resistance seen by thick-oxide NFETs in a given tile not over isolated p-well.

0.0008710

LUP11aTW

1,2

({RX triple-well contact area} / {[(NFET gate over DG) area] over isolated p-well}) with (2.1
Rule 3T68b)2 m tiling over isolated p-well. Limits the amount of vertical p-well resistance
seen by thick-oxide NFETs in a given over isolated p-well.

0.0008710

LUP11b

1,3

({RX substrate contact area} / {[(NFET gate over DG) area] not over isolated p-well]} with
(2.1 Rule 268b)2 m tiling not over isolated p-well. Limits the amount of vertical SX
resistance seen by thick-oxide NFETs in a given tile not over isolated p-well.

0.0010900

LUP11bTW

1,3

({RX triple-well contact area} / {[(NFET gate over DG) area] over isolated p-well}) with (2.1
Rule 3T68b)2 m tiling over isolated p-well. Limits the amount of vertical p-well resistance
seen by thick-oxide NFETs in a given tile over isolated p-well.

0.0010900

{[RX n-well contact area] / [(PFET gate over DG) area]} with (2.1 Rule 268a)2 m tiling over
NW. Limits the amount of vertical n-well resistance seen by thick-oxide PFETs in a given tile
over NW.

0.0000952

{[RX n-well contact area] / [(PFET gate over DG) area]} with (2.1 Rule 268a)2 m tiling over
NW. Limits the amount of vertical n-well resistance seen by thick-oxide PFETs in a given tile
over NW.

0.0001190

LUP12a

LUP12b

1. Only substrate, n-well, and triple-well contact s touching CA are verified during DRC.
2. Applicable if bum-in or elevated voltage stressing will not occur.
3. Applicable if (1.5 x VDD) burn-in will occur.

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The following definitions apply to Figure 3-32.


NW
N-well contact
N-type gate
N-type DG gate
P-type gate
P-type DG gate
Rule
SX
Substrate
Substrate contact
Windows

N-well in Table 3-32.


(RX over JX) over NW.
(Gate over JX) not over NW.
N-type gate inside DG.
(Gate over JZ) over NW.
P-type gate inside DG.
Design rule in Table 3-32.
Substrate in Table 3-32.
Complement to NW.
(RX over JZ) not over (NW or Isolated P-Well).
Squares of size (2.1 Rule 268); windows are stepped across the data in increments of
[(2.1 Rule 268)/2].
Any substrate or n-well region within a window that does not contain either a substrate
contact or an n-well contact, respectively, is permitted.

Figure 3-32. Internal Latchup Design Rules (Page 1 of 2)

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Figure 3-32. Internal Latchup Design Rules (Page 2 of 2)

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The following guidelines apply to internal latchup designs:


1. All thin-oxide NFETs with channel lengths greater than 1.5 Rule 1 should not be checked.
2. All thin-oxide PFETs with channel lengths greater than 1.5 Rule 2 should not be checked.
3. All thick-oxide NFETs with channel lengths greater than 1.5 Rule DG1 (for DG or DGV devices) should not
be checked.
4. All thick-oxide PFETs with channel lengths greater than 1.5 Rule DG2 (for DG or DGV devices) should not
be checked.
5. For Rules LUP09a through LUP10b, the ratio is checked as follows:

6. In a given tile, the thick-oxide gate areas should be weighed by the ratio of Rule LUP11a/LUP09a (that is, DG
gate area Rule LUP11a/LUP09a) and the tile used should be the same as that used in Rule LUP09a.
7. In a given tile, the thick-oxide gate areas should be weighed by the ratio of Rule LUP11b/LUP09b (that is, DG
gate area Rule LUP11b/LUP09b) and the tile used should be the same as that used in Rule LUP09b.
8. In a given tile, the thick-oxide gate areas should be weighed by the ratio of Rule LUP12a/LUP10a (that is, DG
gate area Rule LUP12a/LUP10a) and the tile used should be the same as that used in Rule LUP10a.
9. In a given tile, the thick-oxide gate areas should be weighed by the ratio of Rule LUP12b/LUP10b (that is, DG
gate area Rule LUP12b/LUP10b) and the tile used should be the same as that used in Rule LUP10b.
10. For checking time improvement, n-wells with a ratio greater than or equal to 10 Rule LUP10a, LUP10b,
LUP12a, or LUP12b can be screened out as passed.
11. Signal pads (excluding power supply pads) identified using the net definitions defined in Section 3.27.1 Net
Definitions for ESD Checking will be checked for latchup rule compliance.
12. In latchup rule checking, window shapes either pass or fail. A gate will fail when it touches only a window that
fails and none that pass checking.

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3.27 ESD Silicide-Blocking Design Rules


While the OP level is used for blocked resistors, the SBLK level is used for blocked transistors. The SBLK level
enhances the ESD robustness of a design by marking areas where silicide should not be formed. SBLK requires
standard device data preparation.
Table 3-33. ESD Silicide-Blocking Design Rules
Rule

Notes

Description

Design

SB725

SBLK minimum width.

SB725a

(SBLK not over BIPOLAR) must be an orthogonal rectangle.

SB726

SBLK minimum space and notch.

0.200

SB727

SBLK overlap past RX with coinciding prohibited.

0.180

SB728

SBLK minimum space to RX with coinciding prohibited.

0.200

SB729a

SBLK minimum area (m2).

0.370

SB729b

SBLK minimum enclosed area (m2).

0.370

SB730

SBLK overlap past PC with coinciding prohibited.

0.200

SB730a

Gate minimum within SBLK.

0.200

SB730b

Gate minimum overlap past SBLK.

0.050

SB730c

Gate minimum overlap of SBLK.

0.050

SB730d

Gate overlap of (SBLK touching ESD_DRAINMARK)

0.050

SB731

1,2

(SBLK not over ESD_xx) minimum space to PC with coinciding prohibited.

0.240

SB731a

1,2

Gate minimum space to (SBLK not over ESD_xx).

0.240

SB731b

1,2

((Gate over ESD_xxx) not over SBLK) exact space to SBLK.

0.060

SB732

SBLK over CA is prohibited.

SB733

CA to adjacent SBLK.

0.200

SB734

SBLK over ESD_xxx minimum space to PC.

0.060

SB740

SBLK minimum space to OP.

0.400

SB741a

[SBLK over (RX or PC)] minimum space to JX.

0.070

SB741b

[SBLK over (RX or PC)] minimum within JX.

0.070

0.20

1. ESD_xxx is defined as either ESD_HBM or ESD_CDM.


2. SBLK to PC/gate spacing 0.06 m and 0.240 m does not imply that the space between SBLK and the gate must be resist-free after the
OP lithography process step (see Figure 3-38). SBLK to PC/gate spacing 0.06 m and 0.240 m on ESD NFET designs will result in a
(silicided) polysilicon gate and enables an improvement in ESD performance by preventing/reducing the amount of silicide formed in the
regions between SBLK and gate.
3. JX/JZ transitions on unsilicided RX or PC are forbidden.
4. For ESD devices following SB731b, when using nominal gate length of 40nm, with gate is without SBLK and source and drain have SBLK,
the actual SBLK to SBLK space can be 160nm. This will flag SB726. In order to satisfy SB726, gate length must be >= 80nm when gate is
without SBLK and drain and source have SBLK.

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Figure 3-33. Space Between SBLK and Gate

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Figure 3-34. ESD Silicide-Blocking Design Rules

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3.28 ESD Design Rules


The ESD rules given in this section cover baseline ESD checks that will be performed by the Design rule checker.
The ESD rules stated below only address the need for ESD devices for HBM and CDM protection, along with its
dedicated guard rings. These rules include layout parameters for baseline ESD devices based on MOSFET or
Diodes. Nodes connected to pads are not enumerated based on the actual resistance between the node and the
pad.
Technology device characterization data and additional extensive information on ESD protection implementation
will be available in a dedicated CMOS 40nm-LP ESD Reference Guide. Please contact your
GLOBALFOUNDRIES Semiconductor account manager if you require this document.
The ESD design rules in Table 3-34 below are designed to meet 2 kV Human Body Model (HBM) and 500 V
charged device model (CDM) requirements. To achieve 200V MM, the ESD devices must be sized up
approximately 50%.
Table 3-34. ESD Design Rule Assumptions
Description

Unit

Value

ESD diode turn-on voltage (per diode)

ESD diode on-resistance (per diode)

0.5

ESD NFET holding voltage (2.5 V ESD NFET)

ESD NFET on-resistance

1.6

VDD bus resistance in the path between the ESD diode and the resistance-capacitance
(RC) clamp

Ground bus resistance

0.5

RC clamp on-resistance

0.5

Resistance between pad and ESD device

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The design rules presented in Table 3-34 use the following syntax:

CDM resistor

A p+ polysilicon OP resistor placed in the path between an I/O signal pad and
receiver FET gates.

HBM NFET

An NFET-based ESD HBM (ED or non-ED) protection device comprised of a


grounded gate NFET with a drain connected to an I/O pad.

HC power supply pad

An I/O pad either labeled HC_POWER_ESD on the LBESD level or electrically


connected to an Mx metal and labeled HC_POWER_ESD on the MxESD level,
where Mx = M1M6.

I/O pad

DV wire-bond pad including signal and power pads.

I/O signal pad

All I/O pads either labeled FULL_ESD on the LBESD level or not otherwise identified
as LC power or HC power supply pads. I/O pads are treated as signal pads unless
otherwise specified.

LC power supply pad

An I/O pad either labeled LC_POWER_ESD on the LBESD level or electrically


connected to an Mx metal and labeled LC_POWER_ESD on the MxESD level,
where Mx = M1M6.

Table 3-35. ESD Design Rules


Rule

Notes

Description

Design

ESD0c

15

xxESD labels must be one of the following text strings:


CUSTOM_ESD
FULL_ESD
HC_POWER_ESD
LC_POWER_ESD
LC_POWER_WIRE_ESD
NO_PROTECT_HBM
WIRE_ESD
WIRE_ESD_ENDPT
TEST_PAD_NOESD (on LBESD and M5ESD only)
See Section Net Definitions for ESD Checking for label definitions and associated
checking.

ESD0d

Diode / bipolar-based, NFET-based, or SCR-based HBM device required. I/O


signal pads must be connected to:
One or more (RX n+ diffusions satisfying Rule ESD01a) and one or more (RX p+
diffusions satisfying Rule ESD01b),
One or more (RX n+ diffusions touching NFET gates, satisfying Rule ESD01c)

ESD0e

LC power supply pads must be connected to:


One or more (RX n+ diffusions satisfying Rule ESD01a) and one or more (RX p+
diffusions satisfying Rule ESD01b),
One or more (RX n+ diffusions touching NFET gates, satisfying Rule ESD01c), or
One or more (RX n+ diffusions touching NFET gates, satisfying Rule ESD01d).

ESD01a

N+/SX (p-well) diode/bipolar perimeter. (I/O signal pads, LC power supply pads)
must be connected to [RX n+ diffusion(s) within ESD_HBM] having a total
perimeter.

200

ESD01b

2, 3

P+/NW bipolar perimeter. (I/O signal pads, LC power supply pads) must be
connected to [RX p+ diffusion(s) within ESD_HBM] having a total perimeter.

200

ESD01c

Nonsalicided NFET width. (I/O signal pads, LC power supply pads) must be

330

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Design

connected to {[RX n+ diffusion(s) touching NFET gates] within ESD_HBM} with a


total gate width.
ESD01d

LC power supply pads must be connected to one or more [(RX n+ diffusions


touching NFET gates) within ESD_CLAMP] with a total gate width.

4000

ESD08

Minimizes current through a parasitic NPN (NW/SX/NW) during a negative-mode


HBM event. {[NW connected to I/O signal pads], [(NW within ESD_HBM)
connected to LC power supply pads]} minimum space to NW, different net.

1.5

ESD09

4,5,6

Minimizes current through a parasitic NPN (n+/SX/n+) during a negative-mode


HBM event. {[RX n+ diffusions connected to I/O signal pads], [(RX n+ diffusions
within ESD_HBM) connected to LC power supply pads]} minimum space to RX n+
diffusions, different net.

1.5

ESD10a

4,6

Minimizes current through a parasitic NPN (n+/SX/NW) during a negative-mode


HBM event. {[RX n+ diffusions connected to I/O signal pads], [(RX n+ diffusions
within ESD_HBM) connected to LC power supply pads]} minimum space to NW,
different net.

1.5

Minimizes current through a parasitic NPN (n+/PW/NW) during a negative-mode


HBM event. {[RX n+ diffusions connected to I/O signal pads], [(RX n+ diffusions
within ESD_HBM) connected to LC power supply pads]} minimum within p-well,
different net.

1.5

4,6

{[NW connected to I/O signal pads], [(NW within ESD_HBM) connected to LC


power supply pads]} minimum space to RX n+ diffusions, different net.

1.5

ESD10bTW

RX n+ diffusion minimum within (p-well touching {[NW connected to I/O signal


pads], [(NW over ESD_HBM) connected to LC power supply pads]}

1.5

ESD11d

The maximum gate length of 1.0V ESD NFET.


Decreases the parasitic NPN turn-on voltage of 1.0 V ESD NFETs. {[(Gate over
RVT) within ESD_HBM] touching [RX n+ diffusions connected to an I/O signal pad]}
maximum gate length.

0.08

ESD11e

The maximum gate length of 1.5V EG ESD NFET.


Decreases the parasitic NPN turn-on voltage of 1.5 V EG ESD NFETs. ({Gate
within [intersect (EG, EGV)] within ESD_HBM} touching {RX n+ diffusions
connected to an I/O signal pad}) maximum gate length.

0.16

ESD11f

The maximum gate length of 1.8V EG ESD NFET.


Decreases the parasitic NPN turn-on voltage of 1.8 V EG ESD NFETs. ({[(Gate
within EG) not over EGV] within ESD_HBM} touching {RX n+ diffusions connected
to an I/O signal pad}) maximum gate length.

0.25

ESD11g

The maximum gate length of 1.8V DG ESD NFET.


Decrease the parasitic NPN turn-on voltage of 1.8 V DG ESD NFETs. ({Gate within
[intersect (DG, DGV)] within ESD_HBM} touching {RX n+ diffusions connected to
an I/O signal pad}) maximum gate length.

0.33

ESD11h

The maximum gate length of 2.5V DG ESD NFET.


Decrease the parasitic NPN turn-on voltage of 2.5 V DG ESD NFETs. ({[(Gate
within DG) not over DGV, Overdrive] within ESD_HBM} touching {RX n+ diffusions
connected to an I/O signal pad}) maximum gate length.

0.41

ESD11i

The maximum gate length of 3.3V ESD NFET.


Decrease the parasitic NPN turn-on voltage of 3.3 V ESD NFETs. ({[(Gate within
[intersect (DG, OVERDRIVE)] within ESD_HBM} touching {RX n+diffusions
connected to an I/O signal pad}] maximum gate length.

ESD14b

[NW touching (RX n-well contact guard ring )] minimum width.(for wire-bond
designs).

0.50

ESD14c

[CA over (RX n-well contact guard ring)] maximum space.

10.0

ESD15a

(RX substrate contact guard ring width (for wirebond designs).

0.50

ESD10aTW

ESD10b

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Description

Design

(RX substrate contact guard ring under ESD_CDM) minimum width.

0.25

[CA over (RX substrate contact guard ring )] maximum space.

10.0

ESD15aa

8,9

ESD15b

ESD16

10

CA within (RX within ESD_HBM).

0.050

ESD17a

Limits the cathode (emitter)/anode (base) spacing on n+/SX (p-well) diodes/bipolar


devices. In addition rule checks for minimum contact area in diode diffusions.
{[RX n+ diffusion within ESD_HBM] sized by 1.0000 m} must touch {[CA over (RX
p-well contact)] having a total area 1.72[m2]}.

ESD17b

Limits the anode/cathode spacing on p+/NW bipolar devices. In addition rule


checks for minimum contact area in diode diffusions.
{[RX p+ diffusion within ESD_HBM] sized by 1.0000 m} must touch {[CA over (RX
n-well contact)] having a total area 1.72[m2]}.

ESD18a

Prohibits butted junctions in ESD protect devices. ((RX over JZ) touching (RX over
JX)) is prohibited over (ESD_HBM, ESD_CDM).

ESD19a

NFET gates touching (RX n+ diffusions connected to I/O signal pads) must satisfy
Rules ESD21-ESD27.

ESD21

11

MOSFET gates touching (RX diffusions connected to I/O signal pads) must be in
one of the following gate/SBLK configurations (see Figure ESD Design Rules for
MOSFET-based Protection and must meet one of the rules under ESD24):
(Single NFET) (can be fingered) with individual SBLK shapes on the source and
drain. (Figure 3-36a)
(Single NFET) (can be fingered) with one SBLK shape on the drain only with
SBLK to gate spacing exactly 0.06um. (Figure 3-36b)
(Single NFET) (can be fingered) with one SBLK shape on the drain overlapping
gate exactly by 0.05um (Figure 3-36c)
Single NFET (can be fingered) with one SBLK shape covering the entire device.
(Figure 3-36d)
Stacked NFET with (the drain-side SBLK shape covering one gate and landing
exactly 60nm from the source-side gate) and one SBLK shape on the source-side.
(Figure 3-36e)
Stacked NFET with (the drain-side SBLK shape covering one full gate and
partially on the source-side gate) and one SBLK shape on the source-side. (Figure
3-36f)
Stacked NFET with one SBLK shape covering the entire device. (Figure 3-36g)

PFET gates touching (RX diffusions touching SBLK connected to I/O signal pads)
must be in the following gate/SBLK configurations (see Figure ESD Design Rules
for MOSFET-Based Protection ):
(Single PFET (can be fingered) with one SBLK shape covering the entire device.
(Figure 3-36d)
(Single PFET) with individual SBLK shapes on the source and drain (Figure
3-36a)
Stacked PFET with one SBLK shape covering the entire device. (Figure 3-36g)

ESD FET layout should meet one of the following conditions:


1. Exact SBLK drawn width on the source side
[(SBLK not gate) touching (RX diffusion connected to an I/O signal pad) source
exact width.]
OR
2. Use LVS marker layer ESD_DRAINMARK on the drain side, refer to
figure 3-36b, 3-36c for the layer usage example (in this case, there is no
requirement for SBLK on source side)

0.20

ESD22

ESD24

11

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Description

Design

ESD25a

11

For a 1.0-V ESD FET (see Figure 3-36 ESD Design Rules for MOSFET-Based
Protection). (SBLK not gate) touching [RX diffusion (not touching (DG, DGV or
OVERDRIVE)) connected to an I/O signal pad] drain minimum width.

>

1.0

ESD25b

11

For a 1.5 V EG ESD FET (see Figure 3-36 ESD Design Rules for MOSFET-Based
Protection). (SBLK not gate) touching [RX diffusion (touching EG and EGV)
connected to an I/O signal pad] drain minimum width.

>

1.0

ESD25c

11

For a 1.8 V EG ESD FET (see Figure 3-36). (SBLK not gate) touching [RX diffusion
(touching EG) connected to an I/O signal pad] drain minimum width.

>

1.0

ESD25d

11

For a 1.8 V and 2.5 V DG ESD FET (see Figure 3-36). (SBLK not gate) touching
[RX diffusion (touching DG) connected to an I/O signal pad] drain minimum width.

>

1.0

ESD25e

11

For thick-oxide 3.3 V ESD FETs. {SBLK not gate} touching {RX n+ diffusion
[touching (DG and OVERDRIVE)] connected to an I/O signal pad} drain minimum
width.

>

1.5

ESD26

SBLK overlap of [gate connected to (LC power supply pad or HC power supply pad)
and not connected to (RX substrate contact or RX p-well contact)].

>

0.050

ESD30

({[RX n+ diffusion(s), RX p+ diffusion(s)] over ESD_CDM} and their enclosing


guard rings}) must be within ESD_CDM.

ESD30a

All gates connected to an I/O signal pad must be connected through a CDM resistor

ESD30b

All gates connected to an I/O signal pad must be connected to one or more [RX
diffusions covered within ESD_CDM].

ESD39a

13

CDM resistor (resistor within ESD_CDM) must be a p+ polysilicon OP resistor; all


other types of resistors are prohibited.

ESD40

13

CDM resistor (p+ polysilicon OP resistor within ESD_CDM) minimum length.

3.5

Use of label CUSTOM_ESD is not permitted without prior approval from the
GLOBALFOUNDRIES Semiconductor ESD design technical representative

ESDCUST

ESD Design Rules notes


1. Separate ESD_HBM shapes must be drawn around the p+ n-well diodes, n+ substrate diodes, and NFET HBM protection
devices to enable proper DRC recognition. One ESD_HBM shape is used per device type. The shapes must cover the n+
substrate diode n-well guard ring, p+ n-well diode substrate guard ring, and/or the HBM NFET clamp n-well guard ring. See
Figure ESD Design Rules for Diode-Based Protection and Figure ESD Design Rules for MOSFET-Based Protection.
2. For a diode string, each p+ n-well diode in the diode string needs to meet this design rule.
3. These diodes can also be integrated into a PFET driver that does not have an ESD_HBM shape.
4. RX diffusion and NW shapes that are covered by the same ESD_HBM marker shape are exempt from these rules. NW
shapes that are terminals of the same string diode are also exempt.
5. Device terminals (for example, NFET gates, n+ diffusion OP resistors, and so forth) are exempt from this rule when one
terminal is connected to an I/O pad. This exemption also applies to parallel device terminal connections.
6. This rule does not apply for (diffusions not touching PC) with an area < 1.0 m2.
7. The driver NFET gate lengths should always be greater than the ESD NFET gate lengths.
8. ESD_CDM is a dummy shape placed over ESD CDM protection structures.
9. The maximum CA spacing only applies within the wide area of the RX substrate contact guard ring used to satisfy Rule
ESD15a and ESD15aa.
10. This rule does not apply for (diffusions not over PC) with an area < 1.0 m2.
11. For DRC, a stacked gate configuration is done by checking for gates touching diffusions that do not contain any CA shapes.
These gates are considered stacked devices.
13. Resistors in series or parallel cannot be added together in DRC to satisfy ESD resistance thresholds. ESD_CDM enclosing
p+ polysilicon OP resistor must not be shared by other devices, like FET or diode.
14. Not coded in DRC.
15. The nets that are labeled with CUSTOM_ESD are exempt from all ESD rules, and require prior permission from
GLOBALFOUNDRIES ESD team before using in layout.

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Backend ESD design guidelines


The ESD design guidelines given in Table 3-36 below are designed to meet 2 kV Human Body Model (HBM) and
500 V Charged-Device Model (CDM) requirements. These are considered as good ESD layout practices. These
guidelines are not implemented in the deck and therefore designer should ensure that these guidelines are met for
achieving good ESD robustness.
Table 3-36. Backend ESD Design guidelines
Rule

Description

Design

ESD02

Via requirements for ESD device connection. Each [M(x+1) over Mx] area on the
net connecting I/O pads to [(RX n+ diffusions, RX p+ diffusions) within
(ESD_HBM, ESD_CLAMP)] must contain connecting Vx vias with a total area
(mm2) Mx and M(x + 1) are sequential metal levels in the stack and Vx is the via
level that connects the two metal levels. For example, if Mx = M1, then M(x + 1) =
M2 and Vx = V1.

0.8

ESD03a

Contact requirements for ESD device connection. Each [RX n+ diffusion within
(ESD_HBM, ESD_CLAMP, must contain CA contacts having a total area (m 2).

1.5

ESD03b

Each (RX p+ diffusion within (ESD_HBM, ESD_CLAMP) must contain CA


contacts having a total area (m2).

1.5

ESD04

Metal width requirements for ESD device connection. {M1 connecting I/O pads to
[(RX n+ diffusions, RX p+ diffusions) within (ESD_HBM, ESD_CLAMP)]} width.

15

ESD05

{Mx connecting I/O pads to [(RX n+ diffusions, RX p+ diffusions) within


(ESD_HBM, ESD_CLAMP)} width, where Mx = M2-M6.

15

ESD05d

{Bx connecting I/O pads to [(RX n+ diffusions, RX p+ diffusions) within


(ESD_HBM, ESD_CLAMP)]} width, where Bx = B1-B3.

ESD05e

{Bx connecting I/O pads to [(RX n+ diffusions, RX p+ diffusions) within


(ESD_HBM, ESD_CLAMP)]} minimum width, where Bx = BA, BB, or BD.

ESD05f

{Ex connecting I/O pads to [(RX n+ diffusions, RX p+ diffusions) within


(ESD_HBM, ESD_CLAMP)]} minimum width, where Ex = EA or EB.

4.5

ESD06

{LB connecting I/O pads to [(RX n+ diffusions, RX p+ diffusions) within


(ESD_HBM, ESD_CLAMP)]} minimum width.

2.6

The following guidelines apply to ESD designs:


1) If fingered metal lines are used in the ESD path, the sum of the fingered line widths and via areas must be used
to satisfy Rules ESD02 through ESD06a.
2) ESD_HBM shapes should be drawn to cover all RX shapes associated with the ESD design that are connected
to the I/O pad.
3) All pads identified using the net definitions defined in Section 3.28.2 will be checked for ESD rule compliance.
4) GLOBALFOUNDRIES recommends tying both the transistor source and substrate to the same ground to
prevent the formation of a parasitic diode between any two grounds.
5) Rules ESD04 through ESD06a must be modified for each technology, depending on the number and thickness
of the metal levels.
6) Rules ESD11d, ESD11h, and ESD11i should be calculated as 1.201.25 times the base rule minimum.
7) Rule ESD15a applies only to non-epitaxial technologies. The values for Rules ESD15a and ESD15b should be
greater than or equal to the base rule minimum.
8) A CDM resistor length of 2.75 m will permit a maximum of 40 V across the resistor.

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Figure 3-35. ESD Design Rules for Diode-Based Protection

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Figure 3-36. ESD Design Rules for MOSFET-Based Protection (Page 1 of 3)

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Figure 3-36. ESD Design Rules for MOSFET-Based Protection (Page 2 of 3)

Figure 3-36a

Figure 3-36b

Figure 3-36c

Figure 3-36d

Fully Salicide-Blocked Single ESD


NFET/PFET (ESD Device Only)

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Figure 3-36. ESD Design Rules for MOSFET-Based Protection (Page 3 of 3)

Figure 3-36e

Figure 3-36f

Figure 3-36g

Fully Salicide-Blocked Stacked ESD


NFET/PFET (ESD Device Only)

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Figure 3-37. ESD Design Rules for CDM Protection

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3.28.1 Net Definitions for ESD Checking


For cell-level testing, all nets that will be connected to chip pads should be labeled with one of the labels defined
below. These text labels must be placed on an xxESD design level, where xx = M1, M2, and so forth.
For chip-level testing, only the FULL_ESD, HC_POWER_ESD, or LC_POWER_ESD labels are valid for chip pads.
GLOBALFOUNDRIES treats all unlabeled chips pads as FULL_ESD and checks them as I/O signal pads. Chip
pad text labels must be placed within the chip pad region (for example, the DV or LV passivation opening layer) and
require the LBESD design level. The HC_POWER_ESD and LC_POWER_ESD labels on the xxESD level are
used for cell-level checking. They can also be used to identify chip pads if the pads use the LBESD design level as
described above. Chip pads connected to metal levels containing xxESD text labels are treated as power supply
pads.
The text labels used to initiate ESD checking are as follows:
FULL_ESD

Used to check all ESD and latchup design rules for signal pads with ESD protection.

HC_POWER_ESD

Used to check power supply pins that achieve a chip capacitance of 100 nF between
the supply and ground. Metal ESD Rules (ESD02ESD06) apply.

LC_POWER_ESD

Used for check power supply pins that do not achieve a chip capacitance of 100 nF
between the supply and ground.

LC_POWER_WIRE_ESD

Used to check power supply nets that do not achieve a chip capacitance of 100 nF
between the supply and ground and whose HBM protection is provided by another
cell that connects to the chip pad. Back-end-of-line (BEOL) ESD rules
(ESD02ESD06) apply between LC_POWER_WIRE_ESD and
WIRE_ESD_ENDPT.

NO_PROTECT_HBM

Used to check non-HBM protected cells wired to a pad. All ESD design rules except
Rules ESD01ESD06 apply.

WIRE_ESD

Used to check metal width, contact, and via areas for wide wire-like cells (without
ESD protection) or pad transfer cells. BEOL ESD rules (ESD02ESD06) apply
between LC_POWER_WIRE_ESD and WIRE_ESD_ENDPT. Rules
ESD08ESD017 apply to an LC power supply pad.

WIRE_ESD_ENDPT

Used to define a termination point for wide metal checking of cell I/O pads labeled
WIRE_ESD and LC_POWER_WIRE_ESD within a cell (for example, wide wire cell).

TEST_PAD_NOESD

In test sites and kerfs, used to define a pad that does not have ESD protection
devices connected to it. None of the ESD design rules are applicable on these pads.
CHIPEDGE touching TEST_PAD_NOESD labels will flag an informational warning
message that ESD checking is being bypassed. LBESD is the only level that permits
these labels. These labels will be ignored on any other design or utility level.

Figure 3-38. WIRE_ESD ENDPT Text Label (Example)

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3.28.2 ED P+ Implant for ESD


Table 3-37. ED Design Rules
Rule

Notes

Description

Design

EDX01

ED minimum width.

0.500

EDX02

ED minimum space and notch.

0.500

EDX03

ED minimum space to PC.

0.500

EDX03b

ED over PC is prohibited.

EDX04

ED must be within RX.

0.500

EDX05

CA within ED.

0.500

EDX06

ED shapes must be orthogonal.

1.000

1.000

EDX07a
EDX07b

ED minimum area (m )
2

ED minimum enclosed area (m )

Figure 3-39. ED Design Rules

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3.29 Contact Design Rules


Contacts (CAs) connect either RX and M1 or PC and M1.
Table 3-38. CA Design Rules
Rule

Notes

Description

Design

200

(CA not touching EFUSE) exact width and length.

0.060

201

CA must be an orthogonal rectangle.

203

CA minimum space.

0.080

203a

CA minimum space, when CA has 3 or more neighbours (<0.11 m distance).

0.10

203c

CA minimum space (different net).

0.110

203e

CA maximum distance to (CA or RX_end) over (RX with width < 0.15 m).

18

203f

CA maximum distance to (CA or PC_end2 or gate) over (PC with width < 0.08 m).

18

204

CA minimum within RX.

0.010

204R

CA minimum within RX.

0.030

204_or

At least one CA per RX diffusion and M1 intersection containing a CA must meet Rule (204a
or 204b).

204a

RX minimum overlap past CA for two opposite sides with the others two sides 0.010 m.

0.030

204aR

RX minimum overlap past CA for two opposite sides with the other two sides 0.010 m.

0.040

204b

CA minimum within RX. (Rectangular enclosure 4 sides).

0.020

204eR

Minimum ratio of [(CA over (RX not over OP)) area] / ((RX not over OP) diffusion area).

0.050

207

(CA over RX) minimum space to gate.

0.040

207R

(CA over RX) minimum space to gate.

0.050

207bR

(CA over RX) minimum space to PC inner vertex.

0.070

207cR

{Total length of [CA within 0.08 m spacing of PC side edges with run length > 0 m to PC
sides]/[2 x gate width] maximum ratio (%).

28

208

(CA over PC) minimum space to RX.

0.050

208aR

(CA over PC) minimum space to RX inner vertex.

0.070

208b

(CA over RX) minimum space to [(Gate over DG) not over DGV]

0.080

208c

(CA over RX) minimum space to [(Gate over EG) not over EGV]

0.080

209_or

At least one CA per PC and M1 intersection containing a CA must meet Rule 209a OR 209b

209a

PC minimum overlap past CA for two opposite sides with the other two sides 0.010.

0.020

209aR

(PC not touching EFUSE) minimum overlap past CA for two opposite sides with the other two
sides 0.010.

0.040

209b

PC overlap past CA for two opposite sides with the third side 0.005 m and a fourth side
0.015 m.

0.030

211

CA over gate is prohibited.

212

CA must be within RX or PC.

0.000

228

CABAR must be within (GUARDRNG or crackstop ring).

229

CABAR exact width.

0.089

230

CABAR minimum length.

0.211

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Rule

Notes

232

CABAR minimum space.

0.144

233

CABAR minimum space to CA with touching prohibited.

0.166

240

(CA over RX) must not straddle (butted JX/JZ edge)

241

CA over RX minimum space to (butted JX/JZ edge)

0.040

1.
2.
3.
4.
5.
6.
7.

Description

Design

Exact length and width requires CA to be an orthogonal rectangle.


This rule is covered by the grid check (Rule S1), the acute angle check (Rule S6), and the exact width and length via check.
RX_end = (RX edge with length < 0.15 m) between two (outer vertices connected to edges of length > 0.015 m)
PC_end2 = (PC edge with length < 0.08 m) between two (outer vertices connected to edges of length > 0.015 m).
PC vertex is defined as a PC jog with a jog length > 0.035 m.
Only applies for diffusions containing three or more CAs. CA run length is the sum of the total CA run length on both PC sides.
This rule must satisfy either Rule 204 or 209.

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Figure 3-40. Design Rule 203e

Figure 3-41. Design Rule 203f

0.08

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3.30 1x Metal and Via Design Rules


Table 3-39. M1 Design Rules
Rule

Notes

500

M1 minimum width.

0.070

500b

M1 maximum width.

4.500

501a

M1 minimum area (m2).

0.021

(M1 width all edges less than 0.17 m) minimum area (m2)

0.055

501aSE

14

Description

Design

501b

M1 minimum enclosed area (m2).

0.200

502

M1 minimum space and notch.

0.070

502R

20

M1 minimum space and notch.

0.09

502iR

M1 minimum space to M1 connected to [(RX or Gate) touching EG]

0.080

502jR

M1 minimum space to M1 connected to [(RX or Gate) touching DG]

0.100

503_or

4,5

For (M1_end with length < 0.09 m), the M1_end must meet rule 503a or 503b

503a

M1_LE minimum space to M1 for run length > 0 m

0.080

503b

M1_LS minimum space to M1 for run length > 0 m

0.080

504f

M1 minimum space to (M1 with width > 0.190 m) for run length > 0.30 m.

0.080

504g

M1 minimum space to (M1 with width > 0.265 m) for run length > 0.30 m.

0.120

504h

M1 minimum space to (M1 with width > 0.345 m) for run length > 0.440 m.

0.140

504i

M1 minimum space to (M1 with width > 0.685 m) for run length > 0.685 m.

0.210

504j

M1 minimum space to (M1 with width > 1.65 m) for run length > 1.65 m.

0.500

M1 minimum width between 2 non-M1 regions [one of the non M1 area > 4,000,000um^2]

0.350

504kR

18

504lR

M1 minimum space to (M1 with width > 0.180 m to < 0.220 m) for run length > 0.300 m

>

0.090

505

M1 overlap past CA must meet rules (505a and 505b) or 505c or (505d and 505e)

505R

M1 overlap past CA recommend to meet rules 505aR or 505bR

505a

CA must be within M1.

0.000

505aR

CA must be within M1.

0.030

0.030

0.050

M1 minimum overlap past CA for at least two opposite sides with the other two sides
0.000 m. (Rectangular enclosure)
M1 minimum overlap past CA for at least two opposite sides with the other two sides
0.000 m (Rectangular enclosure).

505b

505bR

505c

M1 minimum overlap past CA for four sides (Rectangular enclosure).

0.020

505d

CA must be within M1.

0.005

505e

M1 minimum overlap past CA for at least two opposite sides with the other two sides
0.005 m. (Rectangular enclosure)

0.025

508aR

((M1/RX intersections) touching CA) must touch 2 CAs.

508bR

((M1/PC intersections) touching CA) must touch 2 CAs.

511

[CA within (M1 with width > 0.700 m)] minimum within M1.

0.030

[CA touching (M1 with width >= 0.110 m, space <0.08 m for run length>0.27 m)] must
be within M1.

0.015

512

19, 21

539a

(M1 OR M1FILL) minimum density (%) with 50.000 um tilling within CHIIPEDGE.

15

539b

(M1 OR M1FILL) maximum density (%) with 50.000 m tiling within CHIIPEDGE.

85

(M1 OR M1FILL) maximum density difference (%) between any two 200 m adjacent tiles
within M1EXCLUD (stepping in 200 m increments).

40

(M1 at 45-degrees) minimum width

0.170

542a

15

580

13, 16

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Rule

Notes

Description

Design

581

13

(M1 at 45-degrees) minimum space to M1

0.170

582

13

(M1 at 45-degrees) minimum edge length

0.260

584

4, 17

M1 line end must be rectangular. Other shapes are not allowed.

1.

Before DRC, certain enclosed metal areas will be filled in. To identify which enclosed area;
apply the following steps:
a) Identify enclosed areas that are < 0.8m wide and < 1.0m2 area.
b) Size the enclosed areas in step a) by +4.0 m inside the original metal layer and union.
c) For each union find the ratio of: (enclosed area)/(union area)
d) If the ratio calculated in step c is <8%, all enclosed areas within the union are filled only for the purposes of checking maximum
width; original design data is un-modified.
2. Rule does not apply to nets connected to triple well or substrate.
3. Nets connect to GND (connected to Pwell contacts) are excluded from this check.
4. M1_end = (M1 edge width length < 0.280 m) between two (outer vertices connected to edges of length > 0.07 m).
5. In situations where the M1_end is not connected to two (outer vertices connected to edges of length 0.070 m), 503_or is not
checked for that line end. (See Figure M1_LE and M1_LS for 503_or).
6. M1_LE corresponds to M1_end extended out by 0.025 m off each end. (See Figure M1_LE and M1_LS for 503_or).
7. M1_LS corresponds to the 0.07 m M1 side extended out beyond the M1_end by 0.25 m . (See Figure M1_LE and M1_LS for
503_or).
8. A CA that has an edge failing 510 will pass if it meets the following criteria: If the failing CA is within 0.220 m of a CA that passes 510
by the methods outlined in either of the 2 subsequent footnotes or it itself passes GR510. All CA considered must touch the same
metal above and the same [(RX not PC), PC] below.
9. A CA that has an edge failing 510 will pass if it meets the following criteria: Identify the edge opposite this failing edge. If there is
another CA within 0.220 m that has a run length > 0 m with this opposite edge, the CA passes 510. All CA considered must touch
the same metal above and same [(RX not PC), PC] below.
10. A CA that has an edge failing 510 will pass if it meets the following criteria: A CA within 0.220 m of the failing CA passing rule 505c
and 505d and not covered by (M1 with width > 0.220 m). All CA considered must touch the same metal above and same [(RX not PC),
PC] below.
11. Redundant CA is defined as a contact (CA) that has another CA within the same intersection of [M1 and (PC not RX)] or [M1 and (RX
not PC)]
12. Mx_predicted (T) is defined in Table F-5 Predicted Densities
13. Only rules 580, 581 and 582 are applicable to M1 at 45-degrees.
14. Rule 501aSE does not include the pattern filling 0.07 m x 0.17 m rectangular
15. Anticipate metal density gradient from layout of small cell by targeting density ~40% (this way, it will limit the risk of low density and of
high gradient
16. Make sure the vertex of 45 degree pattern is on 5nm grid
17. This rule is not DRC checked
18. Rule 504kR is for mask ESD concern. Non M1 region is defined as [NOT (M1 or M1FILL1)]
19. This rule check does not include two or more CAs present in the metal intersection
20. Mx not over (HCVNCAP, VNCAPHV)
21. This rule is to check the edge which parallel to the metal only, see Figure 3-42

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Figure 3-42. M1_LE and M1_LS for 503_or

M1
CA

> 0.27
512

>= 0.11
< 0.08

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Table 3-40. V1 Design Rules


Rule

Notes

Description

Design

550

Vx exact length and width; where x = 1-6.

0.070

553

Vx minimum space; where x = 1-6.

0.070

553a

Vx minimum space (for Vxs on different nets), where x = 1-6

0.095

553b

Vx minimum space (for Vxs on different nets with run length > 0), where x = 1-6

0.110

553c

Vx minimum space, when Vx has three or more neighbors with distance less than 0.098 m,
where x = 1-6

0.090

557

Vx must be an orthogonal rectangle, where x = 1-6.

570

M1 minimum overlap past V1 must meet rule (570a and 570b) or (570c and 570d)

570R

M1 minimum overlap past V1 recommend to meet rule 570aR or 570bR

570a

V1 must be within M1.

0.000

570aR

V1 must be within M1.

0.030

570b

M1 minimum overlap past V1 for at least two opposite sides with the other two sides 0.000
m (rectangular enclosure).

0.030

570bR

M1 minimum overlap past V1 for at least two opposite sides with the other two sides 0.000
m (rectangular enclosure).

0.050

570c

V1 must be within M1.

0.010

570d

M1 minimum overlap past V1 for at least two opposite sides with the other two sides 0.010
m (rectangular enclosure).

0.020

571

6,7

[V1 touching (M1 with width >= 0.110 m space <0.08 m for run length>0.27 m)] must be
within M1.

0.015

573R

((M1/ M2 intersections) touching V1) must touch 2V1s

577

45-degree rotated Vx is not allowed, where x = 1-6.

590

VxBAR exact width, where x = 1-6.

0.078

590a

VxBAR minimum length, where x = 1-6.

0.233

591

VxBAR minimum space, where x = 1-6.

0.155

591a

VxBAR minimum space to Vx with touching prohibited, where x = 1- 6.

0.155

593

VxBAR must be within (GUARDRNG or IND), where x = 1- 6.

0.000

1. Vx_array is defined to be (Vx sized by + 0.065 m, then sized by - 0.240 m, then sized by + 0.175 m).
2. This via array rule is derived from {Vx expanded by [Vx - 5 grid points in m], shrunk by [(-3.5 x Vx) + 5 grid points in m],
expanded by [2.5 x Vx]}.
3. Same net only. Different net vias are limited by Rule 553a & b.
4. Redundant V1 is defined as a via that has another via within the same intersection of the metal below and the metal above.
5. Intent of rule is to enforce redundancy on > 100 m metal lines. Mx line end = (Mx edge with length < 0.260 m) between two (outer vertices
connected to edges of length > 0.015 m).
6. This rule check does not include two or more V1s present in the metal intersection
7. This rule is to check the edge which parallel to the metal only, see Figure 3-43

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Figure 3-43. 1x Metal and Via Design Rules (Page 1 of 4)

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Figure 3-43. 1x Metal and Via Design Rules (Page 2 of 4)


M1

M1

505a/c/d

M1
570a/c

CA

V1

570a/c
V1

570b/d

570b/d

Mx

Mx
610a/610a_or

610a/610a_or

Vx
610b/610b_or

M1
V1

M1

Vx
610b/610b_or

The via having no common


run lenghth are exempted
from 571 checking

V1

> 0.27
571
> 0.27

>= 0.11
< 0.08

>= 0.11
< 0.08

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Figure 3-43. 1x Metal and Via Design Rules (Page 3 of 4)

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Figure 3-43. 1x Metal and Via Design Rules (Page 4 of 4)

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Table 3-41. Mx and Vx Design Rules


Rule

Notes

600

600aR

17, 21

Description

Design

Mx minimum width, where x = 2-7.

0.070

Mx minimum width {when Mx on {[(Mx-1 OR Mx-1FILL) with space >= 5um x 5um] sizing up
virtually to 1um, where x = 2-7.

0.120

600b

Mx maximum width, where x= 2-7.

4.500

601a

Mx minimum area (m2), where x = 2-7.

0.027

601aSE

(Mx with all edges length less than 0.21 m) minimum area (m2), where x = 2-7

0.060

601b

Mx minimum enclosed area (m2), where x = 2-7.

0.200

602

Mx minimum space and notch, where x = 2-7.

0.070

602R

22

Mx minimum space and notch, where x = 2-7.

0.090

602iR

Mx minimum space to Mx connected to [(RX or GATE) touching EG], where x = 2-7

0.080

602jR

Mx minimum space to Mx connected to [(RX or GATE) touching DG] where x = 2-7

0.100

603_or

4,5

For (Mx line-end with width < 0.100), the Mx line must obey 603a or 603b, where x = 2-7

603_orR

4,5

For (Mx line-end with width < 0.100), the Mx line must obey 603aR or 603bR, where x = 2-7

603a

Mx_LE minimum space to Mx for run length > 0 m.

0.100

603aR

Mx_LE minimum space to Mx for run length > 0 m.

0.120

603b

Mx_LS minimum space to Mx for run length > 0 m.

0.100

603bR

Mx_LS minimum space to Mx for run length > 0 m.

0.120

604f

Mx minimum space to (Mx with width > 0.190 m) for run length > 0.30 m, where x=2-7.

0.100

604g

Mx minimum space to (Mx with width > 0.265 m) for run length > 0.30 m, where x=2-7.

0.120

604h

Mx minimum space to (Mx with width > 0.345 m) for run length > 0.440 m, where x=2-7.

0.150

604i

Mx minimum space to (Mx with width > 0.685 m) for run length > 0.685 m, where x=2-7.

0.210

604ia

Mx minimum space to (Mx with width > 1.65 m) for run length > 1.65 m, where x=2-7.

0.500

604jR

20

Mx minimum width between 2 non-Mx regions [one of the non Mx area > 4,000,000um^2],
where x=2-7.

0.350

610

Mx overlap past Vx must meet rules (610a and 610b) or (610a_or and 610b_or), where x =
2-6.

610R

Mx overlap past Vx recommend to meet rules 610aR or 610bR, where x = 2-6.

610a

Vx must be within Mx, where x = 2-6.

0.000

610aR

Vx must be within Mx, where x = 2-6.

0.030

610b

Mx minimum overlap past Vx for two opposite sides with the other two sides 0.000 m,
where x = 2-6. (Rectangular enclosure)

0.030

610bR

Mx minimum overlap past Vx for two opposite side with the other two sides 0.000 m , where
x = 2-6. (Rectangular enclosure).

0.050

610a_or

Vx minimum within Mx, where x = 2-6.

0.010

610b_or

Mx minimum overlap past Vx for two opposite sides with the other two sides 0.010 m,
where x = 2-6. (Rectangular enclosure)

0.020

611

M(x+1) overlap past Vx must meet rules 611a and 611b or 611a_or and 611b_or, where x =
1-6.

611R

M(x+1) overlap past Vx recommend to meet rules 611aR or 611bR, where x = 1-6.

611a

Vx must be within M(x+1), where x = 1-6.

0.000

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Notes

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Description

Design

611aR

Vx must be within M(x+1), where x = 1-6.

0.030

611b

M(x+1) minimum overlap past Vx on two opposite sides with the other two sides 0.000 m,
where x = 1-6 (rectangular enclosure)

0.030

611bR

M(x+1) minimum overlap past Vx on two opposite sides with the other two sides 0.000 m,
where x = 1-6 (rectangular enclosure) (611_or must also be met)

0.050

611a_or

Vx minimum within M(x+1), where x = 1-6.

0.010

611b_or

M(x+1) minimum overlap past Vx for two opposite sides with the other two sides 0.010 m,
where x = 1-6. (Rectangular enclosure)

0.020

612a_MV

18

612c_MV

19

At least [two (Vx vias spaced 0.140 m) or four (Vx vias spaced 0.630 m)] must connect
Mx to M(x+1) when the Mx or M(x+1) width is > 0.210 m and area > 0.0441 m2, where x =
1-6
At least [four (Vx vias spaced 0.140 m) or nine (Vx vias spaced 0.830 m) must connect
Mx to M(x+1) when the Mx or M(x+1) width is > 0.550 m and area > 0.3025 m2, where x =
1-6

613a

At least 2 Vx within the same intersection must be used for a connection that has a Vx 1.14
m (d) away from a metal plate with width > 0.210 m (w) and area > 0.0441 m2, where x =
1-6. See Figure titled Explanation of exact configurations applied to 613

613b

At least 2 Vx within the same intersection must be used for a connection that has a Vx 2.80
m (d) away from a metal plate with width > 1.40 m (w) and area > 1.960 m2, where x = 1-6.
See Figure titled Explanation of exact configurations applied to 613

613c

At least 2 Vx within the same intersection must be used for a connection that has a Vx 7.10
m (d) away from a metal plate with width > 2.10 m (w) and area > 14.7 m2, where x = 1-6.
See Figure titled Explanation of exact configurations applied to 613

614R

Single Vx is not allowed in H-shape M(x+1) when all of the following conditions are met: (1)
The M(x+1) has H-shape interact with two enclosed metal areas: both enclosed metal area
length (EL2) 5.000 m and both enclosed metal area 5.0 m2. (2) The Vx overlaps on the
center metal bar of this H-shape M(x+1). (3) The length (EL1) of the center metal bar 1.000
m and the width of metal bar is 0.210 m, where x = 1-4

616R

((Mx/M(x+1) intersections) touching Vx must touch 2Vxs, where x = 2-6

620

Vx must be fully covered by Mx and Mx+1, where x = 1-6.

633

10

634

85

635

90

15

70

20

636
637
636R

(Mx OR MxFILL) minimum density (%) with 125.000 m tiling within CHIIPEDGE, where x =
2-7.
(Mx OR MxFILL) maximum density (%) with 125.000 m tiling within CHIIPEDGE, where x =
2-7.
(Mx OR MxFILL) maximum density (%) over any 20.000 m tiling (checked by stepping in
10um increments), where x = 2-7.
(Mx OR MxFILL) minimum density (%) with 25.000 m tiling within MxEXCLUD, where x =
2-7.
(Mx OR MxFILL) maximum density (%) with 100.000 m tiling within MxEXCLUD, where x =
2-7.
(Mx OR MxFILL) minimum density (%) over 10.000 m tiling within MxEXCLUD, (checked by
stepping in 5um increments), where x = 2-7.

642

(Mx OR MxFILL) Maximum difference (%) between any two 50 m adjacent tiles within
MxEXCLUD (stepping in 50um increments), where x = 2-7.

40

645

VxEXCLUD must be within CHIPEDGE, where Vx = V1- V6.

100

680

15

(Mx at 45-degrees) minimum width, where x = 2-7.

0.170

681

15

(Mx at 45-degrees) minimum space to Mx, where x = 2-7.

0.170

682

15

(Mx at 45-degrees) minimum edge length, where x = 2-7.

1.000

683R

16,17

It is not allowed to have local density > 70% of all 3 consecutive metal (Mx, Mx+1 and Mx+2)
over any 50um tiling (stepping 25), i.e. it is allowed for either one of Mx, Mx+1 or Mx+2 to have a
local density <= 70%.

684

5, 17

Mx line-end must be rectangular. Other shapes are not allowed

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Rule
1.

2.
3.
4.
5.
6.
7.
8.
9.

10.

11.

13.
14.
15.
16.
17.
18.
19.
20.
21.

22.

Notes

Description

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Design

Before DRC, certain enclosed metal areas will be filled in. To identify which enclosed areas
a) Identify holes that are < 0.8 m wide and < 1.0m2 in area.
b) Size the enclosed areas in step (a) by +4.0 m inside the original metal layer and union.
c) For each union, find the ratio of (enclosed area)/(union area).
d) If the ratio calculated in step (c) is < 8%, all enclosed areas within the union are filled only for the purposes of checking maximum
width; original design data is un-modified.
Rule does not apply to nets connected to triple well or substrate.
Nets connect to GND (connected to Pwell contacts) are excluded from this check.
In situations where the Mx_end is connected to one (outer vertices connected to an edge of length < 0.100 m), 603_or is not
checked for that line end. (See Figure M1_>E and M1_LS for 603_or)
Mx_end = (Mx edge with length < 0.280 m) between two (outer vertices connected to edges of length > 0.07 m), Any other Mx is
defined as a Mx side.
Mx_LE corresponds to Mx_end extended out by 0.035 m off each end. (See Figure Mx_LE and M1_LS for 603_or).
Mx_LS corresponds to the 0.100 m Mx1 side extended out beyond the M1_end by 0.035 m. (See Figure M1_LE and M1_LS for
603_or)
Redundant Vx is defined as a via that has another via within the same intersection of the metal below and the metal above, where x =
2-7.
To prevent open circuit reliability failures, redundant vias are required on all 1x and 2x via levels used to electrically connect two metal
levels (1x or 2x) where wither metal shape is greater than the wide metal criteria of Rules 612a-612c, 2x72a-2x72cb, 2Ax72a2Ax72cb, and 2Bx72a-2Bx72cb.
A Via that has an edge failing 615 will pass if it meets the following criteria: If the failing Via is within 0.220 m of a Via that passes 615
by the methods outlined in either of the 2 subsequent footnotes or it itself passes GR615. All Vias considered must touch the same
metal above and below.
A Via that has an edge failing 615 will pass if it meets the following criteria: Identify the edge opposite this failing edge.
If there is another Via within 0.220 m that has a run length > 0.000 m with this opposite edge, the Via passes 615.
All Vias considered must touch the same metal above and below
Mx_predicted (T) is defined in Table F-5 Predicted Densities.
My_predicted (T) is defined in Table F-5 Predicted Densities.
Only rules 680, 681 and 682 are applicable to Mx at 45-degrees.
a) The metal layers include M1 / Mx and dummy metals.
b) The check does not include chip corner stress relief pattern, seal ring and top2 metals at CUP area.
This rule is not DRC checked
[two (Vx vias spaced 0.140 m)] is defined to be two Vx vias inside (Vx sized by 0.14/2)
[four (Vx vias spaced 0.630 m)] is defined to be four Vx vias inside (Vx sized by 0.63/2)
[four (Vx vias spaced 0.140 m)] is defined to be four Vx vias inside (Vx sized by 0.14/2)
[nine (Vx vias spaced 0.830 m)] is defined to be nine Vx vias inside (Vx sized by 0.83/2)
Rule 604jR is for for mask ESD concern. Non-Mx region is defined as [NOT (Mx OR MxFILL)]
Step1: find Mx-1 or Mx-1 fill with size greater than 5um X5um
Step 2: size up 1um virtually the polygon
Step 3: check for Mx width on Mx-1 or Mx-1FILL to be above 0.12um
Mx not over (HCVNCAP, VNCAPHV)

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Figure 3-44. Mx_LE and Mx_LS for 603_or

Figure 3-45. Explanation of exact configurations applied to 613

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Figure 3-46. Explanation of 614

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Figure 3-47. Groundrule 615 Exemption 1 and 2.

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Figure 3-48. Groundrule 615 Exemption 3.

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Figure 3-49. Wide-Metal Via Design Rules

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3.31 2x Metal and Via Design Rules


The 2x (thick) metal and via levels are at a 2x pitch compared to the 1x levels.
Notes:
1. 2x wires and vias are offered in low-k dielectric and TEOS/FTEOS dielectric. 2x wire levels for the low-k
dielectric are L1-L4. 2x wire levels for the oxide process are BA, BB, BD, BE, and BG. The BC and BF levels
are used for the front-end-of-line (FEOL) process and cannot be used for 2x wiring.
2. The 2x via levels for the low-k process are J0-J3 and the 2x via levels for the oxide process are WT, WA, WB,
WD, and WE.
Table 3-42. 2x Metal Design Rules in Low-K Dielectric
Rule

Notes

Description

Design

2Ax00

Lx minimum width, where x = 1-4.

0.140

2Ax00b

Lx maximum width, where x = 1-4.

12.000

Lx minimum width {when Lx on {[(Lx-1 or Lx-1FILL) with space >= 5um x 5um] sizing 1um},
where x = 1-4.

0.200

2Ax00cR

2, 5

2Ax01a

Lx minimum area (m2), where x = 1-4.

0.070

2Ax01b

Lx minimum enclosed area (m2), where x = 1-4.

0.200

2Ax02

Lx minimum space and notch, where x = 1-4.

0.140

2Ax04

Lx minimum space to (Lx with width > 0.21 m) for run length >= 0.52 m, where x = 1-4.

0.190

2Ax04b

Lx minimum space to (Lx with width > 1.5 m) for run length >= 1.5 m, where x = 1-4.

0.500

2Ax04e

Lx minimum space to (Lx with width > 4.5 m) for run length >= 4.5 m, where x = 1-4.

1.500

2Ax04fR

Lx minimum width for non-Lx region to (non-Lx region with area > 4,000,000 m2), where x
= 1-4, non-Lx = [NOT (Lx or LxFILL)

0.350

2Ax06a

Jx must be within Lx+1. where x = 0-3. the via must be within the metal above.

0.005

2Ax06aR

Jx must be within Lx+1. where x = 0-3. the via must be within the metal above.

0.050

2Ax06b

Lx+1 minimum overlap past Jx for two opposite sides with the other two sides 0.005 m.
(Rectangular enclosure), where x = 0-3.

0.050

2Ax06bR

Lx+1 minimum overlap past Jx for two opposite sides with the other two sides 0.005 m.
(Rectangular enclosure), where x = 0-3.

0.080

2Ax40a

(Lx OR LxFILL) minimum density (%) with 25.000 m tiling within LxEXCLUD, where x =
1-4.

15

2Ax40b

(Lx OR LxFILL) maximum density (%) with 100.000 m tiling within LxEXCLUD, where x =
1-4.

70

2Ax41a

(Lx OR LxFILL) minimum density (%) with 50.000 m tiling within CHIIPEDGE, where x =
1-4.

15

2Ax41b

(Lx OR LxFILL) maximum density (%) with 20.000 m tiling (checked by stepping in 10um
increments), where x = 1-4.

70

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Rule
2Ax42a

2Ax42bR

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Description

Design

(Lx OR LxFILL) Maximum difference (%) between any two 50.000 m adjacent tiles within
LxEXCLUD (stepping 50um increments), where Lx = L1, L2, L3, L4, L5.

30

3, 5

It is not allowed to have local density > 70% of all 3 consecutive metal (Lx, Lx+1 and Lx+2)
over any 50um tiling (stepping 25), i.e. it is allowed for either one of Lx, Lx+1 or Lx+2 to have a
local density <= 70%. where x = 1-4.

2Ax45

(Lx at 45-degrees) minimum width (run length > 0 m), where x = 1-4.

0.400

2Ax46

(Lx at 45-degrees) minimum space to Lx (run length > 0 m), where x = 1-4.

0.400

2Ax47

(Lx at 45-degrees) minimum edge length, where x = 1-4.

1.000

1. Before DRC, certain enclosed metal areas will be filled in. To determine which enclosed areas.
a. Identify holes that are < 1.8 m wide and < 3.5 m2 in area.
b. Size the enclosed areas in step (a) by +4.0 m inside the original metal layer and union.
c. For each union, find the ratio of (enclosed area)/(union area).
d. If the ratio calculated in step is < 18%, all enclosed areas within the union are filled only for the purpose of checking maximum width;
original design data is un-modified
2. Step1: find Lx-1 or Lx-1 fill with size greater than 5um X5um
Step 2: size up 1um virtually the polygon
Step 3: check for Lx width on Lx-1 or Lx-1FILL to be above 0.2um
3. a) The metal layers include Lx and Lx dummy metals.
b) The check does not include crackstop and guard ring.
4. If customer doesnt draw LxFILL, DS will be needed.
5. This rule is not DRC checked

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Table 3-43. 2x Via Design Rules in Low-K Dielectric


Rule

Notes

Description

Design

2Ax49

JxEXCLUD must be within CHIPEDGE, where Jx = J0-J3.

100

2Ax50

Jx exact length and Width, where x = 0-3.

0.130

2Ax53

Jx minimum space, where x = 0-3.

0.150

2Ax54

Jx minimum space, when Jx has three or more neighbors with distance less than 0.190 m,
where x = 0-3

0.170

2Ax57

Jx must be an orthogonal rectangle, where x = 0-3.

2Ax60

J0 must be within MLAST1X.

0.005

2Ax60R

J0 within MLAST1x.

0.050

0.050

0.080

MLAST1X minimum overlap past J0 for two opposite sides with the other two sides 0.005
m. (Rectangular enclosure)
MLAST1X minimum overlap past J0 for two opposite sides with the other two sides 0.005
m. (Rectangular enclosure)

2Ax60aa

2Ax60aaR

2Ax60dR

Every MLAST1X and L1 intersection containing a J0 must contain two or more J0.

2Ax62

Jx must be within Lx, where x = 1-3; the via must be within the metal below.

0.005

2Ax62R

All Jx within Lx, where x = 1-3.

0.050

0.050

0.080

Lx minimum overlap past Jx for two opposite sides with the other two sides 0.005 m, where
x = 1-4. (Rectangular enclosure), where x = 1-3.
Lx minimum overlap past Jx for two opposite sides with the other two sides 0.005 m, where
x = 1-4. (Rectangular enclosure), where x = 1-3.

2Ax62aa

2Ax62aaR

2Ax62dR

Every Jx per Lx and L(x+1) intersection containing a Jx must contain two or more Jx, where x
= 1-3.

2Ax72Sa

At least [Two (J0vias spaced 0.290 m) or four (J0 vias spaced 0.570 m)] must connect
MLAST1X to L1 when the MLAST1X or L1 width > 0.420 m and area > 0.176 m2

2Ax72Sb

10

At least [Two (Jx vias spaced 0.290 m) or four (Jx vias spaced 0.570 m)] must connect
Lx to Lx+1 when the Lx or Lx+1 width > 0.420m and area > 0.176 m2. where x = 1-3.

2Ax72Sc

11

At least [Four (J0 vias spaced 0.290 m) or nine (J0 vias spaced 0.770 m)] must connect
MLAST1X to L1 when the MLAST1X or L1 width > 1.140 m and area > 1.3 m2

2Ax72Sd

12

At least [Four (Jx vias spaced 0.290 m) or nine (Jx vias spaced 0.770 m)] must connect
Lx to Lx+1 when the Lx or Lx+1 width > 1.140 m and area > 1.3 m2. where x = 1-3.

2Ax72Se

14

At least [Two (J0 vias spaced 1.7 m) must connect MLAST1X to L1 when the MLAST1X or
L1 width > 1.8 m and area > 3.24 m2.

2Ax72Sf

15

At least [Two (Jx vias spaced 1.7 m) must connect Lx to Lx+1 when the Lx or Lx+1 width >
1.8 m and area > 3.24 m2. where x = 1-3.

*2Ax73a

At least 2 J0 within the same metal intersection must be used for a connection that has a J0
1.400 m (d) away from a metal plate with width > 0.700 m (w) and area > 0.49 m2.

2Ax73aa

At least 2 Jx within the same metal intersection must be used for a connection that has a Jx
1.400 m (d) away from a metal plate with width > 0.700 m (w) and area > 0.49 m2. where
x = 1-3.

2Ax73b

At least 2 J0 within the same metal intersection must be used for a connection that has a J0
2.800 m (d) away from a metal plate with width > 2.000 m (w) and area > 4.0 m2.

2Ax73bb

At least 2 Jx within the same metal intersection must be used for a connection that has a Jx
2.800 m (d) away from a metal plate with width > 2.000 m (w) and area > 4.0 m2. where x
= 1-3.

2Ax73c

At least 2 J0 within the same metal intersection must be used for a connection that has a J0
7.100 m (d) away from a metal plate with width > 10 m (w) and area > 30 m2.

2Ax73cc

2Ax74

At least 2 Jx within the same metal intersection must be used for a connection that has a Jx
7.100 m (d) away from a metal plate with width > 10 m (w) and area > 30 m2. where x =
1-3.
Single J0 is not allowed in H-shape L1 when all for the following conditions are met: (1) The L1
has H-shape interact with two enclosed metal areas: both enclosed metal area length (EL2)
5.000 m and both enclosed metal area 5 m2. (2) The Vx overlaps on the center metal bar
of this H-shape L1. (3) The length (EL1) of the center metal bar 1.000 m and the width of
metal bar is 0.420 m.

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Rule
2Ax78R

Notes
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Description

Design

maximum consecutive stacked Vx / Jx layer, which has only one via for each Vx/Jx layer to
avoid high Rc

2Ax80

Jx must be fully covered by [MLAST1X and Lx+1] or [Lx and Lx+1], where x = 0-3.

2Ax90

JxBAR exact width, where x = 0-3.

0.155

2Ax90a

JxBAR minimum length, where x = 0-3.

0.466

2Ax91

JxBAR minimum space, where x = 0-3.

0.466

2Ax91a

JxBAR minimum space to Jx with touching prohibited, where x = 0-3.

0.466

2Ax93

JxBAR must be within (GUARDRNG or IND), where x = 0-3.

1. "Jx_array" is defined to be (Jx sized by + 0.135 m, then sized by - 0.485 m, then sized by + 0.350 m).
2. This via array rule is derived from {Jx expanded by [Jx - 5 grid points in m], shrunk by [(-3.5 x Jx) + 5 grid points in m], expanded by [2.5
x Jx]}.
3. This wide-metal J0 setback rule applies to both redundant and non-redundant J0 vias.
4. This wide-metal Jx setback rule applies to both redundant and non-redundant Jx vias, where x = 1-4.
5. Intent of rule is to enforce redundancy on > 100 m metal lines. MLAST1X line end = (MLAST1X edge with length < 0.420 m) between
two (outer vertices connected to edges of length > 0.015 m).
6. Intent of rule is to enforce redundancy on > 100 m metal lines. Lx line end = (Lx edge with length < 0.500 m) between two (outer
vertices connected to edges of length > 0.015 m).
8. Eg: VIA1-VIA4, VIA2-VIA5, VIA3-VIA6. This rule does not apply to top via. It is allowed to stack from VIA3 to VIA8 because VIA7 and VIA8
are top vias. It is allowed to stack > 4 Vx layers if 2 or more vias in each Vx layer are on the same metal.
9. [two (J0 vias spaced 0.290 m)] is defined to be two J0 vias inside (J0 sized by 0.29/2)
[four (J0 vias spaced 0.570 m)] is defined to be four J0 vias inside (J0 sized by 0.57/2)
10. [two (Jx vias spaced 0.290 m)] is defined to be two Jx vias inside (Jx sized by 0.29/2)
[four (Jx vias spaced 0.570 m)] is defined to be four Jx vias inside (Jx sized by 0.57/2)
11. [four (J0 vias spaced 0.290 m)] is defined to be four J0 vias inside (J0 sized by 0.29/2)
[nine (J0 vias spaced 0.770 m)] is defined to be nine J0 vias inside (J0 sized by 0.77/2)
12. [four (Jx vias spaced 0.290 m)] is defined to be four Jx vias inside (Jx sized by 0.29/2)
[nine (Jx vias spaced 0.770 m)] is defined to be nine Jx vias inside (Jx sized by 0.77/2)
13. This rule is not DRC checked
14. [two (J0 vias spaced 1.7 m)] is defined to be two J0 vias inside (J0 sized by 1.7/2)
15. [two (Jx vias spaced 1.7 m)] is defined to be two Jx vias inside (Jx sized by 1.7/2)

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Table 3-44. 2x Metal Design Rules in FTEOS Dielectric


Rule

Notes

Description

Design

2Bx00

Bx minimum width, where x = A, B, D, E, or G.

0.140

2Bx00b

Bx maximum width, where x = A, B, D, E, or G.

12.000

Bx minimum width {when Bx on {[(Bx-1 or Bx-1FILL) with space >= 5um x 5um] sizing 1um},
where x = A, B, D, E, or G.

0.200

2Bx00cR

2, 4

2Bx01a

Bx minimum area (m2), where x = A, B, D, E, or G.

0.070

2Bx01b

Bx minimum enclosed area (m2), where x = A, B, D, E, or G.

0.200

2Bx02

Bx minimum space and notch, where x = A, B, D, E, or G.

0.140

2Bx04

Bx minimum space to (Bx with width > 0.21 m) for run length >= 0.52 m, where x = A, B,
D, E, or G.

0.190

2Bx04b

Bx minimum space to (Bx with width > 1.5 m) for run length >= 1.5 m, where x = A, B, D,
E, or G.

0.500

2Bx04e

Bx minimum space to (Bx with width > 4.5 m) for run length >= 4.5 m, where x = A, B, D, E,
or G.

1.500

2Bx04fR

Bx minimum width for non-Bx region to (non-Bx region with area > 4,000,000 m2), where x
= A, B, D, E, or G, non-Bx = [NOT (Bx or BxFILL)

0.350

2Bx06a

(WT, WA, WB, WD, WE) must be within (BA, BB, BD, BE, BG); the via must be within the
metal above.

0.005

2Bx06aR

(WT, WA, WB, WD, WE) must be within (BA, BB, BD, BE, BG); the via must be within the
metal above.

0.050

2Bx06b

(BA, BB, BD, BE, BG) minimum overlap past (WT, WA, WB, WD, WE) for two opposite sides
with the other two sides 0.005 m.

0.050

2Bx06bR

(BA, BB, BD, BE, BG) minimum overlap past (WT, WA, WB, WD, WE) for two opposite sides
with the other two sides 0.005 m.

0.080

2Bx40a

(Bx OR BxFILL)minimum density (%) with 25.000 m tiling within BxEXCLUD, where x = A, B,
D, E, or G.

15

2Bx40b

(Bx OR BxFILL)maximum density (%) with 100.000 m tiling within BxEXCLUD, where x = A,
B, D, E, or G.

70

2Bx41a

(Bx OR BxFILL)minimum density (%) with 50.000 m tiling within CHIIPEDGE, where x = A,
B, D, E, or G.

15

2Bx41b

(Bx OR BxFILL)maximum density (%) with 20.000 m tiling(checked by stepping in 10um


increments), where x = A, B, D, E, or G.

70

2Bx42a

(Bx OR BxFILL) maximum difference (%) between any two 50.000 m adjacent tiles within
BxEXCLUD (stepping 50um increments), where x = A, B, D, E, or G.

30

It is not allowed to have local density > 70% of all 3 consecutive metal (Bx, Bx+1 and Bx+2) over
any 50um tiling (stepping 25), i.e. it is allowed for either one of Bx, Bx+1 or Bx+2 to have a local
density <= 70%. where x = A, B, or D, and (x + 1), (x + 2) = metal level above.

2Bx42bR

2, 3

2Bx45

(Bx at 45-degrees) minimum width (run length > 0 m), where x = A, B, D, E, or G.

0.400

2Bx46

(Bx at 45-degrees) minimum space to Lx (run length > 0 m), where x = A, B, D, E, or G.

0.400

2Bx47

(Bx at 45-degrees) minimum edge length, where x = A, B, D, E, or G.

1.000

1. Before DRC, certain enclosed metal areas will be filled in. To identify enclosed areas.
a. Identify holes that are < 1.8 m wide and < 3.5 m2 in area.
b. Size the enclosed areas in step a by +4.0 m inside the original metal layer and union.
c. For each union find the ratio of (enclosed area)/(union area).
d. If the ratio calculated in step (c) is < 18%, all enclosed areas within the union are filled only for the purposes of checking maximum
width; original design data is un-modified.
2. This rule is not DRC checked
3. a) The metal layers include Lx and Lx dummy metals.
b) The check does not include crackstop and guard ring.
4. Step1: find Bx-1 or Bx-1 fill with size greater than 5um X5um
Step 2: size up 1um virtually the polygon
Step 3: check for Bx width on Lx-1 or Bx-1FILL to be above 0.2um

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Table 3-45. 2x Via Design Rules in FTEOS Dielectric


Rule

Notes

Description

Design

2Bx50

Wx exact length and width, where x = T, A, B, D, or E.

0.130

2Bx53

Wx minimum space, where x = T, A, B, D, or E.

0.150

2Bx54

Wx minimum space, when Wx has three or more neighbors with distance less than 0.190 m,
where x = T, A, B, D, or E.

0.170

2Bx57

Wx must be an orthogonal rectangle, where x = T, A, B, D, or E.

2Bx60

WT must be within MLAST1X.

0.005

2Bx60R

WT within MLAST1X.

0.050

2Bx60aa

MLAST1X minimum overlap past WT for two opposite sides with the other two sides 0.005
m. (Rectangular enclosure)

0.050

2Bx60aaR

MLAST1X minimum overlap past WT for two opposite sides with the other two sides 0.005
m. (Rectangular enclosure)

0.080

2Bx60dR

Every MLAST1X and BA intersection containing a WT must contain two or more WT.

2Bx62

(WA, WB, WD, WE) must be within (BA, BB, BD, BE); the via must be within the metal below.

0.005

2Bx62R

All Wx within Bx, where x = A, B, D, E.

0.050

2Bx62aa

{BA, BB, BD, BE} minimum overlap past {WA, WB, WD, WE} for two opposite sides with the
other two sides 0.005 m. (Rectangular enclosure)

0.050

2Bx62aaR

{BA, BB, BD, BE} minimum overlap past {WA, WB, WD, WE} for two opposite sides with the
other two sides 0.005 m. (Rectangular enclosure)

0.080

2Bx62dR

Every {WA, WB, WD, WE} per {BA, BB, BD, BE} and {BB, BD, BE, BG} intersection containing
a {WA, WB, WD, WE} must contain two or more {WA, WB, WD, WE}.

2Bx72Sa

2Bx72Sb

2Bx72Sc

10

2Bx72Sd

11

2Bx72Se

13

At least [Two (WT vias spaced 1.7 m) must connect MLAST1X to BA when the MLAST1X
or BA width is > 1.8 m and area > 3.24 m2

2Bx72Sf

14

At least [Two (Wx vias spaced 1.7 m) must connect Bx to Bx+1 when the Bx or Bx+1 width
> 1.8m and area > 3.24 m2. where Wx = WA, WB, WD, or WE, Bx = metal level below, and
B(x + 1) = metal level above.

2Bx73

[WT touching (MLAST1X with width > 0.520 m)] must be within MLAST1X.

0.035

2Bx73a

2Bx73aa

At least 2 WT within the same metal intersection must be used for a connection that has a WT
1.400 m (d) away from a metal plate with width > 0.700 m (w) and area > 0.49 m2.
At least 2 Wx within the same metal intersection must be used for a connection that has a Wx
1.400 m (d) away from a metal plate with width > 0.700 m (w) and area > 0.49 m2.
where x = A, B, D, or E.

2Bx73b

At least 2 WT within the same metal intersection must be used for a connection that has a WT
2.800 m (d) away from a metal plate with width > 2.000 m (w) and area > 4.0 m2.

2Bx73bb

2Bx73c

2Bx73cc

At least [Two (WT vias spaced 0.290 m) or [Four (WT vias spaced 0.570 m)] must
connect MLAST1X to BA when the MLAST1X or BA width > 0.420m and area > 0.176 m2.
At least [Two (Wx vias spaced 0.290 m) or [Four (Wx vias spaced 0.570 m)] must
connect Bx to Bx+1 when the Bx or Bx+1 width > 0.420m and area > 0.176 m2. where Wx
= WA, WB, WD, or WE, Bx = metal level below, and B(x + 1) = metal level above.
At least [four (WT vias spaced 0.290 m) or nine (WT vias spaced 0.770 m)] must
connect MLAST1X to BA when the MLAST1X or BA width is > 1.140 m and area > 1.3 m2.
At least [four (Wx vias spaced 0.290 m) or (Wx vias spaced 0.770 m)] must connect Bx
to Bx+1 when the Bx or Bx+1 width > 1.140m and area > 1.3 m2. where Wx = WA, WB,
WD, or WE, Bx = metal level below, and B(x + 1) = metal level above.

At least 2 Wx within the same metal intersection must be used for a connection that has a Wx
2.800 m (d) away from a metal plate with width > 2.000 m (w) and area > 4.0 m2.
where x = A, B, D, or E.
At least 2 WT within the same metal intersection must be used for a connection that has a WT
7.100 m (d) away from a metal plate with width > 3.000 m (w) and area > 30 m2.
At least 2 Wx within the same metal intersection must be used for a connection that has a Wx
7.100 m (d) away from a metal plate with width > 3.000 m (w) and area > 30 m2. where
x = A, B, D, or E.

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Rule

2Bx74

2Bx78R

Notes

7, 12

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Description

Design

Single WT is not allowed in H-shape BA when all of the following conditions are met: (1) The
BA has H-shape interact with two enclosed metal areas: both enclosed metal area length
(EL2) 5 m and both enclosed metal area 5 m2. (2) The Vx overlaps on the center metal
bar of this H-shape BA. (3) The length (EL1) of the center metal bar 1.0 m and the width of
metal bar is 0.420 m.
maximum consecutive stacked Vx / Wx layer, which has only one via for each Vx/Wx layer to
avoid high Rc
(WT, WA, WB, WD, WE) must be fully covered by ([MLAST1X and BA], [BA and BB], [BB and
BD], [BD and BE], [BE and BG]).

2Bx80

2Bx90

WxBAR exact width, where x = T, A, B, D, or E.

0.155

2Bx90a

WxBAR minimum length, where x = T, A, B, D, or E.

0.466

2Bx91

WxBAR minimum space, where x = T, A, B, D, or E.

0.466

2Bx91a

WxBAR minimum space to Wx with touching prohibited, where x = T, A, B, D, or E.

0.466

2Bx93

WxBAR must be within (GUARDRNG or IND), where x = T, A, B, D, or E.

1. "Wx_array" is defined to be (Wx sized by + 0.135 m, then sized by - 0.485 m, then sized by + 0.350 m).
2. This via array rule is derived from {Wx expanded by [Wx - 5 grid points in m], shrunk by [(-3.5 x Wx) + 5 grid points in m],
expanded by [2.5 x Wx]}.
3. This wide-metal WT setback rule applies to both redundant and non-redundant WT vias.
4. This wide-metal Wx setback rule applies to both redundant and non-redundant Wx vias, where x = A, B, D, or E.
5. Intent of rule is to enforce redundancy on 100 m metal lines. MLAST1X line end = (MLAST1X edge with length < 0.420 m)
between two (outer vertices connected to edges of length > 0.015 m).
6. Intent of rule is to enforce redundancy on 100 m metal lines. BA, BB, BD, BE line end = (BA, BB, BD, BE edge with length
< 0.420 m) between two (outer vertices connected to edges of length > 0.015 m).
7. Eg: VIA1-VIA4, VIA2-VIA5, VIA3-VIA6. This rule does not apply to top via. It is allowed to stack from VIA3 to VIA8 because VIA7 and
VIA8 are top vias. It is allowed to stack > 4 Vx layers if 2 or more vias in each Vx layer are on the same metal.
8. [two (WT vias spaced 0.290 m)] is defined to be two WT vias inside (WT sized by 0.29/2)
[four (WT vias spaced 0.570 m)] is defined to be four WT vias inside (WT sized by 0.57/2)
9. [two (Wx vias spaced 0.290 m)] is defined to be two Wx vias inWside (Wx sized by 0.29/2)
[four (Wx vias spaced 0.570 m)] is defined to be four Wx vias inside (Wx sized by 0.57/2)
10. [four (WT vias spaced 0.290 m)] is defined to be four WT vias inside (WT sized by 0.29/2)
[nine (WT vias spaced 0.770 m)] is defined to be nine WT vias inside (WT sized by 0.77/2)
11. [four (Wx vias spaced 0.290 m)] is defined to be four Wx vias inside (Wx sized by 0.29/2)
[nine (Wx vias spaced 0.770 m)] is defined to be nine Wx vias inside (Wx sized by 0.77/2)
12. This rule is not DRC checked
13. [two (WT vias spaced 1.7 m)] is defined to be two WT vias inside (WT sized by 1.7/2)
14. [two (Wx vias spaced 1.7 m)] is defined to be two Wx vias inside (Wx sized by 1.7/2)

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Figure 3-50. 2x Metal and Via Design Rules

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3.32 1x to 6x Transitional Via Design Rules


The 1x to 6x transitional via level resides in the TEOS/FTEOS dielectric. 1x to 6x transitional vias are denoted as
OT.
Table 3-46. 1x to 6x Transitional Via Design Rules
Rule

Notes

Description

Design

6Bx50

OT exact length and width.

0.360

6Bx53

OT minimum space.

0.340

6Bx53c

OT minimum space, when OT has three or more neighbors with distance less than 0.560 m.

0.540

6Bx57

OT must be an orthogonal rectangle.

6Bx60

OT must be within MLAST1X; via must be within the metal below.

0.020

6Bx60aR

((MLAST1X/ FA intersections) touching OT) must touch 2 OTs

6Bx61

OT must be within FA.

0.020

6Bx61a

OT must be within MLAST1X on two opposite sides with the other two sides 0.020m.

0.080

6Bx62

OT must be within FA on two opposite sides with the other two side 0.020 m.

0.080

6Bx72aR

[(MLAST1X and FA intersections) touching OT] must have at least [(2 OT vias with space
1.7 m, when (MLAST1X or FA width and length > 1.8 m)

6Bx73aR

[(MLAST1X and FA intersections) touching OT] must have at least 2 OT vias if the intersection
is spaced 5.0 m from [(MLAST1X or FA) with width > 3.0 m, and area > 30 m 2]

6Bx80

OT must be fully covered by MLAST1X and FA

6Bx90

OTBAR exact width.

0.400

6Bx90a

OTBAR minimum length.

1.200

6Bx91

OTBAR minimum space.

1.200

6Bx91a

OTBAR minimum space to OT with touching prohibited.

1.200

6Bx93

OTBAR must be within (GUARDRING or IND).

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3.33 2x to 6x Transitional Via Design Rules


The 2x to 6x transitional via level resides in the TEOS/FTEOS dielectric. 2x to 6x transitional vias are denoted as
GM.
Table 3-47. 2x to 6x Transitional Via Design Rules
Rule

Notes

Description

Design

6Tx50

GM exact length and width.

0.360

6Tx53

GM minimum space.

0.340

6Tx53a

GM minimum space, when GM has three or more neighbors with distance less than 0.560 m.

0.540

6Tx57

GM must be an orthogonal rectangle.

6Tx60

GM must be within LLAST2X; via must be within the metal below.

0.020

6Tx60cR

((LLAST2X / FA intersections) touching GM must touch 2GMs

6Tx61

GM must be within FA.

0.020

6Tx61a

GM must be within LLAST2X on two opposite sides with the other two sides 0.020m

0.080

6Tx62

GM must be within FA on two opposite sides with the other two sides 0.020 m

0.080

6Tx72aR

[(LLAST2X and FA intersections) touching GM] must have at least [(2 GM vias with space
1.7 m, when (LLAST2X or FA width and length > 1.8 m)

6Tx73aR

[(LLAST2X and FA intersections) touching GM] must have at least 2 GM vias if the
intersection is spaced 5.0 m from [(LLAST2X or FA) with width > 3.0 m, and area > 30
m2]

6Tx80

GM must be fully covered by LLAST2X and FA

6Tx90

GMBAR exact width.

0.400

6Tx90a

GMBAR minimum length.

1.200

6Tx91

GMBAR minimum space.

1.200

6Tx91a

GMBAR minimum space to GM with touching prohibited.

1.200

6Tx93

GMBAR must be within (GUARDRING or IND).

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3.34 6x Metal and Via Design Rules


The 6x (thick) metal and via levels are at a 6x pitch compared to the 1x levels. The 6x metal and via levels reside in
the TEOS/FTEOS dielectric. 6x metal levels are denoted as FA and FB, while 6x via levels are denoted as OT.
Table 3-48. 6x Metal and Via Design Rules
Rule

Notes

6x00

6x00aR

4, 6

Description

Design

Fx minimum width, where x = A or B.

0.400

Fx minimum width {when Fx on {[(Fx-1 OR Fx-1FILL) with space >= 5um x 5um] sizing up virtually
to 1um, where x = A or B.

0.420

6x00b

Fx maximum width, where x = A or B.

12.000

6x01a

Fx minimum area (m2), where x = A or B.

0.565

6x01b

Fx minimum enclosed area (m2), where x = A or B.

0.565

6x02

Fx minimum space and notch, where x = A or B.

0.400

6x04a

Fx minimum space to (Fx with width > 1.65 m) for run length > 1.65 m, where x = A or B.

0.500

6x04b

Fx minimum space to (Fx with width > 4.95 m) for run length > 4.95 m, where x = A or B.

1.500

6x40a

(Fx OR FxFILL) minimum density (%) with 25.000 m tiling within FxEXCLUD, where x = A or B.

20

6x40b

(Fx OR FxFILL) maximum density (%) with 100.000 m tiling within FxEXCLUD, where x = A or B.

80

6x41a

(Fx OR FxFILL) minimum density (%) with 50.000 m tiling within CHIPEDGE, where x = A or B.

20

6x41b

(Fx OR FxFILL) maximum density (%) with 100.000 m tiling within CHIPEDGE, where x = A or B.

80

6x41e

(Fx OR FxFILL) maximum density (%) with 20.000 m tiling (10.000 m stepping increments),
where x = A or B.

90

(Fx OR FxFILL) maximum difference (%) between any two 100.000 um adjacent tiles within
MxEXCLUD (stepping in 100um increments), where x =A, B

40

6x42
6x49

Fx line-end must be rectangular. Other shapes are not allowed.

6x50

JR exact length and width.

0.360

6x53

JR minimum space.

0.340

6x53c

JR minimum space, when JR has three or more neighbors with distance less than 0.560 m.

0.540

6x57

JR must be an orthogonal rectangle.

6x61R

((FA / FB intersections) touching JR must touch 2JRs

6x62

JR must be within FA.

0.020

6x63

JR must be within FB.

0.020

6x64

JR must be within FA on two opposite sides with the other two sides 0.020 m.

0.080

6x65

JR must be within FB on two opposite sides with the other two side 0.020 m.

0.080

6x72aR

[(FA and FB intersections) touching JR] must have at least [(2 JR vias with space 1.7 m, when
(FA or FB width and length > 1.8 m)

6x73aR

[(FA and FB intersections) touching JR] must have at least 2 JR vias if the intersection is spaced
5.0 m from [(FA or FB) with width > 3.0 m, and area > 30 m.]

6x80

JR must be fully covered by FA and FB

6x90

JRBAR exact width.

0.400

6x90a

JRBAR minimum length.

1.200

6x91

JRBAR minimum space.

1.200

6x91a

JRBAR minimum space to JR touching prohibited.

1.200

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Notes

6x93

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Description

Design

JRBAR must be within (GUARDRNG or IND).

1. Before DRC, certain enclosed metal areas will be filled in. To identify enclosed areas.
a. Identify holes that are < 1.8 m wide and < 3.5 m2 in area.
b. Size the enclosed areas in step a by +4.0 m inside the original metal layer and union.
c. For each union find the ratio of (enclosed area)/(union area).
d. If the ratio calculated in step (c) is < 18%, all enclosed areas within the union are filled only for the purposes of checking maximum
width; original design data is un-modified.
2. Fx_predicted (T) is defined in Table F-5 Predicted Densities.
3. Bond pad is excluded from density check for rule 6x41a, 6x41b, 6x41e
4. This rule is not DRC checked
5. If customer doesn't draw FxFILL, DS will be needed.
6. Step1: find Fx-1 or Fx-1 fill with size greater than 5um X5um
Step 2: size up 1um virtually the polygon
Step 3: check for Fx width on Fx-1 or Fx-1FILL to be above 0.42um

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Figure 3-51. 6x Metal and Via Design Rules

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3.35 LB and VV Design Rules


LM is a reference level used to denote the last copper metal level in the selected BEOL metallization option.
Table 3-49. LB and VV Design Rules
Rule

Notes

LB00

LB00a

Description

Design

LB minimum width.

2.000

LB Width (Interconnection only)

2.000

LB00b

LB Width (Interconnection only)

35.000

LB00bR

Recommended total width of BUS line (connection with bump pad)

20

LB02

LB minimum space and notch.

2.000

LB04b

(LB not touching a DV terminal pad) minimum space to (LB with a width > 35 m).

4.000

LB05

LB Space to Fuse or LMARK

5.000

LB06a

(LB OR LBFILL) density inside CHIPEDGE

10%

LB06b

(LB OR LBFILL)density inside CHIPEDGE

70%

LB49

VV must be an orthogonal rectangle.

LB50

VV exact length and width.

3.000 or
2.000

LB53

VV minimum space.

2.000

LB70

VV must be within LM.

0.500

LB75

VV must be within LB.

0.500

LB90

VVBAR exact width.

1.388

LB90a

VVBAR minimum length.

2.000

LB91

VVBAR minimum space and notch.

2.000

LB91a

VVBAR minimum space to VV with touching prohibited.

2.000

LB93

VVBAR must be within crackstop ring or IND.

0.000

LBx43PD

LB_predicted (100) density, with the exemption of tile touching IND

10.000

1.
2.
3.
4.
1)
2)
3)

LM is a reference level used to denote the last copper metal level in the selected BEOL metallization option
LB_Predicted (T) is defined in Table F-5 Predicted Densities.
No DR check
LB interconnect is defined by:
for Wirebond: {LB NOT [[DV, RZ] sized by 2.2um]}
for flip chip [3 on 6]: {LB NOT [[LV ] sized by 18.2um]}
for flip chip [4 on 8, 4 on 9, 5 on 10]: {LB NOT [[LV] sized by 2.2um]}

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Figure 3-52. LB and VV Design Rules

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3.36 BEOL Vertical Natural Capacitor Design Rules


3.36.1 Hierarchal Vertical Natural Capacitor (HCVNCAP)
The hierarchal vertical natural capacitor (HCVNCAP) is constructed from via_finger and vialess_finger capacitor,
see Table 3-52 list all HCVNCAP metal schemes for available BEOL option. Missing metal levels are prohibited
because they affect the capacitance density calculation.

Figure 3-53. HCVNCAP Cross Section

M5
V4

Via_finger

M4

M3

Vialess_finger

M2

M1

Figure 3-54. HCVNCAP top view

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Table 3-50. HCVNCAP Design Rules


Rule

Notes

Description

Design

HCN100a

[(Mx over VNCAP_Mx) not over VNCAP_M(x - 1)] touching V(x - 1) is prohibited, where x =
2-7.

HCN100b

[(Mx over VNCAP_Mx) not over VNCAP_M(x + 1)] touching Vx is prohibited, where x = 1-6.

HCN110a

Mx via_finger exact width for Mx finger touching VNCAP_Mx, where x= 1-7.

0.100

HCN110b

Mx vialess_finger exact width for Mx finger not touching VNCAP_Mx, where x= 1-7.

0.07

HCN115

[HCVNCAP touching (VNCAP, VNCAPHV)] is prohibited

HCN120a

Mx via_finger exact space to Mx finger for Mx over VNCAP_Mx, where x = 1-7.

0.078

HCN120b

Mx vialess_finger exact space to Mx finger for Mx not over VNCAP_Mx, where x = 1-7.

0.07

HCN121a

Mx via_finger exact space to Mx strap, where x = 1-7.

0.250

HCN121b

Mx vialess_finger exact space to Mx strap, where x = 1-7.

0.250

HCN125

1,2

Mx over VNCAP_Mx must be either a strap or finger, where Mx = M1- M7.

HCN140

Vx exact space (within the same Mx via_finger touching VNCAP_Mx), where x = 4-6.

0.14

HCN155

Vx must be within [Mx over VNCAP_Mx] and [M(x + 1) over VNCAP_M(x + 1)], where x = 4-6.

0.015

HCN196

1,2

Vx minimum space to adjacent [Mx strap, M(x + 1) strap], where x = 4-6.

0.380

HCN199a

1,2

Mx strap minimum width, where x = 1-7.

0.130

HCN199b

1,2

Mx strap maximum width, where x = 1-7.

0.900

HCN199c

1,2

All Mx Strap edges have to be coincident with other Mx strap edges where Mx = M1- M7

HCN199d

1,2

Mx strap width within the same VNCAP_Mx must be equal

HCN510

Each Mx via_finger over VNCAP_Mx must be fully populated with Vx vias, where x = 4-6.

HCN520

Vx vias on adjacent fingers must be staggered (no common run length 0.000 m), where x =
4-6.

HCN575a

Adjacent (interdigitated) Mx via_fingers must be on different nets, where x = 1-7.

HCN575b

Adjacent (interdigitated) Mx vialess_fingers must be on different nets, where x = 1-7.

HCN576a

There must be exactly two nets touching the interdigitated Mx via_fingers of the capacitor,
where x = 1-7.

HCN576b

There must be exactly two nets touching the interdigitated Mx vialess_fingers of the capacitor,
where x = 1-7.

HCN588

VNCAP_Mx must be fully populated with Mx via_fingers, where x = 4-7.

HCNM1a

(HCVNCAP touching VNCAP_Mx) must cover (Mx via_finger), where Mx= M4- M7.

HCNM1b

(HCVNCAP touching VNCAP_Mx) must cover (Mx vialess_finger touching HCVNCAP),


where Mx= M4- M7.

HCNM2a

(VNCAP_Mx over HCVNCAP) must touch at least two Mx via_fingers, where Mx = M1- M7

HCNM2b

VNCAP_Mx must touch at least two Mx vialess_fingers, where Mx = M1- M7.

HCNM3

1,2

VNCAP_Mx must touch exactly two Mx straps, where Mx = M1- M7

HCNM5a

VNCAP_Mx minimum space to Mx, where Mx = M1- M7

0.25

HCNM5b

(Mx not over HCVNCAP) touching Mx via_fingers is prohibited, where Mx = M1- M7.

HCN0

When used for a capacitor, (Mx touching HCVNCAP) must be within HCVNCAP, where Mx =
M1 - M7.

HCNP1

HCVNCAP minimum width.

1.000

HCNP2

HCVNCAP minimum space.

1.000

HCNP3

HCVNCAP minimum area (m2).

4.000

HCNP4

HCVNCAP maximum area (mm2).

0.025

HCNP7

HCVNCAP exactly overlap of Mx straps

0.13

HCNP7a

[VNCAP2 touching (HCVNCAP, VNCAPHV)] must abut Mx strapes

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Description

Design

HCNP10

HCVNCAP must be an orthogonal rectangle.

HCNP11

HCVNCAP must enclose at least one VNCAP_PARM.

HCNP12

HCVNCAP must enclose at least one VNCAP_COUNT.

HCNP13

(HCVNCAP touching more than seven VNCAP_COUNT) is prohibited.

1. Mx via_finger = [Mx over VNCAP_Mx with a width equal to Rule HCN110a (for x = 1-7)]. Mx strap = [Mx over VNCAP_Mx with a
width satisfy Rule HCN199a and HCN199b (for x = 1-7)].
2. Mx vialess_finger = [Mx over VNCAP_Mx with a width equal to Rule HCN110b (for x = 1-7)]. Mx strap = [Mx over VNCAP_Mx with
a width satisfy Rule HCN199a and HCN199b (for x = 1-7)].
3. To determine if a finger is fully populated with vias, use Rules 550, HCN140, HCN155 and HCN196 for 1x vias. A via must be
present if there is enough space.
4. To determine if VNCAP_Mx is fully postulated with fingers, use Rules HCN110 and HCN120 for 1x (thin) metal levels to calculate if a
finger can fit within the VNCAP_Mx shape. A finger must be present if there is enough space.
5. This rule prevents any wiring other than VNCAP connections and jogs in wiring connections within 2 m from VNCAP_Mx.
6. For additional information, see section 3.6, Hierarchal Vertical Natural Capacitor (VNCAP) section.
7. This rule is not validated during DRC. GLOBALFOUNDRIES recommends using the HCVNCAP pcell layouts; otherwise, the
designer is responsible for drawing VNCAP, VNCAP_COUNT, VNCAP_Mx and VNCAP_PARM shapes that correctly represent the
desired capacitor, where x= 1-8.
8 . See Hierarchal Vertical Natural Capacitor (HCVNCAP) Design rules Section, table 3-51. GLOBALFOUNDRIES recommends using
the HCVNCAP pcell layouts; otherwise, the designer is responsible for drawing HCVNCAP, VNCAP_COUNT, VNCAP_Mx and
VNCAP_PARM shapes that correctly represent the desired capacitor, where x= 1-7.
9. This is for RF HCVNCAP device.

Figure 3-55. HCVNCAP connection design rule

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3.36.2 Alternative Polarity MoM Capacitor (APMOM)


The Alternative Polarity MoM Capacitor (APMOM) is constructed from metal vialess_finger capacitor (see figure
3-53a and figure 3-54a). Table 3-52 list all APMOM metal schemes for available BEOL option. Missing metal levels
are prohibited because they affect the capacitance density calculation.
Table 3-50a. APMOM Design Rules
Rule

Notes

Description

Design

APMOM1

(VNCAPHV touching VNCAP_Mx) must cover (Mx vialess_finger touching VNCAPHV),


where Mx= M4- M7.

APMOM2a

[(VNCAP_Mx over VNCAPHV) touching Mx via_finger] is prohibited, where Mx = M1- M7

APMOM3

[VNCAPHV touching (VNCAP, HCVNCAP)] is prohibited

APMOMP0

(Mx vialess finger over VNCAPHV) must not be coincident with [M(x +1) vialess finger over
VNCAPHV], where Mx = M1 - M7.

APMOMP1

VNCAPHV minimum width.

1.000

APMOMP2

VNCAPHV minimum space.

1.000

APMOMP3

VNCAPHV minimum area (m2).

4.000

APMOMP4

VNCAPHV maximum area (mm2).

0.025

APMOMP7

VNCAPHV exactly overlap Mx straps

0.13

APMOMP10

VNCAPHV must be an orthogonal rectangle.

APMOMP11

VNCAPHV must enclose at least one VNCAP_PARM.

APMOMP12

VNCAPHV must enclose at least one VNCAP_COUNT.

APMOMP13

(VNCAPHV touching more than seven VNCAP_COUNT) is prohibited.

1. See APMOM Design rules Section, table 3-51. GLOBALFOUNDRIES recommends using the APMOM pcell layouts; otherwise, the
designer is responsible for drawing VNCAPHV, VNCAP_COUNT, VNCAP_Mx and VNCAP_PARM shapes that correctly represent the
desired capacitor, where x= 1-7.

Figure 3-53a. APMOM Capacitor Cross Section

M6

M5

M4

M3

M2

M1

Vialess_finger

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Figure 3-54a. APMOM Capacitor Topview

VNCAP2
HCN121b

HCN110b

L
HCN120b

VNCAPHV

HCN199

APMOM with vialess finger

3.36.3 Using VNCAP_PARM and VNCAP_COUNT


The number of VNCAP_PARM shapes determines the metal level on which the capacitor starts as shown in Table 3-51.

Table 3-51. VNCAP Starting Level According to VNCAP_PARM


Number of VNCAP_PARM Shapes

Capacitor Starting Level

M1

M2

M3

M4

M5

M6

M7

The number of VNCAP_COUNT shapes equals the number of metal levels in the capacitor. For example, VNCAP_COUNT = 3
indicates that the capacitor is comprised of three metal levels.
When combined with the specified BEOL stack, VNCAP_PARM and VNCAP_COUNT can be used to fully specify the
capacitor. This includes recognition of the required simulation properties:
botlev
toplev

1x metal starting level


1x metal stopping level

Figure 3-56 shows one layout for a HCVNCAP comprised of five 1x metal levels. Note that VNCAP_PARM and
VNCAP_COUNT shapes can be placed anywhere within the HCVNCAP and VNCAPHV level.

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Figure 3-56. VNCAP_PARM and VNCAP_COUNT Layout Example

Table 3-52. HCVNCAP and APMOM metal scheme list for available BEOL option
Metallization
Option
5L1x_*_LB,
5L1x_*_*_LB,

6L1x_*_LB,
6L1x_*_*_LB,

HCVNCAP

APMOM

Number of
VNCAP_PARM
Shapes

Number of
VNCAP_COUNT
Shapes

Layer use for


vialess_finger*

Layer use for


via_finger

Layer use for


vialess_finger*

M1, M2, M3

M4, V4, M5

M1-M5

M2, M3

M4, V4, M5

M2-M5

M3

M4, V4, M5

M3-M5

M1, M2, M3, M4

M5, V5, M6

M1-M6

M2, M3, M4

M5, V5, M6

M2-M6

M3, M4

M5, V5, M6

M3-M6

M4

M5, V5, M6

M4-M6

M1, M2, M3,M4,M5

M6, V6, M7

M1-M7

M2, M3,M4,M5

M6, V6, M7

M2-M7

M3,M4,M5

M6, V6, M7

M3-M7

M4,M5

M6, V6, M7

M4-M7

M5

M6, V6, M7

M5-M7

7L1x_*_LB

*vialess_finger layer can start from any M1x layer, follow with subsequent layers.

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3.37 Inductor Design Rules


Inductors can be designed using a variety of metal and via levels. GLOBALFOUNDRIES recommends placing
BFMOAT underneath an inductor for Q factor improvement (Q = quality factor or ratio of inductance divided by
frequency).
Note: Metal shapes over IND do not receive standard fill during data preparation. Instead, they receive reduced
density fill for decreased substrate coupling. Reduced density RX and PC fill is silicided by default. If the silicidation
of the RX or PC fill, or any other RX or PC shape, is not desired, use SBLK to block it. For RX and PC shapes used
for shielding, silicidation is usually favored.
Table 3-53. Inductor Design Rules
Rule

Notes

Description

Design

IND00

[(M1-M7, L1-L4, BA, BB, BD, BE, BG, FA, FB) over IND] minimum width.

2.000

IND01a

(M1 over IND) maximum width.

5.000

IND01b

((M2 - M7) over IND) maximum width.

12.000

IND02

{[(M1- M7, BA, BB, BD, BE, BG, FA, FB) over IND] with width 2.000 m and < 8.2000 m}
minimum space and notch.

1.800

IND03

{[(L1-L4, BA, BB, BD, BE, BG, FA, FB) over IND] with width 8.200 m and 12.2500 m}
minimum space and notch.

2.520

IND04

[(M1- M7, L1-L4, BA, BB, BD, BE, BG, FA, FB, LB) vertex] minimum within IND.

0.000

IND05a

IND maximum width.

340

IND05b

IND minimum width.

30

IND06

IND must be an orthogonal rectangle.

IND07bR

IND must be within BFMOAT.

0.000

IND08R

Use metal bends and via bars at 45 .GLOBALFOUNDRIES recommends connecting via
bars in a vertex.

IND09a

(RX over IND) must be within JZ.

0.140

IND09b

(PC over IND) must be connected to substrate.

IND11

{[Gate and any (RX, LB) not part of IND] under or over IND} are prohibited.

IND50

(RX over IND) minimum width.

2.000

IND52

(RX over IND) minimum space and notch.

1.000

IND100

(PC over IND) minimum width.

2.000

IND102

(PC over IND) minimum space and notch.

1.000

IND594

[(V1BAR-V6BAR) over IND] must be within M1-M7.

0.100

IND595

[(V1BAR-V6BAR) over IND] must be within M2- M7.

0.100

IND694

[(WTBAR, J0BAR) over IND] must be within MLAST1X.

0.200

IND694OT

(OTBAR over IND) must be within MLAST1X.

0.200

IND695

(WTBAR over IND) must be within BA; (J0BAR over IND) must be within L1.

0.200

IND697a

[(J1BAR-J3BAR, WABAR, WBBAR, WDBAR, WEBAR) over IND] must be within L1-L3, BA,
BB, BD, BE.

0.200

IND697b

[(J1BAR-J3BAR, WABAR, WBBAR, WDBAR, WEBAR) over IND] must be within L2-L4, BB,
BD, BE, BG.

0.200

IND794GM

(GMBAR over IND) must be within BLAST2X.

0.400

IND795OT

(OTBAR over IND) must be within FA.

0.400

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Notes

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Description

Design

IND796JR

(JRBAR over IND) must be within FA.

0.400

IND797JR

(JRBAR over IND) must be within FB.

0.400

IND894

(VVBAR over IND) must be within the metal below.

1.000

IND895

[VVBAR over IND] must be within LB.

1.000

1. Non-orthogonal widths within 0.04 m of the design rule value are verified during DRC.

Figure 3-57. Inductor Design Rules

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3.38 Fuse Design Rules


This section describes design rules for the electrically programmable fuse (eFUSE). The eFUSE is constructed on
the PC level and resides in the STI region.
EFUSE Definitions:

Marking layer 200[202] is used to differentiate between Anode and Cathode of EFUSE. The side covered by
marking layer 200[202] is Anode.
- EFUSE Cathode CAREC end
- EFUSE Cathode CAREC side
- Inner EFUSE Cathode CAREC
- Outer EFUSE Cathode CAREC
- EFUSE Anode CA end
- EFUES Anode CA side
- Inner EFUSE Anode CA
- Outer EFUSE Anode CA

Edge of (CAREC touching EFUSE) that is 0.078 m long.


Edge of (CAREC touching EFUSE) that is 0.187 m long.
CAREC touching (EFUSE CAREC end that is spaced exactly 0.033 m to
PCFUSE)
CAREC touching (EFUSE CAREC end that is spaced exactly 0.073 m within
PC)
Edge of (CA touching EFUSE) perpendicular to PC that is 0.066 m long
Edge of (CA touching EFUSE) parallel to PC that is 0.066 m long
CA touching (EFUSE CA end that is spaced exactly 0.033 m to PCFUSE)
CA touching (EFUSE CA end that is spaced exactly 0.014 m within PC)

Note: The listed rules enable checking; designers must use the physical layout data available from your GLOBALFOUNDRIES
technical representative.

Table 3-54. Electrical Fuse Design Rules


Rule

Notes

Description

Design

EF01

PCFUSE exact width.

0.044

EF02

PCFUSE exact length.

0.220

EF03

PCFUSE must be an orthogonal rectangle.

EF04

PCFUSE minimum space.

0.770

EF05

PCFUSE is prohibited over (M1, CA, CAREC).

EF08

(PCFUSE over PC) must only abut (PC not PCFUSE) at both PCFUSE small ends.

EF08b

PCFUSE minimum space to [(PC touching (CA, CAREC)) not touching any PCFUSE].

0.770

EF08c

(PCFUSE sides) exact space to ((PC with width 0.044 m) not touching CA)

0.154

EF08d

(PCFUSE Anode/ Cathode sides) exact space to ((PC with width 0.044 m) not touching
CA)

0.126

EF09

[M1 not touching (PC touching PCFUSE)] minimum space to PCFUSE.

0.770

EF10a

Each EFUSE Anode must touch exactly one Inner EFUSE Anode CA and One outer EFUSE
Anode CA; and exactly 4 CAs.

EF10b

Each EFUSE cathode must touch exactly one Inner EFUSE CAREC and exactly one Outer
EFUSE CAREC shape; and exactly 2 CARECs.

EF10c_cathode

(CAREC touching EFUSE) exact width

0.078

EF10c_anode

(CA touching EFUSE) exact width.

0.066

EF10d_cathode

(CAREC touching EFUSE) exact length

0.187

EF10d_anode

(CA touching EFUSE) exact width.

0.066

EF10e_cathode

EFUSE CAREC side exact within PC

0.011

EF10e_anode

EFUSE CA side exact within PC

0.017

EF10f_cathode

EFUSE CAREC end exact space

0.110

EF10f_anode

EFUSE CA end exact space

0.093

EF10g

(PCFUSE Anode/ Cathode sides) exact within M1

0.116

EF10i

(M1 touching (PC touching PCFUSE)) must abut the PCFUSE ends

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Rule

Notes

Description

Design

EF10j

((PC touching PCFUSE) not over PCFUSE) must be within M1

0.000

EF11a

[(PC touching PCFUSE) not over PCFUSE] exact width (anode).

0.100

EF11b

[(PC touching PCFUSE) not over PCFUSE] exact length (anode).

0.590

EF12a

[(PC touching PCFUSE) not over PCFUSE] exact width (cathode).

0.100

EF12b

[(PC touching PCFUSE) not over PCFUSE] exact length (cathode).

0.590

EF16

PCFUSE must be centered at PC anode and cathode ends.

EF18

PCFUSE must be covered by PC with the PCFUSE long sides coincident with PC.

EF20

EFUSE must be orthogonal.

EF21

EFUSE minimum width.

0.440

EF22

EFUSE minimum space and notch.

0.440

EF23

EFUSE must touch PCFUSE.

EF24

PCFUSE must be within EFUSE.

0.242

EF25

(PC touching PCFUSE) must be within EFUSE.

0.242

EF26

EFUSE is prohibited over (DG, EG, NW, OP, RX, BFMOAT, BIPOLAR, DRES, HVT, NR, PR,
LVT, XW, LW, SLVT, GY, IY, NCAP, PCAP, PRES, RVT, ZVT).

EF27

EFUSE minimum space to (DG, EG, NW, OP, RX, BFMOAT, BIPOLAR, DRES, HVT, NR,
PR, LVT, XW, LW, SLVT, GY, IY, NCAP, PCAP, PRES, RVT, ZVT).

0.242

1. The design value is based on preliminary data and is subject to change.

Figure 3-58. Electrical Fuse Design Rules

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3.39 DV Passivation Opening Design Rules


Table 3-55. DV Design Rules
Rule

Notes

Description

Design

655b

DV minimum width.

15.400

657c

DV minimum notch.

3.300

657d

DV minimum space.

6.600

658ab

DV must be within CHIPEDGE

8.800

3.40 RZ Design Rules


Table 3-56. RZ Design Rules
Rule

Notes

Description

Design

Mx maximum density (%) with 50.0000 um tiling under ((DV, RZ) wire-bond pad sized by 1.98
um), where x=1-6.
Bx maximum density (%) with 50.0000 um tiling under ((DV, RZ) wire-bond pad sized by 1.98
um), where x=1-4.

80

80

961aR

961bR

966R

[(BA, BB, BD) over ((DV,RZ) wire-bond pad sized by 1.98 um)] minimum space and notch..

RZ00

(CHIPEDGE touching RZ) touching DV is prohibited.

RZ655b

RZ minimum width

15.400

RZ657b

RZ minimum space

6.600

RZ657c

RZ minimum notch

3.300

RZ658ab

RZ must be within CHIPEDGE.

8.800

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3.41 Flip Chip Terminal Design Rules


GLOBALFOUNDRIES offers multiple flip chip metallurgies and processes; contact your GLOBALFOUNDRIES
technical representative to determine which type best fits your application.

3.41.1 Mask Sequence and Alignment


References to the LM level refer to the last 2x or 4x thick metal wiring level, respectively.
Table 3-57. Design Mask Levels
Mask Level1

Shape Description

Aligns to

VV

Opening in the oxide/nitride passivation above the last copper metal level. Required for flip
chip terminals, probe pads, and so forth.

LM

LV

Opening in the final polyimide passivation and nitride/oxide underneath. Required over flip
chip terminals and probe pads.

LB

LB

AlCu transfer pad and wiring level above last copper wiring level to the final passivation opening for flip chip -style terminal connections.

VV

1. Some design levels are also manipulated during mask data preparation (DPREP). Refer to the 40nm-LP Data Preparation Manual
for more information.

Table 3-58. Nondesign Mask Levels


Mask Level1

Shape Description

Aligns to

TM

Plated terminal metal area.

LB

EM

Mold transfer (FCNP) sputtered ball-limiting metallurgy (BLM) area.

LB

CM

Mold transfer (FCNP) terminal metal area.

EM

1. Some design levels are also manipulated during mask data preparation (DPREP). Refer to the 40nm-LP Data Preparation Manual
for more information.

Table 3-59. Shape Manipulation Performed Prior to Writing the Mask


Mask
LV

Design Preparation from Design Levels


LV octagons converted to circles: size LV circle by -0.74 m.

TM1

Generated from (LV, LVDUMMY).

EM

Generated from LV.

CM

Generated from LV.

1. flip chip -plating mask process.

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3.41.2 Active Flip Chip Terminals


The flip chip structure is a lead/tin ball over a transition metallurgy pad. This section describes the design rules
required for connecting a flip chip terminal to the chip circuitry (an active Flip Chip). Section 3.41.4 describes how
dummy terminals are used.
An active flip chip terminal makes contact with the final copper metal level (LM) through the LV via, the LB transfer
pad and wiring level, and the VV via in the final passivation layer (polyimide, nitride/ oxide, AlCu, or oxide). This
structure is shown in Figure 3-59.

Figure 3-59. Active Flip Chip Terminal Structure

The guidelines below must be followed when designing a flip chip pattern:
1. The outer row of pads must be asymmetrical on all four sides of the chip.
2. The asymmetrical pad design is required within 2.34 mm of the true chip center for all chips larger than 10 mm
on a side in one or both dimensions. The preferred pattern of asymmetry is three adjacent depopulated flip chip
sites surrounded by an area of fully populated sites. The three depopulated sites should not be in the same row
or the same column.
3. For standard flip chip flip-chip packages, the LV terminal to CHIPEDGE distance must be less than or equal
to 500 m on at least three sides of the chip for some flip chips. Use dummy flip chip pads to achieve this
requirement.
4. The outer row of pads should be approximately the same distance from the edge of the chip on all sides.
5. Circular patterns of flip chip pads are prohibited.
6. The flip chip structure is prohibited outside of CHIPEDGE.
7. Flip chip terminals connected to the last wiring must not float. The metal must be connected to RX and satisfy
the ESD rules in Section 3.28 (see Rule 918 in Table 3-60). Floating flip chip terminals that use the LVDUMMY
level are permitted.
8. All designs with more than 5000 tested pins must obtain approval from Test Probe Engineering before design
submission.
In addition, the following guidelines are recommended:
1. Unpopulated or sparse flip chip patterns should be avoided. Use dummy to make the flip chip pattern more
uniform.
2. Using a 5 on 10 flip chip size/pitch or fewer than the maximum permissible number of flip chip terminals per
chip typically improves manufacturing yields. The 5 on 10 flip chip syntax refers to a 5 mil solder ball on a 10
mil pitch (1 mil = 25.4 m).
3. For designers who plan to characterize their designs prior to flip chip processing by probing last metal pads,
the following recommendation should be observed to prevent probe damage to adjacent wiring: LB pad to LB
wiring should be greater than 60 m.
Note: The flip chip terminal design must be reviewed with packaging and test groups. flip chip terminal designs
with on-chip pitches of less than 230 m must be reviewed with probe engineering. Deviations from the guidelines
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presented above or from the design rules in Table 3-60 must be approved by GLOBALFOUNDRIES terminal
metals engineering. Contact your GLOBALFOUNDRIES technical representative to obtain the necessary reviews
and approvals.
In Table 3-60, the maximum number of flip chip terminals per chip is 9000; the minimum number of flip chip
terminals per chip is 3.
Table 3-60. Flip Chip Terminal (Active and Dummy) Design Rules
Flip Chip Solder Ball Diameter and Pitch
Rule

Notes

Description

910

(LV, LVDUMMY) octagon dimension D (see


Figure 3-60).

911

911a

3 on 61
Design

4 on 8
Design

4 on 9
Design

5 on 10
Design

51.700

51.700

51.700

51.700

(LV, LVDUMMY) center to LV center.

165.000

220.000

247.500

275.000

LVDUMMY must not touch LV.

912

LV minimum within LB.

18.15000

14.300

14.300

14.300

913

VV minimum space to LV.

4.950

8.800

8.800

8.800

915a

LV minimum space to {union [(LV, LVDUMMY)


center, flip chip]}.

115.500

120.450

120.450

140.250

916

(LV, LVDUMMY) center within CHIPEDGE.

115.500

120.450

120.450

140.250

917

(LV, LVDUMMY) center to chip product label.

82.550

95.150

95.150

112.750

918

(LV touching LB) must be tied to RX.

1. Bond, assembly, and test restrictions apply, and prior approval from packaging manufacturing engineering and must be obtained before using
this pitch.
2. The octagon dimensions required for LV and LVDUMMY shapes are given in Figure 3-60. Octagon dimensions have a 0.10-m tolerance
associated with these shapes.
3. This rule does not apply to LVDUMMY designs.
4. The minimum distance between the flip chip center and the diced chip edge is a critical parameter for certain package flip-chip plastic ball grid
array packages. For specific applications, this minimum distance must be reviewed for reliability restrictions.
5. This rule prevents flip chip terminals from obscuring the chip identification information. Chip designs containing multiple the part number do
not need to comply with Rule 917 at every occurrence.
6. The metal must be connected to RX and must satisfy the ESD rules in Section 3.28.

Figure 3-60. Octagon Dimensions for LV and LVDUMMY Shapes (Need to update below table)

51.70
21.43
15.13

Note: When using either high- or low-temperature plated flip chip bumps, order a mask size 1 mil smaller than the
required flip chip bump diameter. For example, order a 4-mil mask for a 5 mil plated flip chip bump. Plated flip chip
bumps are typically 1 mil larger once they are built.

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Figure 3-61. Flip Chip Terminal Design Rules

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Logo and Part
Number

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3.41.3 LB and LV Pad Design


Table 3-61. Flip Chip Terminal LB or LV Pad Design Rules
Flip Chip Solder Ball Diameter and Pitch
Rule

Notes

Description

916a

(LV center) minimum within CHIPEDGE


(applicable to FCPBGA packages only).

166.100

916b

(LV center) minimum space to PROTECT


(applicable to FCPBGA packages only).

471.900

919

Wiring from LB landing pad if maximum current


specification is 123 mA when C + D + E + F
75.6 m (see Figure 3-62).

920

Wiring from LB landing pad if maximum current


specification is 123200 mA when C + D + E + F
122.7 m (see Figure 3-62).

3 on 6
Design

4 on 8
Design

4 on 9
Design

5 on 10
Design

1. Waiver requests for flip-chip plastic ball grid array (FCPBGA) packages that cannot meet this rule must be approved by
GLOBALFOUNDRIES.
Contact your GLOBALFOUNDRIES technical representative to obtain the necessary approvals.
2. This rule can be waived for redundant power flip chip s and applications that do not require reliability greater than 5000 power on/off cycles.
Other waiver requests for FCPBGA packages that cannot meet this rule must be approved by GLOBALFOUNDRIES.
Contact your GLOBALFOUNDRIES technical representative to obtain the necessary approvals.

Figure 3-62. Flip Chip Terminal LB or LV Pad Design

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3.41.4 Dummy Flip Chip Terminals


Dummy flip chip terminals are electrically inactive. They are used to provide additional mechanical support or to
enable use of the same flip chip masks for multiple part numbers. Flip chip dummy terminals are designed by using
the LVDUMMY dummy level instead of LV so that there is no VV or LV opening in the nitride passivation (see
Figure 3-63). LVDUMMY shapes are permitted over LB or VV, but they must adhere to Rules 910, 911, 911a, 916,
and 917 for proper placement.

Figure 3-63. Dummy Flip ChipTerminal Structure

3.41.5 Reliability Design Rules


Electromigration is analyzed by dividing interconnect networks into simplified elements: metal lines of a given
width, contacts and vias that serve as interlevel connections to lines, and flip chip solder balls that connect the chip
to the package. The designer must follow the electromigration rules for all these design elements. See Section 6
Reliability Design Rules and Models for more information.

3.41.5.1 Exceptions
This section describes exceptions to the general rules at 110C and 100 000 power-on hours (see Section 6
Reliability Design Rules and Models).
Flip chip terminal pad types are defined as follows:
Positive FC pad
(VDD pad)

Negative FC pad
(Ground pad)

flip chip pad at a higher voltage potential than the chip metallization with electron
current flowing from the chip to the package.
flip chip pad at a lower voltage potential than the chip metallization with electron
current flowing from the package to the chip.

Table 3-62. Design Rules for Flip Chip Terminals at 110C for Ceramic Packages
Design Size (LV Diameter)

Flip Chip Pad Size

Line into Flip Chip


Pad

Line Width into Flip Chip Pad


(Design) 1

Maximum Idc per Flip Chip


(mA)

51.7 m

80.3

LB

W 134.97 m

200

1. If the metal line fed into the flip chip pad is less than the width specified in this table, then use Section 6 Reliability Design Rules and Models
to determine the maximum permissible current for the metal line. The upper bound of 200 mA per flip chip applies to all flip chip terminal pad
types (positive, negative, and signal). For signal pads, the metal line Irms will be the limiter.

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Figure 3-64. Flip Chip LB Level

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3.42 Wire-Bond Terminal Design Rules


40nm-LP supports three types of wire-bond pads:
A basic inline wire-bond pad
A longer version of the basic wire-bond pad with a separate probe area but at the same pitch as the basic pad
A staggered version of the basic wire-bond pads for efficient spacing of a larger number of wire-bond pads
These three types of wire-bond pads are very similar and share a common set of design rules.
Note: Copper line and via support (CLVS) structures are prohibited in TEOS/FTEOS levels.
Table 3-63. Common Wire-Bond Pad Design Rules
Rule

Notes

Description

Design

940

(DV, RZ) minimum within PROBE; PROBE must not straddle (DV, RZ) passivation opening.

0.000

942c

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum space to VV.

1.870

945c

(DV, RZ) wire-bond pad maximum within CHIPEDGE.

220

951

IND is prohibited under (DV, RZ) wire-bond pad.

953

[LB touching ((DV, RZ) wire-bond pad, (DV, RZ) probe pad)] must be connected to RX;
floating pads are prohibited.

WB08

{(DV, RZ) wire-bond pad, (DV, RZ) Probe Pad} must be within LB.

2.200

WB09

[((DV, RZ) wire-bond pad, (DV, RZ) probe pad) not over crackstop ring] must be an orthogonal
rectangle.

1. Maximum value to prevent excessively long bond wires.


2. The metal must be connected to RX and satisfy the ESD design rules.

Figure 3-65. DV Wire-Bond Pad Design Rules

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3.42.1 Inline Wire-Bond Pads


This section describes the basic inline wire-bond pad. The dimensions of the pad opening are intended for bonding
and probing. See Table 3-1 Design Rule Checking Abbreviations for the definitions of DV wire-bond pad and DV
probe pad.
Table 3-64. Inline Wire-Bond Pad Design Rules
Rule

Notes

Description

Design

941c

(DV, RZ) wire-bond pad minimum distance, center to center.

44.000

946ca

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum width parallel to the closest
CHIPEDGE.

37.400

946cb

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum length perpendicular to the closest
CHIPEDGE with bonding and probing permitted.

82.500

Figure 3-66. Inline Wire-Bond Pad Design Rules

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3.42.2 Inline Dual Wire-Bond/Probe Pads


Dual wire-bond/probe pads separate the bond area from the probe area. Because the wire-bond area is not used
for probing, the size of the opening can be smaller compared to the inline wire-bond pad. CLVS structures are not
required below the probe pad.
In addition to the design rules below, the common wire-bond pad design rules in Table 3-63 must be observed. See
Table 3-1 Design Rule Checking Abbreviations for the definitions of DV wire-bond pad and DV probe pad.
Table 3-65. Inline Dual Wire-Bond/Probe Pad Design Rules
Rule

Notes

Description

Design

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum distance, center to center.

44.000

D946ca

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum width parallel to the closest
CHIPEDGE.

37.400

D946cb

(DV, RZ) wire-bond pad minimum length perpendicular to the closest CHIPEDGE.

37.400

D946cc

(DV, RZ) probe pad minimum length perpendicular to the closest CHIPEDGE.

77.000

D941c

1. (DV, RZ) should be sized by sized by -3.5 m, then by +5 m, then by -1.5 m prior to checking this ground rule.

Figure 3-67. Inline Dual Wire-Bond/Probe Pad Design Rules

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3.42.3 Staggered Wire-Bond Pads


The staggered wire-bond pad configuration adds an additional row of pads toward the inside of the chip. This
configuration is useful in reducing the total chip area in pad-limited designs. The outer row of pads is identical to the
inline wire-bond pads and follows the design rules in Table 3-66. These pads can be used for bonding and probing.
These same design rules apply to the inner row of pads when probing is requested. If bonding is sufficient, the pad
opening can be reduced according to Rules 946ca and S946cb.
In addition to the design rules below, the common wire-bond pad design rules in Table 3-63 must also be observed.
See Table 3-1 Design Rule Checking Abbreviations for the definitions of DV wire-bond pad and DVprobe pad.
Table 3-66. Staggered Wire-Bond Pad Design Rules 25 m Pitch
Rule

Notes

Effective Pitch
27.5 m

Description

S941c

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum distance, center to center.

55.000

S946ca

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum width parallel to the closest
CHIPEDGE.

48.400

S946cb

(DV, RZ) probe pad minimum length perpendicular to the closest CHIPEDGE (inner row of
staggered pads).

82.500

S946cc

(DV, RZ) wire-bond pad minimum length perpendicular to the closest CHIPEDGE with
probing prohibited (inner row of staggered pads).

48.400

S946cd

(DV, RZ) pad minimum length perpendicular to the closest CHIPEDGE (outer row of
staggered pads).

82.500

S955c

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum space and notch; dimension is
perpendicular to the closest CHIPEDGE.

17.600

Table 3-67. Staggered Wire-Bond Pad Design Rules 30 m Pitch


Rule

Notes

Effective Pitch
33 m

Description

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum distance, center to center.

66.000

S946ca

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum width parallel to the closest
CHIPEDGE.

59.400

S946cb

(DV, RZ) probe pad minimum length perpendicular to the closest CHIPEDGE (inner row of
staggered pads).

82.500

S946cc

(DV, RZ) wire-bond pad minimum length perpendicular to the closest CHIPEDGE with
probing prohibited (inner row of staggered pads).

59.400

S946cd

(DV, RZ) pad minimum length perpendicular to the closest CHIPEDGE (outer row of
staggered pads).

82.500

S955c

((DV, RZ) wire-bond pad, (DV, RZ) probe pad) minimum space and notch; dimension is
perpendicular to the closest CHIPEDGE.

17.600

S941c

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Figure 3-68. Staggered Wire-Bond Pad Design Rules

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3.42.4 Testing and Packaging Restrictions


For GLOBALFOUNDRIES-tested wire-bond parts, note the following testing and packaging guidelines:
1. The largest possible pad size and opening should be used for manufacturing robustness.
2. Pad designs and the associated test approach must be approved by your GLOBALFOUNDRIES technical
representative.
3. On chips with staggered wire-bond pads:
a.
Wafer-level testing is limited to the outer row of pads unless prior arrangements are made with the
applicable test group.
b.
Power and ground pads are prohibited on the inner row.
4. Testing is performed at 4085C unless prior arrangements are made with the applicable test group.
5. Corner rules:
a.
Inline pads. At the four corner areas, the first bond pad must be placed away from the mechanical
and thermal stress-concentrated die edges. Unique patterns must be placed there for eye-point
recognition. Starting from the corners, the first four pitches must be wider than the pitch in the
regularly repeating bond pad center area. See Figure 3-69 for design dimensions. All pads must
be located geometrically or symmetrically toward the direction of the internal leads.
b.
Staggered pads. See Figure 3-70 for layout and design dimensions.
6. If inner rows are used for probing, these rows must be 93.5 m x 48.4 m
Figure 3-69. Inline Corner PAD Design Rules

Figure 3-70. Staggered Corner PAD Design Rules

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3.42.5 LB Wide Metal Slot Guidelines


Chips packaged in plastic flat packs are subject to chip/plastic thermal mismatch stress that can result in dielectric
cracking and metal movement around the chip periphery. Many factors, such as module build process, chip size,
chip film thicknesses and composition, topology, and metal layout, contribute to chip susceptibility. To reduce chip
susceptibility, GLOBALFOUNDRIES strongly recommends following the slot and corner chamfer guidelines below
for chips that will be packaged in plastic flat packs:
1. Approximate the portion of the chip where slots in the metal can provide stress relief by placing a 10 mm
10 mm dummy box in the center of the chip. Place slots in the wide metal lines (that is, line width 44 m,
with the exception of wire-bond pads) outside the box. GLOBALFOUNDRIES recommends 3.3 m (W)
33 m (L) slots.
2. Place slots so that the maximum width of the last metal (outside of the 10 mm 10 mm box) is less than 44
m wide.
3. If the lines are very wide, space the slots 1040 m apart lengthwise. End-to-end spacing between slots
should be at least 3.3 m. For long, wide metal, stagger the starting position of the slots for best results.
4. To prevent electromigration problems from current funneling, position the slot length parallel to the current
flow. Avoid geometries that funnel currents and lead to electromigration problems.
5. In the areas of the chip with metal slots, place chamfered corners on the right-angled bends of wide LB
lines. GLOBALFOUNDRIES recommends an inside edge of at least 16.5 m for chamfered corners.
6. Avoiding using LB in the chip corners except with wire-bond pads or the chip guard ring. Chip corners are
defined as the four triangular corner regions with a length of 440 m along the chip edge.

Figure 3-71. LB Wide Metal Slot Guidelines

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3.43 Chip Guard Ring Design Rules


The chip guard ring provides both a low resistance path to ground for surge currents and a metal seal against ionic
contaminants. GUARDRNG is the marking level that must be drawn by over guard ring structures to support metal
hole generation.
In addition to the design rules presented in Table 3-68, the guidelines below must be followed when designing a
chip guard ring:
1. The chip guard ring must be a complete unbroken ring around the entire chip area. The chip guard ring
must be connected to the ground bus.
2. The chip guard ring must be comprised of the following levels: RX, JZ, CABAR, M1, V1BAR, and all
remaining metal and VxBAR levels (depending on the selected BEOL metallization option) up to the last
copper metal (LM). Continuous xxBAR vias and contacts must be used in the guard ring structure. See
Figure 3-72 Chip Guard Ring Example Cross Section.
3. The guard ring must not have any vertices except for the 45 angles that occur at the corner bevels.
4. The prohibition against 45 xxBAR shapes does not apply to the chip guard ring at the corner bevels. The
measured width of the 45 xxBAR shapes on the corner bevels might not match the specified dimensions
exactly due to grid snapping ( grid 2 tolerance). This tolerance also applies to the within design rules.
5. The xxBAR length restriction does not apply to the chip guard ring.
6. The chamfer region is required for all chips for process robustness. A chamfer or corner bevel of exactly
74.000m is required to be cut from each corner of the chip. The chamfer area is triangular and has an
area of exactly half of a 74.000m 74.000m square. The chip guard ring does not enclose the chamfer
area. The chip guard ring has 45 edges at the corners of the active chip area.
In addition, GLOBALFOUNDRIES recommends the following guideline:
1. The chip guard ring should be comprised of four cells (top, bottom, left, and right) placed on the primary cell.
This structure eases hierarchical data manipulation for design rule checking and design preparation
Table 3-68. Chip Guard Ring and PROTECT Design Rules
Rule

Note

Description

Design

990a

(CABAR touching GUARDRNG) must be within M1 and RX.

1.727

990f

(VxBAR touching GUARDRNG) must be within Mx, where x = 1-6.

1.722

990g

(VxBAR touching GUARDRNG) must be within M(x+1), where x = 1-6.

1.722

990h

[(W0BAR, WTBAR, L0BAR) touching GUARDRNG] must be within MLAST1X.

1.683

990hOT

(OTBAR touching GUARDRNG) must be within MLAST1X.

1.562

990i

[(J1BAR-J3BAR) touching GRARDRND] must be within L1-L4; (WABAR touching


GUARDRNG) must be within BA; (WBBAR touching GUARDRNG) must be within BB;
(WDBAR touching GUARDRNG) must be within BD; (WEBAR touching GUARDRNG) must
be within BE (BxBAR must be within the metal below).

1.683

990IGM

(GMBAR touching GUARDRNG) must be within FA

1.562

990IOT

(OTBAR touching GUARDRNG) must be within FA.

1.562

990j

[(J0BAR-J3BAR) touching GUARDRNG] must be within L1-L4; (WTBAR touching


GUARDRNG) must be within BA; (WABAR touching GUARDRNG) must be within BB;
(WBBAR touching GUARDRNG) must be within BD; (WDBAR touching GUARDRNG) must
be within BE; (WEBAR touching GUARDRNG) must be within BG (BxBAR must be within the
metal above).

1.683

990kGM

(GMBAR touching GUARDRNG) must be within (BLAST2X or LLAST2X).

1.562

990nn

(JRBAR touching GUARDRNG) must be within FA (JRBAR within metal below).

1.540

990oo

(JRBAR touching GUARDRNG) must be within FB (JRBAR within metal above).

1.540

991

(RX over GUARDRNG) must be within JZ.

0.121

992

WxBAR (x = 0-3, T, A, B, D, or E), JxBAR (x = 0-3), OTBAR, GMBAR, JRBAR, and


GUARDRNG must completely cover CABAR within the chip guard ring design.

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Description

Design

992a

VxBAR (x = 1-6) must be completely covered by CABAR within the chip guard ring design.

999

(RX, M1-M7, L1-L4, BA, BB, BD, BE, BG, FA, FB) over GUARDRNG within CHIPEDGE
(exact value).

0.000

999a

All active chip design shapes except JZ; (see Rule 999b) must be within CHIPEDGE.

0.000

999b

(JZ touch GUARDRNG) within CHIPEDGE (exact value).

-0.121

999c

GUARDRNG must be covered by CABAR sized by 1.790 m.

0.000

999d

(CA, square via shapes, IND) is prohibited touching GUARDRNG.

999s

The chip guard ring must be a complete, unbroken ring around the entire chip area and be
comprised of the following levels: RX, JZ, CABAR, M1, and V1BAR. If they are present in the
data, levels M2-M7, V2BAR- V6BAR, J0BAR-J3BAR, WTBAR, WABAR, WBBAR, WDBAR,
WEBAR, L1- L4, BA, BB, BD, BE, BG, GMBAR, OTBAR, JRBAR, FA, FB) must also be
included.

999zz

The lower left coordinate of the least enclosing rectangle of CHIPEDGE must be at (0, 0).

PT01

Four triangles on the PROTECT level must be added in the chamfer region for proper mask
merge. The four triangles are defined by the least-enclosing rectangle of CHIPEDGE minus
the CHIPEDGE design level.

PT01a

PROTECT must be an orthogonal 45-deg. triangle.

PT01b

There should be four PROTECT shapes for every CHIPEDGE shape.

PT01c

Union (CHIPEDGE, PROTECT) must be a single orthogonal rectangle.

PT01d

Each PROTECT shape must have one 45-deg. edge in common with CHIPEDGE.

PT01e

Orthogonal PROTECT edge exact length.

74.000

PT01f

PROTECT should not be checked against Rule S2 for acute angles.

PT01g

PROTECT shapes should not intersect nor be covered by CHIPEDGE

PT01h

Design levels, except JZ, are prohibited within PROTECT.

PT999a

CHIPEDGE must be chamfered. The horizontal and vertical components of the chamfer must
be exactly 74.000m

74.000

1. VxBAR must be within the metal below.


2. VxBAR must be within the metal above.
3.Pending crackstop qualification data

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Figure 3-72. Chip Guard Ring Example Cross Section

Chip guard-ring width

Figure 3-73. CHIPEDGE Chamfer Requirement

74.000um

74.000 um

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3.44 Permissible Chip Size Design Rules


Permissible chip (CHIPEDGE) sizes are limited to the following:
1. The two design rules for CHIPEDGE x and y dimensions must be followed.
2. For the minimum productivity kerf, there are two maximum chip sizes:
Maximum chip x = 32.00 mm, the maximum y with this chip is 23.98 mm
Maximum chip y = 25.80 mm, the maximum x with this chip is 30.83 mm
3. The chip size in the x and y directions must be no finer than 0.002 m.
Table 3-69. CHIPEDGE Design Rules
Rule

Description

Design

CE001

CHIPEDGE x and y dimensions must be an even number of grid points (that is, a multiple of (2 0.001).
Checked as (x or y dimension / (2 grid) = whole number).

CE002

CHIPEDGE x and y dimensions must be a multiple of 0.002 m.

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3.45 Mask Process Control Image Design Rules


Process control images (PCIs) are used in GLOBALFOUNDRIES mask processing to control image size and
registration for all mask levels. For critical levels, such as RX, PC, CA, M1, Vx, Wx and Bx, Jx, Lx, PCI marks are
required. For levels M2M6 and V1V5, GLOBALFOUNDRIES strongly recommends that special PCI
measurement structures be distributed inside the chip in addition to those that are automatically placed outside the
chip during kerf assembly. To ensure an optimum distribution of PCI marks, GLOBALFOUNDRIES strongly
recommends placing PCI target cells throughout the design on the critical mask levels noted above according to
the design rules in Table 3-70.
A typical 10 mm 10 mm chip requires approximately 25 PCI marks on each critical level. PCI marks can be placed
anywhere in the design hierarchy. They can be stacked, but stacking is not required. During data preparation, the
content of the each TGPCIxx cell is automatically replaced by a swap file containing the optimized PCIs.
Table 3-70. xxING Design Rules for PCI Target Cells
Rule

Notes

Description

Design

781a

Each PCI mark must be comprised of a single data cell named TGPCIxx (all uppercase). Each
TGPCIxx data cell must contain only a single square shape on the xxING design level (where
xx = Rx, PC, CA, M1M7, V1 V6, W0W3, B1B4, J0 J3, L1 L4, WT, WA, WB, WD, WE,
BA, BB, BD, BE, BG), with the origin of the data cell coincident with the exact center of the
square.

781b

The sequence of characters PCI (all uppercase) cannot appear in any data cell in the design
except those specifically required by Rule 781a.

782a

xxING exact length and width, where xx = RX, PC, CA, M1 M7, V1 V6, W0W3, B1B4, J0
J3, L1 L4, WT, WA, WB, WD, WE, BA, BB, BD, BE, BG.

7.200

783

xxING minimum space to xxING, where xx = RX, PC, CA, M1 M7, V1 V6, W0W3, B1B4,
J0 J3, L1 L4, WT, WA, WB, WD, WE, BA, BB, BD, BE, BG. (xxING touching xxING is
prohibited. For example, RXING touching RXING is prohibited, while RXING touching PCING
is permitted.)

97.130

784

xxING minimum space to xx, where xx = RX, PC, CA, M1 M7, V1 V6, W0W3, B1B4, J0
J3, L1 L4, WT, WA, WB, WD, WE, BA, BB, BD, BE, BG. (xxING touching xx is prohibited.
For example, M1ING touching M1 is prohibited, while M1ING touching M2 is permitted.)

0.730

785

RXING minimum space to (PC, CA) with RXING touching (PC, CA) prohibited; PCING
minimum space to (RX, CA) with PCING touching (RX, CA) prohibited; CAING minimum
space to (RX, PC and M1) with CAING touching (RX, PC and M1) prohibited.

0.730

786

xxING minimum space to (Mx, My), where xxING touching (Mx, My) is prohibited; where
xx=all 1x or 2x via levels (V1 V6, W0 W3, J0 J3, WT, WA, WB, WD, or WE), Mx = metal
level below xx, and My = metal level above xx.

0.320

787

All xxING shapes must be either coincident with MxING and MyING or spaced away by rule
784, where xx = all 1x or 2x via levels (V1- V6, W0-W3, J0 J3, WT, WA, WB, WD or WE), Mx
= metal level below xx, and My = metal level above xx.

(xxING expanded by +1 mm/edge) should cover the entire chip, where xx = Rx, PC, CA, M1
M7, V1V6, W0W3, B1B4, J0 J3, L1 L4, WT, WA, WB, WD, WE, BA, BB, BD, BE, or
BG. Note: This rule applies to each xxING level and helps ensure an even distribution of PCIs
across the chip.

788

1. This rule applies to each xxING level and helps ensure an even distribution of PCIs across the chip.

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3.46 Reserved Level Checking Design Rules


The design rules presented in Table 3-71 correspond to the reserved levels described in Table 2-3 Design Levels,
Utility Levels, and GDS Stream Layers on 40nm-LP and Table 2-5 Kerf Design Levels on 40nm-LP.
Table 3-71. Reserved Level Checking Design Rules
Rule

Description

Design

RL02

xxFILL is prohibited, where xx = V1-V6, W0-W3, or J0-J3

RL03

WxEXCLUD is prohibited, where Wx = W0-W3

RL04

MxCHEXCL touching CHIPEDGE is prohibited, where Mx = M1-M7, B1-B4, L1-L4, BA, BB, BD, BE, BG,
EA, EB, FA, FB, UA, UB.

RL05

xxHOLE is prohibited, where xx = M1- M7, B1-B4, L1-L4, BA, BB, BD, BE, BG, EA, EB, V1- V6, W0-W3,
WT, WA, WB, WD, WE, YT, YA, OT, GM, JR, FA, FB, HL, LT, UA, UB, GA.

RL06

MxPLANE is prohibited, where Mx = M1- M7, B1-B4, L1-L4, BA, BB, BD, BE, BG, EA, EB, FA, FB, UA,
UB.

RL07

(FRAME, KERFEXCL, NEGMKS, POSMKS) is prohibited.

RL08

(DIR, DNIRxx, NIXxx, NONIAGxx, SRAMxx, xxANCHOR, xxCUS, xx NOTCH, xxOPC, xxOPCHOLE) is
prohibited, where xx = any combination of alphanumeric characters.

3.47 Product Label Design


Product labels are placed in the chip outside the scribe line area, and are comprised of:
Chip legal protection notices
- copyright symbol and year
- company logo
- mask work notice
Chip identification
- part number
- release version or EC number
Mask Level Identification
- mask level names and versions

3.47.1 General Requirements


1. Place the product labels in one or more corners of the chip, preferably in the lower-left corner.
2. Surround the entire group of product labels with a substrate contact ring. Functional chip structures are
prohibited within this region.
3. Cover the entire product label area with the LOGOBND dummy level to suppress spurious DRC
errors. Note that only product labels are permitted under LOGOBND.
4. Confirm that shapes within the LOGOBND area abide by all line, space, and area rules for the level
on which they are designed.
5. Alphanumeric polygon definitions:

Obtain a 40nm-LP design kit from your GLOBALFOUNDRIES technical representative. The design kit
contains the correct character set.
If the GLOBALFOUNDRIES-provided character set is not used, compose characters from polygons that
followhe design rules for line widths, spacings, orthogonal and 45 shapes, enclosed shapes, shape areas,
and so forth, and that meet the expanded spacing rules in Table 3-72.
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6. Place characters only on the PC and M1 design levels. Characters placed on other levels will not be verified
during DRC.
Table 3-72 provides additional spacing rules for LOGOBND areas.
Table 3-72. Special LOGOBND Design Rules
Rule

Notes

Description

Design

PN1a

LOGOBND must be within CHIPEDGE.

PN1b

LOGOBND must be within CHIPEDGE.

PN2a

At least one LOGOBND must touch both (PC and M1).

PN2b

NW, T3, ED, DG, JX, JZ, OP, SLVT, GY, IY, LVT, XW, LW, HVT, NR, PR, V1BAR-V5BAR,WTBAR,
WABAR, J0BAR-J3BAR, WBBAR, WDBAR, WEBAR, OTBAR, GMBAR,JRBAR, VV, DV touching
LOGOBND is prohibited.

PN3

[(RX, PC, CA, M1-M6, V1-V5, L1-L4, BA, BB, BD,BE, BG, J0-J3, WT, WA, WB, WD,WE, OT, GM,
FA, FB, JR and LB) touching LOGOBND] must be within LOGOBND.

0.8

PN4a

For each design level [(RX, PC, M1-M6, L1-L4, BA, BB, BD, BE, BG, FA, FB and LB) touching
LOGBND], the only primary rules checked are minimum width, minimum space and notch,
minimum area, and minimum enclosed area.

PN4b

[(CA, V1-V5, J0-J3, WT, WA, WB, WB, WD, WE, OT, GM, JR) touching LOGOBND] the only
primary rules checked are exact width and length and minimum space.

PN5

[RX, PC, CA, M1-M6, V1- V5, L1-L4, BA, BB, BD, BE, BG, J0-J3, WT, WA, WB, WD, WE, OT, GM,
FA, FB, JR and LB) touching LOGOBND] must be polygons or rectangles.

1. Alpha opcodes are prohibited on design levels.

Figure 3-74. Product Label Placement Example

2011 GLOBALFOUNDRIES M

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3.47.2 Chip Protection Notices


The copyright notice, company logos, and mask work notice (*M*), are legal notices that protect
proprietary designs and certain chip features. All product designs should contain both the company
logo and the mask work notice. Product designs that contain significant designs or have a high copy risk
should also include the copyright notice for additional protection.
Chip protection notices must be placed on the first metal level (M1) only.
An example of a combined mask work and copyright notice is shown in Figure 3-75. Note that the font
shown has enclosed shapes that might be below the minimum character size. A design character
generator can produce shapes without these enclosed areas.
Figure 3-75. Combined Mask Work and Copyright Notice

2010 GLOBALFOUNDRIES *M*


3.47.3 Chip Identificaton
The GLOBALFOUNDRIES-assigned chip part number is required on the PC and M1 levels of each chip.
The GLOBALFOUNDRIES part number is required whether the design is a test site, prototype, or
production part. If the release to manufacturing (RTM) A/B approach is being used, where the FEOL
(silicon) and BEOL (wiring level) designs have different part numbers, then the RTM A part number must
appear on PC and the RTM B part number must appear on M1. GLOBALFOUNDRIES part numbers can
be obtained from your GLOBALFOUNDRIES technical representative prior to design submission.

Exceptions to the GLOBALFOUNDRIES part number requirement are as follows:


Products for which the deliverables are untested wafers do not require an GLOBALFOUNDRIES part number.
If a customer supplies a merged data set that contains several chips or tiles, as in a multiproject
wafer (MPW) or an array of chip variants for design optimization, then the
GLOBALFOUNDRIES-assigned part number must only appear once in the data set. Place the part
number in one of the corners of the data set as described in Section 3.42.1 General Requirements
on page 171. A customer-determined unique identifier is required on each individual chip or tile if
GLOBALFOUNDRIES performs the dicing or testing; otherwise, identification by tile and chip is
recommended.
If a product part number is changed for any reason, a waiver is not required. Your
GLOBALFOUNDRIES technical representative must submit an engineering change (EC) number
request and maintain a change log for trace-ability.
Customer part numbers and identifiers can be placed on a chip in addition to the GLOBALFOUNDRIES part
number.

3.47.4 Mask Level Identification


Mask level identification is prohibited on all front-end-of-line (FEOL) levels except RX and PC
due to the shapes propagating to derived levels.

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3.48 RX, PC, Metal Dummy Fill Design Rules


GLOBALFOUNDRIES Product Engineering performs Design Services as a standard part of the 40nm-LP tape-out.
RXFILL, PCFILL, MxFILL will be generated during design services. However, GLOBALFOUNDRIES also allow
customers use their own dummification (RXFILL, PCFILL and MxFILL) for RX, PC and Mx respectively. The
customized dummies should refer to Table 3-73 design rules.
Table 3-73. RXFILL, PCFILL Design Rules
Rule

Notes

Description

Design

RXFILL100

RXFILL must not touch (LOGOBND, PC, PCFUSE, PROTECT, RX, RXING).

RXFILL101

RXFILL minimum space to (RX, RXING)

0.64

RXFILL102

RXFILL minimum space to (LOGOBND, PC, PROTECT, RXEXCLUD). RXFILL abutting


RXEXCLUD and straddling RXEXCLUD are prohibited.

0.2

RXFILL104

RXFILL minimum space to PCFUSE.

RXFILL105

RXFILL minimum space.

0.15

RXFILL106

RXFILL minimum width.

0.34

RXFILL107

RXFILL maximum width.

RXFILL110

RXFILL minimum within NW.

0.240

RXFILL111

RXFILL space to NW, with abutting prohibited, and RXFILL must not straddle NW.

0.240

PCFILL200

PCFILL must not touch (LOGOBND, PC, PCFUSE, PCING, PROTECT, RX).

PCFILL201

PCFILL minimum space to (PC, PCING).

0.64

PCFILL202

PCFILL minimum space to (LOGOBND, PROTECT, RX, PCEXCLUD). PCFILL abutting


PCEXCLUD and straddling PCEXCLUD are prohibited.

0.2

PCFILL204

PCFILL minimum space to PCFUSE.

PCFILL205

PCFILL minimum space.

0.22

PCFILL206

PCFILL minimum width.

0.34

PCFILL207

PCFILL maximum width.

xxFILL299

xxFILL must be within CHIPEDGE, where xx = PC, RX.

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Table 3-74. MxFILL Design Rules


Rule

Notes

Description

Design

MXFILL500

MxFILL must not touch (KERFEXCL, LOGOBND, Mx, PROTECT), where Mx = M1-M7, BA,
BB, BD,BE, BG, FA, FB, LB.

MXFILL502

MxFILL space to PCFUSE with touching prohibited, where Mx = M1 or M2.

MXFILL504

MxFILL must not touch MxING, where Mx = M1-M7.

MXFILL511

MxFILL space to (Mx, MxING), where Mx = M1-M7.

0.458

MXFILL512

MxFILL minimum space to (KERFEXCL, LOGOBND, MxEXCLUD, PROTECT), where Mx =


M1-M7. MxFILL abutting MxEXCLUD and straddling MxEXCLUD are prohibited.

0.20

MXFILL515

MxFILL minimum space, where Mx = M1-M7

0.15

MXFILL516

(MxFILL not touching IND) width, where Mx = M1-M7.

0.258

MXFILL518

(MxFILL touching IND) width, where Mx = M1-M7

0.20

MXFILL519

MxFILL maximum width. (Checked y sizing down 1.5um/side), where Mx = M1-M7

MXFILL521

BxFILL minimum space to Bx, where Bx = BA, BB, BD.

0.4

MXFILL522

BxFILL minimum space to (BxEXCLUD, LOGOBND, PROTECT, KERFEXCL), where Bx =


BA, BB, BD. BxFILL abutting BxEXCLUD and straddling BxEXCLUD are prohibited.

0.35

MXFIL 525

BxFILL minimum space, where Bx = BA, BB, BD.

0.3

MXFILL526

(BxFILL not touching IND) width, where Bx = BA, BB, BD.

0.88

MXFILL527

(BxFILL touching IND) width, where Bx = BA, BB, BD.

0.4

MXFILL528

BxFILL maximum width. (Checked y sizing down 2 um/side), where Bx = BA, BB, BD.

MXFILL541

FxFILL minimum space to Fx, where Fx = FA, FB.

0.8

MXFILL542

FxFILL minimum space to (FxEXCLUD, KERFEXCL, LOGOBND, PROTECT), where Fx =


FA, FB. FxFILL abutting FxEXCLUD and straddling FxEXCLUD are prohibited.

0.8

MXFILL545

FxFILL minimum space, where Fx = FA, FB.

0.6

MXFILL546

(FxFILL not touching IND) width, where Fx = FA, FB.

1.8

MXFILL547

(FxFILL touching IND) width, where Fx = FA, FB.

0.8

MXFILL548

FxFILL maximum width. (Checked y sizing down 2 um/side),where Fx = FA, FB

MXFILL591

LBFILL space to LB.

2.84

MXFILL592

LBFILL minimum space to (KERFEXCL, LOGOBND, PROTECT, LBEXCLUD). LBFILL


abutting LBEXCLUD and straddling LBEXCLUD are prohibited.

2.84

MXFILL595

LBFILL minimum space.

2.4

MXFILL596

LBFILL exact width.

7.11

MXFILL597

LBFILL minimum space to IND with touching prohibited

2.84

MXFILL598

xxFILL must be rectangle, where xx = M1-M6, BA, BB, BD, FA, FB, LB.

MXFILL599

xxFILL must be within CHIPEDGE, where xx = M1-M7, BA, BB, BD, FA, FB, LB

0.0

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3.49 NOHALO and NOSD Design Rules


There is no spice model to support for device using NOHALO and NOSD layers. Designer should approach to
GLOBALFOUNDRIES field engineer for the usage of these two layers.
Table 3-75. NOHALO and NOSD Design Rules
Rule

Notes

Description

Design

NOHALO01

NOHALO minimum width

0.180

NOHALO02

NOHALO minimum space and notch

0.180

NOHALO03

NOHALO minimum minimum area

0.110

NOHALO04

NOHALO minimum enclosed area

0.110

NOHALO05

NOHALO minimum within JX/JZ with coinciding permitted

0.180

NOSD01

NOSD minimum width

0.180

NOSD02

NOSD minimum space and notch

0.180

NOSD03

NOSD minimum minimum area

0.110

NOSD04

NOSD minimum enclosed area

0.110

NOSD05

NOSD minimum within JX/JZ with coinciding permitted

0.180

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3.50 ACLV macros Drop-In to PRIME die


ACLV macros are used in GLOBALFOUNDRIES for intra/ inter-field inline PC CDs monitor. Cell name for ACLV
macro is MACROACLV. GLOBALFOUNDRIES strongly recommends that MACROACLV cells be distributed
inside the PRIME die by customers in addition to those that are automatically placed outside the PRIME die during
kerf assembly. Design rules for MACROACLV cell are listed in table 3-76.
Table 3-76. ACLV Macro Design Rules
Rule

Description

Design

ACLV_1

MACROACLV exact length and width (MACROACLV is a square shape).

6.666

ACLV_2

MACROACLV space to MACROACLV.

97.130

ACLV_3

MACROACLV minimum space to (RX, PC) with MACROACLV touching (RX,


PC) prohibited.

0.730

During data preparation, the content of each MACROACLV cell is automatically replaced by a swap file containing
the actual ACLV pattern. A typical 10mm x 10mm die requires approximately 15 ACLV holders, and they can be
placed anywhere in the design hierarchy. See Table 3-77 for general guidelines on number of MACROACLV cells
drop-in for different die sizes. For placement of MACROACLV cells near CHIPEDGE, GLOBALFOUNDRIES
recommends that these MACROACLV cells be within 0.5mm from CHIPEDGE, see Figure 3-76 for illustration.
Table 3-77. General guidelines on number of MACROACLV cells drop-in for different PRIME die sizes
S/N

Length (mm)

Width (mm)

Area (mm2)

10

10

100

No. of MACROACLV
cells drop-in
15

64

10

36

16

Figure 3-76. Placement of MACROACLV near CHIPEDGE

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4. Design for Manufacturability


Chip design establishes a chips vulnerability to defect-induced yield loss. The design optimization guidelines
described in this section were generated following the development and use of critical area analysis tools on a wide
variety of designs. Following these guidelines helps ensure:

Faster technology and product development because manufacturing sites typically target CA and V1 images
at upper specification limits and metal spacing near lower specification limits to prevent open circuits.
Improved yields because the resulting designs will be less sensitive to the random manufacturing defects
that impact yield.
More chips that fulfill the specifications sooner.
Fewer process variations, especially for contacts.
Fewer parasitics and improved circuit performance.

Design for manufacturability does not always require drastic changes. Every change, including a change of only
one grid point, can help. The following general recommendations will help improve the manufacturability of a
design:

Do not compromise on area; use existing empty space.


Use the recommended rules wherever possible.
Increase space and width equally wherever possible.
For long, parallel metal or polysilicon lines, use wider spacing. (A long line is approximately 50 times the
minimum design length.)

Recommended rules have been categorized into relative priorities in order to:
- Denote which rules are predicted to have a more significant functional yield impact when followed thereby driving
efficient design changes.
- Enable Design trade-offs.
Priorities Defined (1 4)
- Priority level 1 defines rules with highest predicted relative yield leverage.
- Priority level 4 defines rules with the lowest predicted relative yield leverage.

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4.1 Recommended Nonminimum Design Rules for Yield Enhancement


Follow guideline above and always use larger than minimum design dimensions whenever possible, unless it
results in increased chip size or decreased performance. Using recommended design rules in Table 4-1 will result
in improved yields.
The recommended design rules in Table 4-1 are being checked in the MCD (manufacturing check deck).
Table 4-1. Priority for Primary Recommended Rules
Priority

Primary Recommended Rules

1(highest)

50R, 52R, 114R, 207R, 207bR ,505R, 505aR, 505bR

51R, 102R, 115R, 204R, 204eR , 508aR,

SE1R, SE2aR,100R, 208aR, 209aR , 502IR, 502jR, 508bR, 570aR, 570bR, 570R, 602iR, 602jR, 603_orR
, 603aR, 603bR, 610aR, 610bR, 610R, 611aR, 611bR, 611R

502R, 504IR, 573R, 602R, 616R, 636R

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5. Device Electrical Parameters


All the dimensions in this section are wafer dimensions unless otherwise specified. Electrical parameters are given
for a temperature of 25C unless otherwise specified. For wide/long device >2/2, please consult the process owner
for more information.

5.1 Available Devices


Table 5-1. Available Field-Effect Transistors
FET Name

Model
Name

VDD (V)

LDesmin
(m)

Tox_eq (nm)

Unique Design Levels1

Unique Mask Layers1

Regular-Vt NFET

nfet

1.1

0.040

1.8

JX

BV

Regular-Vt PFET

pfet

1.1

0.040

1.8

NW,JZ

CV

Sueprlow-Vt NFET

slvtnfet

1.1

0.040

1.8

JX, SLVT

GY

Superlow-Vt PFET

slvtpfet

1.1

0.040

1.8

NW,JZ, SLVT

IY

Low-Vt NFET

lvtnfet

1.1

0.040

1.8

JX, LVT

XW

Low-Vt PFET

lvtpfet

1.1

0.040

1.8

NW,JZ,LVT

LW

High-Vt NFET

Hvtnfet

1.1

0.040

1.8

JX, HVT

NR

High-Vt PFET

hvtpfet

1.1

0.040

1.8

NW, JZ,HVT

PR

1.5V HSIO NFET

egvnfet

1.5

0.100

2.8

EG, JX

GN, IN, DG

1.5V HSIO PFET

egvpfet

1.5

0.100

2.8

NW, EG, JZ

GP, IP, DG

1.8V HSIO NFET

egnfet

1.8

0.150

2.8

EG, JX

GN, IN, DG

1.8V HSIO PFET

egpfet

1.8

0.150

2.8

NW. EG, JZ

GP, IP, DG

egldnfet

1.8

0.150

2.8

EG, JX

GN, IN, IP, DG

egldpfet

1.8

0.150

2.8

NW. EG, JZ

N3, GP, IN, IP, DG

1.8V I/O NFET dgv

dgvnfet

1.8

0.250

5.2

DG, JX

DE, JN, DG

1.8V I/O PFET dgv

dgvpfet

1.8

0.250

5.2

NW, DG, JZ

DF, JP, DG

2.5V I/O NFET

dgnfet

2.5

0.270

5.2

DG, JX

DE, JN, DG

2.5V I/O PFET

dgpfet

2.5

0.270

5.2

NW, DG, JZ

DF, JP, DG

dgldnfet

2.5

0.270

5.2

DG, JX

DE, JN, JP, DG

dgldpfet

2.5

0.270

5.2

NW, DG, JZ

N3, DF, JN, JP, DG

3.3V I/O NFET overdrive

dgxnfet

3.3

0.550

5.2

DG, JX

DE, JN, DG

3.3V I/O PFET overdrive

dgxpfet

3.3

0.440

5.2

NW, DG, JZ

DF, JP, DG

dgxldnfet

3.3

0.550

5.2

DG, JX

DE, JN, JP, DG

dgxldpfet

3.3

0.440

5.2

NW, DG, JZ

N3, DF, JN, JP, DG

Native thin NFET

zvtnfet

1.1

0.3

1.8

ZVT, JX

BV

Native medium NFET

zvtegnfet

1.8

0.8

2.8

ZVT, EG, JX

GN, DG

Native thick NFET

zvtdgnfet

2.5

1.2

5.2

ZVT, DG, JX

DE, DG

1.8V Medium-oxide 5V
LDNMOS
1.8V Medium-oxide 5V
LDPMOS

2.5V Thick-oxide 5V
LDNMOS
2.5V Thick-oxide 5V
LDPMOS

3.3V Thick-oxide 5V
LDNMOS
3.3V Thick-oxide 5V
LDPMOS

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FET Name

Model
Name

LDesmin
(m)

VDD (V)

Tox_eq (nm)

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Unique Design Levels1

Unique Mask Layers1

1. Additional design level beyond the base feature-required front-end-of-line (FEOL) levels (that is, RX, NW, ZP, PC, PH, BH, TJ, JX, and JZ).
Additional masks beyond the base feature-required front-end-of-line (FEOL) levels (that is, RX, NW, BF, ZP, PC, BN, BP and CA).
2. Higher HC degradation is expected on larger pitch (>440nm) for DGPFET for the same minimum Ldes.

Table 5-2. Other Available Devices


Device Name

Unique Design Levels1

Model Name

Unique Mask Layers

Diffusion Diodes
N+junction

diodenx

N-well contact

P+ junction

diodepnw

N+ junction T3

N3

Triple-well contact T3

N3

N+ tie down diode

tdndsx

TIEDOWN

P+ tie down diode

tdpdnw

TIEDOWN

DE, JN, DG

DF, JP, DG

N+junction DG
P+junction DG

diodenx

diodepnw
4

N+ tie down diode DG

tdndsx

TIEDOWN

DE, JN, DG

P+ tie down diode DG

tdpdnw4

TIEDOWN

DF, JP, DG

N+ tie down diode T3

N3

nwell-psub

diodenwx

dnwell-psub

diodetwx

N3

pwell-dnwell

diodepwtw

N3

Vertical PNP bipolar transistor

vpnp

SBLK, BIPOLAR

OP

Vertical NPN bipolar transistor

vnpn

SBLK, BIPOLAR

N3, OP

Unsalicided P+Poly

opppcres

OP, PRES

OP

Unsalicided N+Poly

npolyf_u

OP, PRES

OP

Unsalicided P+Diff

pplus_u

OP, DRES

OP

Unsalicided N+Diff

opndres

OP, DRES

OP

OP N+ diff resistor T3

N3, OP

Salicided P+Poly

ppolyf_s

POLY_SAL

Salicided N+Poly

npolyf_s

POLY_SAL

Salicidied P+Diff

pplus_s

DIFF_SAL

CV

Salicided N+Diff

nplus_s

DIFF_SAL

BV

Nwell resistor under STI

nwres

NWRES

Nwell resistor under active

nwella

BPNWR

OP

Well Diodes

Bipolar Device

Resistors

Capacitors

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Unique Design Levels1

Model Name

Unique Mask Layers

Thin-oxide NCAP

ncap

Medium-oxide NCAP

egncap

EG

IP, DG

Thick-oxide NCAP

dgncap

DG

JP, DG

Thin-oxide PCAP

pcap

T3

N3

Medium-oxide PCAP

egpcap

T3, EG

N3, IN, DG

Thick-oxide PCAP

dgpcap

T3, DG

N3, JN, DG

HCVNCAP

hcvncap

HCVNCAP

APMOM

apmom

VNCAPHV

esdnsh

ESD_xxx3

OP, BV

1.5V ESD EG NFET

esdnsh

ESD_xxx

OP, GN, IN, DG

1.8V ESD EG NFET

esdnsh

ESD_xxx3

OP, GN, IN, DG

1.8V ESD DG NFET

esdnsh

ESD_xxx3

OP, DE, JN, DG

2.5 ESD DG NFET

esdnsh

ESD_xxx

OP, DE, JN, DG

3.3 ESD DG NFET

esdnsh

ESD_xxx3

OP, DE, JN, DG

1.1V ESD NFET W/ ESD implant

esdnsh_ed

ESD_xxx3

OP, BV, ED

1.5V ESD EG NFET W/ ESD implant

esdnsh_ed

ESD_xxx3

OP, GN, IN, DG, ED

1.8V ESD EG NFET W/ ESD implant

esdnsh_ed

ESD_xxx

OP, GN, IN, DG, ED

1.8V ESD DG NFET W/ ESD implant

esdnsh_ed

ESD_xxx3

OP, DE, JN, DG, ED

2.5 ESD DG NFET W/ ESD implant

esdnsh_ed

ESD_xxx3

OP, DE, JN, DG, ED

esdnsh_ed

ESD_xxx

OP, DE, JN, DG, ED

1.1V ESD PFET

esdpsh

ESD_xxx3

OP, CV

1.5V ESD EG PFET

esdpsh

ESD_xxx3

OP, GP, IP, DG

1.8V ESD EG PFET

esdpsh

ESD_xxx3

OP, GP, IP, DG

1.8V ESD DG PFET

esdpsh

ESD_xxx

OP, DF, JP, DG

2.5 ESD DG PFET

esdpsh

ESD_xxx3

OP, DF, JP, DG

3.3 ESD DG PFET

esdpsh

ESD_xxx3

OP, DF, JP, DG

esdnsh_tw

ESD_xxx3

N3, OP, BV

1.5V ESD Triple Well EG NFET

esdnsh_tw

ESD_xxx

N3, OP GN, IN, DG

1.8V ESD Triple Well EG NFET

esdnsh_tw

ESD_xxx3

N3, OP GN, IN, DG

1.8V ESD Triple Well DG NFET

esdnsh_tw

ESD_xxx3

N3, OP, DE, JN, DG

2.5V ESD Triple Well DG NFET

esdnsh_tw

ESD_xxx

N3, OP, DE, JN, DG

3.3V ESD Triple Well DG NFET

esdnsh_tw

ESD_xxx3

N3, OP, DE, JN, DG

ESD NFET
1.1V ESD NFET

ESD NFET w/ ESD IMPLANT

3.3 ESD DG NFET W/ ESD implant


ESD PFET

ESD Triple-Well NFET T3


1.1V ESD Triple Well NFET

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Unique Design Levels1

Model Name

Unique Mask Layers

ESD other devices


ESDSCR Dual Well Version

esdscr_dw

ESDSCR_HBM

ESDSCR Triple Well Version

esdscr_tw

ESDSCR_HBM

N3

ESD Vertical PNP bipolar

esdvpnp

ESD_xxx3

CV

ESD Vertical NPN bipolar

esdvnpn

ESD_xxx

N3, BV

ESD N+ junction

esdndsx

ESD_xxx3

SBLK n resistor

sblkndres

ESD_xxx

OP

SBLK n resistor w/ ESD implant

sblkndres_ed

ESD_xxx3

OP, ED

SBLK p resistor

sblkpdres

ESD_xxx3

OP

ESD Stacked NFET Shell

esdnsh_stk

ESD_xxx

efuse

EFUSE

FUSE
Efuse

Triple Well FETs (No additional models required)


Triple-Well NFET Super Low-Vt

slvtnfet

N3, GY

Triple-Well NFET Low-Vt

lvtnfet

N3, XW

Triple-Well NFET Regular-Vt

nfet

N3, BV

Triple-Well NFET High-Vt

hvtnfet

N3, NR

Triple-Well 1.8V HSIO NFET

egnfet

N3, GN, IN, DG

Triple-Well 1.8V NFET dgv

dgvnfet

N3, DE, JN, DG

Triple-Well 2.5V I/O NFET

dgnfet

N3, DE, JN, DG

3. ESD_xxx is defined as either ESD_HBM or ESD_CDM


4. Respective DG diode model parameters are selected by instance parameter diosel=1

EG
DG
T3
T3, EG
T3, DG

ncap
egncap
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dgncap
pcap
egpcap
dgpcap
hcvncap
apmom

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5.2 Compact Models


40nm-LP compact models are available.

5.3 NFET in Isolated P-Well (Triple-Well) Devices


All NFET devices in Table 5-1 are available in a standard substrate/p-well and isolated p-well (triple-well) that can
be biased independently from the substrate. The electrical parameters in following sections are the same for the
substrate/p-well and triple-well versions of the NFET.

5.4 Well Edge-Proximity Effect


NFET and PFET devices less than 1 m from n-well and triple-well edges will have a different threshold voltage
than devices located further away from well edges. NFETs located in the substrate will behave differently than
triple-well NFETs. The magnitude of the well edge-proximity effect also depends on the oxide thickness. The root
cause of this phenomenon originates from dopant atom scattering in the photo resist, which changes the effective
doping of the adjacent devices.

Figure 5-1. Well Edge-Proximity Effect Due to Dopant Atom Scattering

A model is available to calculate this effect based on the device dimensions, device type, proximity to, and the
number of proximate well edges.

5.5 Shallow Trench Isolation Design Specifications


The following specifications restrict the shallow trench isolation (STI) oxide width and applied voltage under normal
operating conditions. These specifications can be used to ensure the acceptable leakage level of 1.0pA/ m.

5.6 Stress Proximity


PC-to-PC pitch and CA-to-CA pitch can influence the strain and carrier mobility in a device and, consequently, the
device performance. The device compact model can account for stress proximity effects when the appropriate
device parameters are provided.

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5.7 Important Notes


5.7.1 Device Operating Voltages
Table 5-3. Operating Voltages
Gate
Dielectric
Thickness

Devices

LDes (m)

Nominal
VDD (V)

Maximum
VDD max (V)

1.1

1.21

Overdrive
high
VDD
(V)

Maximum
Overdrive
VDDhigh (V)

VDD
Tolerance
(%)

Low-Vt
Thin
(1.80nm)

Regular-Vt

1.26

10

0.3

1.5 V high-speed I/O

0.100

1.5

1.65

1.8 V regular I/O

0.150

1.8

1.98

0.8

1.8

1.98

0.25 (n)
0.25 (p)

1.8

1.98

2.5 V regular I/O

0.27

2.5

2.75

3.3 V regular I/O

0.55 (n)
0.44 (p)

3.3

3.63

1.2

2.5

2.75

Medium-oxide zero-Vt
1.8 V thick-oxide I/O
Thick
(5.2 nm)

1.2

High-Vt
Thin-oxide zero-Vt

Medium
(2.8 nm)

0.040

Thick-oxide zero-Vt

10

10

The final values will be available after technology qualification.


To ensure circuit stability and eliminate device degradation during product use conditions, circuit designers should
consider reliability design rules and perform worst-case simulations.

5.7.2 Trigger and Sustaining Voltage of MOSFET Snapback


MOSFET snapback breakdown occurs when the parasitic bipolar transistor is turned on. Snapback causes a very
high, destructive current to pass through the drain area and should be prevented. The trigger voltage is the
maximum drain voltage that prevents snapback. The sustaining voltage is the drain-to-source voltage drop during
snapback.

5.7.3 Device Length and Width


Device design length, LDes, refers to the PC design level and the device design width, W Des, refers to the RX
design level (see Figure 5-2)

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Figure 5-2. Device Length and Width

Nominal polysilicon gate length after processing, Lp, and nominal channel width, Weff, are used in device design,
performance projection, and device modeling. They differ from L Des and W Des by L and W :

The worst-case polysilicon gate length, Lp_wc, and worst-case channel width, Weff_wc, are :

5.7.4 Channel Length/Width Variation


Process variation, such as gate lithography, etch bias, and lateral source/ drain diffusion, results in channel length
variation. Variations in the STI width lead to channel-width tolerances.

5.7.5 Threshold voltage


Threshold voltage is defined as the gate-to-source bias, VG, at which :
|ID | = 10 nA*W / L
for SG
|ID | = 100 nA*W/L
for EG/DG

5.7.5.1 Threshold Voltage Tolerance


Threshold voltage tolerance can be calculated by combining the base tolerance with the tolerance expected from
the short and narrow channel effects. The threshold tolerance, D vt, is :

where,
Dvtb
LDesmin
Lmin-3
WDes
WDes-3

= 3 base Vt tolerance of 0.045 V


= minimum design length
= 3 minimal length
= nominal design width
= width with 3 width variation

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5.7.6 Gate Dielectric Thickness (Tox_eq, Tox_gl, Tox_inv)


The equivalent thickness (Tox_eq) of the gate dielectric is defined as:

where,
Tphy

= physical thickness of the gate dielectric


ox
= dielectric constant of SiO2 = 3.9
dialec = dielectric constant of the actual gate dielectric
Tox_eq is a performance measure and cannot be monitored. Gate-oxide leakage and the corresponding
leakage-equivalent oxide thickness are measured. The conversion formula from leakage to oxide thickness is
given by:

in nanometers, where J is the current through the oxide measured at |VG| = 2V in accumulation.
Tox_inv is defined as Tox_inv = ox x 0 / Cinv
Where,

0
Cinv

= vacuum permeability, 0 = 8.854 x 10 F/cm


= gate capacitance measured in inversion
-14

Due to the excessive leakage of the gate dielectric, measured capacitance is a strong function of the test structure
and frequency.

5.7.7 Gate-Oxide Leakage


Gate-oxide leakage is a major contributor to device leakage for thin-oxide devices.
There is significant leakage through the gate into the source/drain in gate-inversion mode (VG > Vt, VD = VS = 0V).
Table 5-4 presents leakage values for FET devices with nominal LDes values. For devices in standby mode,
leakage will depend on the design length.
Table 5-4. Thin-Oxide Gate Leakage for Different Models at 25C
Leakage
Mode

VD (V)

VB (V)

VG (V)

Units

Standby Ion (inversion mode)

1.1

Standby Ion (maximum Vdd)

Standby Ioff

1.1

Standby Ioff (maximum Vdd)

1.2

NFET

PFET

nA/m

TBD

TBD

1.2

nA/m

TBD

TBD

nA/m

TBD

TBD

nA/m

TBD

TBD

Gate-oxide leakage depends on the threshold voltage. Devices with lower threshold voltages can have higher
gate leakages. At the supply-voltage level, the difference is small (less than 5%). At 25C to 85C, gate-oxide
leakage increases by 15%. Use the device models to generate gate-oxide leakage values.
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5.8 Superlow-Vt / Low-Vt FET Device


Table 5-5a. Electrical Parameters for Low-Vt FET Devices
LVT
Dimensions
Parame
ter

Definition

tol

WACWV

tol

Tinv
Tox_gl
Vtlin1
Vtsat1

VD = 0.05 V, VB
=0V
VD = 1.1 V, VB
=0V

1.2V

Value

Value

NFET

PFET

0.005 0.003

0.000 0.003

0.005 0.007

0.000 0.007

0.005 0.0075

0.000 0.0075

0.00 0.016

0.00 0.016

0.00 0.025

0.00 0.025

nm

2.4 0.14

2.60 0.14

nm

1.80 0.13

1.75 0.13

1/1

0.213 (+0.035 / -0.034)

1 / 0.040

Units

ACLV

1.1V

NFET

PFET

0.299 (+0.033 / -0.035)

0.213

0.299

0.151 (+0.097 / -0.086)

0.192 (+0.081 / -0.098)

0.137

0.178

0.3 / 0.040 (N)


0.5 / 0.040 (P)

0.164 (+0.109 / -0.111)

0.198 (+0.087 / -0.104)

0.15

0.184

0.12 / 0.040

0.166 (+0.138 / -0.163)

0.22 (+0.13 / -0.142)

0.152

0.206

174 (+27 / -24)

186 (+35 / -24)

188

200

60 (+11 / -11)

76 (+11 / -13)

60

76

WDes / LDes

V
V

A/
m

1/1

11 (+9% / -9%)

3.5 (+11% / -11%)

12

3.9

Idlin2

VD = 1.1 V, VB
=0V
VD =1.1 V, VB =
0V
VB = 0 V, Vtsat
Vtlin
VD = 0.05 V,
Vt-shift VB = 01
V
VD = 0.05 V,
VG = 1.1 V, VB
=0V
VD = VG = 1.1
V, VB = 0 V

A/
m

1 / 0.040

696 (+21% / -25%)

339 (+20% / -19%)

842.2

417

Ion2

A/
m
A/
m

0.3 / 0.040 (N)


0.5 / 0.040 (P)

724 (+28% / -28%)

347 (+23% / -21%)

876

426.8

Ion2

VD = VG = 1.1
V, VB = 0 V
VD = VG = 1.1
V, VB = 0 V

0.12 / 0.040

800 (+43% / -35%)

401 (+36% / -32%)

968

493.2

Ioff2

VD = 1.1 V, VG
= VB = 0 V

nA/ m

1 / 0.040

7.6 (0.09x / 7x)

3.4 (0.11x / 12x)

10.6

4.8

Ioff2

VD = 1.1 V, VG
= VB = 0 V

nA/ m

0.3 / 0.040 (N)


0.5 / 0.040 (P)

5.3 (0.07x / 13x)

2.9 (0.09x / 17x)

7.4

Cj_area2

Vj = 0 V

fF/ m2

1.1053 0.2

0.996 0.2

Coverl2

VG = 0.0 V

fF/ m

0.216 0.02

0.181 0.02

Vtsat1
Vtsat1
DIBL
Body
effect

Ion2

V
V
mV

0.3 / 0.040 (N)


0.5 / 0.040 (P)

mV

L = 0.040 m

1. The threshold voltage is defined as gate-to-source bias at which:


|ID | = 10 nA*W / L
2. Normalized by Wdrawn, Ldrawn

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Table 5-5b. Electrical Parameters for Superlow-Vt FET Devices

SLVT
Dimensions
Parame
ter

Definition

L and LACLV

Units

WDes / LDes

1.1V

1.2V

Value

Value

NFET

PFET

0.005 0.003

0.000 0.003

0.005 0.007

0.000 0.007

NFET

PFET

L and Ltol

0.005 0.0075

0.000 0.0075

W and WACWV

0.00 0.016

0.00 0.016

W and Wtol

0.00 0.025

0.00 0.025

Tinv

nm

2.4 0.14

2.60 0.14

Tox_gl

nm

1.80 0.13

1.75 0.13

1/1

0.21 (+0.04 / -0.033)

0.293 (+0.043 / -0.043)

0.21

0.293

1 / 0.040

0.117 (+0.119 / -0.116)

0.153 (+0.091 / -0.106)

0.102

0.138

0.3 / 0.040 (N)


0.5 / 0.040 (P)

0.131 (+0.13 / -0.134)

0.156 (+0.097 / -0.112)

0.116

0.141

0.12 / 0.040

0.142 (+0.158 / -0.175)

0.184 (+0.137 / -0.146)

0.127

0.169

0.3 / 0.040 (N)

179 (+35 / -33)

197 (+43 / -26)

194

212

0.5 / 0.040 (P)

52 (+15 / -20)

60 (+10 / -13)

52

60

VD = 0.05 V,
VB = 0 V

VD = 1.1 V, VB
=0V

VD = 1.1V, VB
=0V

Vtsat

VD = 1.1V, VB
=0V

DIBL

VB = 0 V, Vtsat
Vtlin

mV

Body
effect

VD = 0.05 V,
Vt-shift VB =
01V

mV

VD = 0.05 V,
VG = 1.1V, VB
=0V

A/
m

1/1

11.1 (+11% / -9%)

3.5 (+12% / -13%)

12.1

3.9

VD = VG = 1.1
V, VB = 0 V

A/
m

1 / 0.040

749 (+21% / -24%)

368 (+21% / -21%)

898.8

449

VD = VG = 1.1
V, VB = 0 V

0.3 / 0.040 (N)


0.5 / 0.040 (P)

780 (+26% / -28%)

380 (+23% / -22%)

936

463.6

VD = VG = 1.1
V, VB = 0 V

A/
m

0.12 / 0.040

842 (+38% / -35%)

435 (+33% / -31%)

1010.4

530.7

VD = 1.1 V, VG
= VB = 0 V

nA/ m

1 / 0.040

20.3 (0.06x / 14x)

9.8 (0.12x / 11x)

28.4

13.7

VD = 1.1 V, VG
= VB = 0 V

0.3 / 0.040 (N)


0.5 / 0.040 (P)

12.9 (0.04x / 22x)

9.2 (0.09x / 14x)

18.1

12.8

1.106 0.2

1.000 0.2

0.217 0.02

0.183 0.02

Vtlin

Vtsat
Vtsat

Idlin

Ion
Ion
Ion
Ioff
Ioff

Cj_area
Coverl

A/
m

Vj = 0 V

nA/ m
fF/
2
m

VG = 0.0 V

fF/ m

L = 0.040 m

1. The threshold voltage is defined as gate-to-source bias at which:


|ID | = 10 nA*W / L
2. Normalized by Wdrawn , Ldrawn

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5.9 Regular-Vt FET Device


Table 5-6. Electrical Parameters for Regular-Vt FET Devices

RVT
Dimensions
Parame
ter

Definition

L and LACLV

Units

1.2V

Value

Value

NFET

PFET

0.005 0.003

0.000 0.003

0.005 0.007

0.000 0.007

WDes / LDes

1.1V

L and Ltol

0.005 0.0075

0.000 0.0075

W and WACWV

0.00 0.016

0.00 0.016

W and Wtol

0.00 0.025

0.00 0.025

nm

2.4 0.14

2.60 0.14

nm

1.80 0.13

1.75 0.13

Tinv
Tox_gl

NFET

PFET

Vtlin

VD = 0.05 V,
VB = 0 V

1/1

0.233 (+0.031 / -0.035)

0.316 (+0.034 / -0.033)

0.233

0.316

Vtsat

VD = 1.1 V, VB
=0V

1 / 0.040

0.238 (+0.071 / -0.076)

0.288 (+0.079 / -0.08)

0.223

0.273

VD = 1.1V, VB
=0V

0.3 / 0.040 (N)


0.5 / 0.040 (P)

0.253 (+0.09 / -0.098)

0.295 (+0.087 / -0.086)

0.238

0.28

Vtsat

VD = 1.1V, VB
=0V

0.12 / 0.040

0.258 (+0.134 / -0.147)

0.321 (+0.135 / -0.123)

0.243

0.306

DIBL

VB = 0 V, Vtsat
Vtlin

mV

161 (+18 / -18)

161 (+16 / -10)

176

176

Body
effect

VD = 0.05 V,
Vt-shift VB =
01V

mV

0.3 / 0.040 (N)


0.5 / 0.040 (P)

83 (+13 / -16)

113 (+10 / -11)

83

113

VD = 0.05 V,
VG = 1.1V, VB
=0V

A/
m

1/1

10.9 (+9% / -7%)

3.4 (+8% / -10%)

11.8

3.8

VD = VG = 1.1
V, VB = 0 V

A/
m

1 / 0.040

563 (+19% / -19%)

268 (+22% / -22%)

675.6

327

VD = VG = 1.1
V, VB = 0 V

A/
m

0.3 / 0.040 (N)


0.5 / 0.040 (P)

575 (+26% / -23%)

272 (+25% / -24%)

690

331.8

VD = VG = 1.1
V, VB = 0 V

A/
m

0.12 / 0.040

635 (+39% / -34%)

310 (+38% / -37%)

762

378.2

VD = 1.1 V, VG
= VB = 0 V

nA/ m

1 / 0.040

0.96 (0.31x / 6x)

0.39 (0.13x / 8x)

1.34

0.55

VD = 1.1 V, VG
= VB = 0 V

0.3 / 0.040 (N)


0.5 / 0.040 (P)

0.74 (0.31x / 9x)

0.27 (0.09x / 10x)

1.04

0.38

1.045 0.2

0.996 0.2

0.203 0.02

0.172 0.02

Vtsat

Idlin

Ion

Ion
Ion
Ioff
Ioff

Cj_area
Coverl

Vj = 0 V

nA/ m
fF/
2
m

VG = 0.0 V

fF/ m

L = 0.040 m

1. The threshold voltage is defined as gate-to-source bias at which:


|ID | = 10 nA*W / L
2. Normalized by Wdrawn , Ldrawn

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5.10 High-Vt FET Device


Table 5-7. Electrical Parameters for High-Vt FET Devices

HVT
Dimensions
Parame
ter

Definition

L and LACLV

Units

1.2V

Value

Value

NFET

PFET

0.005 0.003

0.000 0.003

0.005 0.007

0.000 0.007

WDes / LDes

1.1V

L and Ltol

0.005 0.0075

0.000 0.0075

W and WACWV

0.00 0.016

0.00 0.016

W and Wtol

0.00 0.025

0.00 0.025

Tinv

nm

2.4 0.14

2.60 0.14

Tox_gl

nm

1.80 0.13

1.75 0.13

NFET

PFET

Vtlin

VD = 0.05 V,
VB = 0 V

1/1

0.288 (+0.034 / -0.038)

0.344 (+0.033 / -0.038)

0.288

0.344

Vtsat

VD = 1.1 V, VB
=0V

1 / 0.040

0.367 (+0.079 / -0.086)

0.395 (+0.089 / -0.086)

0.357

0.386

VD = 1.1 V, VB
=0V

0.3 / 0.040 (N)


0.5 / 0.040 (P)

0.376 (+0.102 / -0.117)

0.402 (+0.095 / -0.094)

0.366

0.393

Vtsat

VD =1.1 V, VB
=0V

0.12 / 0.040

0.381 (+0.152 / -0.184)

0.412 (+0.129 / -0.139)

0.371

0.403

DIBL

VB = 0 V, Vtsat
Vtlin

mV

138 (+15 / -16)

133 (+13 / -12)

148

142

Body
effect

VD = 0.05 V,
Vt-shift VB =
01 V

0.3 / 0.040 (N)


0.5 / 0.040 (P)

mV

115 (+18 / -18)

153 (+12 / -14)

115

153

VD = 0.05 V,
VG = 1.1 V, VB
=0V

A/
m

1/1

10.1 (+10% / -8%)

3.3 (+11% / -10%)

11.1

3.7

VD = VG =
1.1V, VB = 0 V

A/
m

1 / 0.040

365 (+27% / -24%)

189 (+33% / -30%)

485.5

249.5

VD = VG = 1.1
V, VB = 0 V

A/
m

0.3 / 0.040 (N)


0.5 / 0.040 (P)

370 (+37% / -31%)

189 (+36% / -32%)

492.1

249.5

VD = VG = 1.1
V, VB = 0 V

A/
m

0.12 / 0.040

415 (+59% / -44%)

220 (+55% / -42%)

552

290.4

VD = 1.1 V, VG
= VB = 0 V

nA/ m

1 / 0.040

0.041 (0.45x / 5x)

0.032 (0.55x / 6x)

0.049

0.038

VD = 1.1 V, VG
= VB = 0 V

0.3 / 0.040 (N)


0.5 / 0.040 (P)

0.044 (0.43x / 10x)

0.032 (0.6x / 8x)

0.053

0.038

1.053 0.02

0.988 0.02

0.188 0.02

0.158 0.02

Vtsat

Idlin

Ion
Ion
Ion
Ioff
Ioff

Cj_area
Coverl

Vj = 0 V

nA/ m
fF/
2
m

VG = 0.0 V

fF/ m

L = 0.040 m

1. The threshold voltage is defined as gate-to-source bias at which:


|ID | = 10 nA*W / L
2. Normalized by Wdrawn , Ldrawn

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5.11 Medium-Oxide 1.5V I/O FET Device


Table 5-8. Electrical Parameters for Medium-Oxide 1.5V I/O FET Devices

1.5V I/O
Dimensions
Paramet
er

Definition

L and LACLV

WDes / LDes

NFET

PFET

0.006 0.0056

0.006 0.0056

L and Ltol

0.006 0.0096

0.006 0.0096

W and WACWV

0.00 0.016

0.00 0.016

W and Wtol

0.00 0.025

0.00 0.025

nm

3.5 0.2

3.75 0.2

nm

2.8 0.2

2.8 0.2

Tinv
Tox_gl

Units

Value

VD = 0.05 V,
VB = 0 V

2/2

0.371 / 0.426 / 0.486

-0.383 / -0.436 / -0.512

Vtsat

VD = 1.5 V, VB
=0V

2 / 0.10

0.101/ 0.211/ 0.321

-0.490/-0.400/-0.310

Body
effect

VD = 0.05 V,
Vt-shift VB =
01 V

mV

2 / 0.1

29 / 38 / 47

128 / 137 / 146

VD = VG = 1.5
V, VB = 0 V

A/
m

2 / 0.1

578/ 705 /838

213/ 266 /327

VD = 1.5 V, VG
= VB = 0 V

nA/ m

2 / 0.1

1.5/ 15.4/ 182

0.004/ 0.043 / 0.3

Vtlin

Ion

Ioff

1. The threshold voltage is defined as gate-to-source bias at which:


|ID | = Icrit.= 100 nA*W/L
2. Normalized by Wdrawn, Ldrawn

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5.12 Medium-Oxide 1.8V I/O FET Device


Table 5-9. Electrical Parameters for Medium-Oxide 1.8V I/O FET Devices
1.8V I/O
Dimensions

Param
eter

Definition

L and LACLV

NFET

PFET

0.006 0.0056

0.006 0.0056

L and Ltol

0.006 0.0096

0.006 0.0096

W and
WACWV

0.00 0.016

0.00 0.016

W and W tol

0.00 0.025

0.00 0.025

Tinv

nm

3.5 0.2

3.75 0.2

Tox_gl

nm

2.8 0.2

2.8 0.2

Vtlin

Units

WDes / LDes

Value

VD = 0.05 V,
VB = 0 V

2/2

0.386 / 0.441 / 0.502

-0.402 / -0.456 / -0.532

Vtsat

VD = 1.8 V,
VB = 0 V

2 / 0.150

0.305 / 0.382 / 0.460

-0.524 / -0.445 / -0.378

Vtsat

VD = 1.8 V,
VB = 0 V

0.36 / 0.150

0.462 /0.372/ 0.280

-0.354 / -0.442 / -0.534

VD = 0.05 V,
Vt-shift VB =
01 V

mV

2 / 0.150

80 / 86 /92

148 / 155 / 162

Body
effect
Ion

VD = VG = 1.8
V, VB = 0 V

A/
m

2 / 0.150

561 / 651 / 743

238 / 282 / 329

Ion

VD = VG = 1.8
V, VB = 0 V

A/
m

0.36 / 0.150

592 / 711 / 838

250 / 300 / 356

Ioff

VD = 1.8 V,
VG = VB = 0 V

2 / 0.150

2.83 / 18.3 / 158

51.4 / 8.3 / 2.7

Vj = 0 V

pA/
m
fF/
2
m

1.4 0.2

1.1 0.2

VG = 0.0 V

fF/ m

0.263 0.03

0.182 0.02

Cj_area
Coverl

L = 0.15 m

1. The threshold voltage is defined as gate-to-source bias at which:


|ID | = Icrit.= 100 nA*W/L
2. Normalized by Wdrawn, Ldrawn

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5.13 Thick-Oxide 1.8V I/O FET Device


Table 5-10. Electrical Parameters for Thick-Oxide 1.8V I/O FET Devices
1.8V
Dimensions
Value
Parameter

Definition

L and LACLV

NFET

PFET

0.010 0.0056

0.010 0.0056

L and Ltol

0.010 0.0096

0.010 0.0096

W and W ACWV

0.00 0.016

0.00 0.016

W and W tol

0.00 0.025

0.00 0.025

nm

5.91 0.40

6.09 0.40

Tinv

Units

W Des / LDes

VD = 0.05 V, VB
=0V

2/2

0.484 (+0.082 /
-0.078)

0.59 (+0.081 / -0.076)

Vtsat

VD = 1.8 V, VB =
0V

2/0.25

0.235 (+0.126 /
-0.131)

0.345 (+0.113 /
-0.113)

Body
effect

VD = 0.05 V,
Vt-shift VB = 0
0.9 V

mV

2/0.25

97 (+15 / -16)

133 (+18 / -19)

VD = VG = 1.8 V,
VB = 0 V

A/
m

2/0.25

425 (+18% / -17%)

206 (+24% / -20%)

Vtlin

Ion

VD = 1.8 V, VG =
pA/
VB = 0 V
m
2/0.25
600 (0.02x / 60x)
1. The threshold voltage is defined as gate-to-source bias at which:
|ID | = 100 nA*W/L
Ioff

2. Normalized by Wdrawn, Ldrawn

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5.14 Thick-Oxide 2.5V I/O FET Device


Table 5-11. Electrical Parameters for Thick-Oxide 2.5V I/O FET Devices
2.5V
Dimensions
Value
Parameter

Definition

L and LACLV

NFET

PFET

0.010 0.0056

0.010 0.0056

L and Ltol

0.010 0.0096

0.010 0.0096

W and W ACWV

0.00 0.016

0.00 0.016

W and W tol

0.00 0.025

0.00 0.025

nm

5.91 0.40

6.09 0.40

Tinv

Units

W Des / LDes

VD = 0.1 V, VB =
0V

2/2

0.484 (+0.08 / -0.078)

0.59 (+0.077 / -0.076)

VD = 2.5 V, VB =
0V

2 / 0.27

0.28 (+0.117 / -0.122)

0.379 (+0.105 /
-0.108)

Vtsat

VD = 2.5 V, VB =
0V

0.32 / 0.27

0.283 (+0.146 /
-0.152)

0.392 (+0.136 /
-0.144)

Body
effect

VD = 0.1 V,
Vt-shift VB = 0
1.25 V

mV

2 / 0.27

147 (+16 / -17)

194 (+19 / -21)

VD = VG = 2.5 V,
VB = 0 V

A/
m

2 / 0.27

615 (+13% / -12%)

330 (+17% / -15%)

VD = VG = 2.5 V,
VB = 0 V

A/
m

0.32 / 0.27

662 (+17% / -15%)

352 (+21% / -18%)

VD = 2.5 V, VG =
VB = 0 V

pA/
m

2 / 0.27

125 (0.32x / 27x)

17 (0.2x / 17x)

Vj = 0 V

fF/
2
m

0.996 0.09

1.04 5 0.1

fF/
m

0.324 0.04

0.333 0.04

Vtlin

Vtsat

Ion

Ion

Ioff

Cj_area

Coverl

1. The threshold voltage is defined as gate-to-source bias at which:


|ID | = 100 nA*W/L
2. Normalized by Wdrawn, Ldrawn

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5.15 Thick-Oxide 3.3V I/O FET Device


Table 5-12. Electrical Parameters for Thick-Oxide 3.3V I/O FET Devices
3.3V
Dimensions
Value
Parameter

Definition

L and LACLV

NFET

PFET

0.010 0.0056

0.010 0.0056

L and Ltol

0.010 0.0096

0.010 0.0096

W and W ACWV

0.00 0.016

0.00 0.016

W and W tol

0.00 0.025

0.00 0.025

nm

5.91 0.40

6.09 0.40

Tinv
1

Vtsat

Body
effect
2

Ion

Units

W Des / LDes

VD = 3.3 V, VB =
0V
VD = 0.05 V,
Vt-shift VB = 0
1.65 V

2/0.55 (n),
2/0.44 (p)

0.47 (+0.085 / -0.082)

0.52 (+0.094 / -0.084)

mV

2/0.55 (n),
2/0.44 (p)

299 (+10 / -10)

351 (+8 / -8)

VD = VG = 3.3 V,
VB = 0 V

A/
m

2/0.55 (n),
2/0.44 (p)

540 (+10% / -10%)

307 (+12% / -11%)

VD = 3.3 V, VG =
pA/
2/0.55 (n),
VB = 0 V
m
2/0.44 (p)
0.5 (0.81x / 1.2x)
1. The threshold voltage is defined as gate-to-source bias at which:
|ID | = 100 nA*W/L
Ioff

2. Normalized by Wdrawn, Ldrawn

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5.16 Thin-Oxide Native NFET Device


Table 5-13. Electrical Parameters for Thin-Oxide Native NFET Devices

Parameter

Definition

L and LACLV

Units

ZVT

1.1V

Dimensions

Value

WDes / LDes

NFET

0.005 0.003
0.005 0.007

L and Ltol

0.005 0.0075

W and WACWV

0.00 0.016

W and Wtol

0.00 0.025

VD = 0.05 V, VB =
0V

2/2

0.056 (+0.055 / -0.068)

Vtsat

VD = 1.1 V, VB =
0V

2 / 0.3

0.089 (+0.063 / -0.068)

Body
effect

VD = 0.05 V,
Vt-shift VB = 01
V

mV

2 / 0.3

7.9 (+0.04 / -0.36)

VD = VG = 1.1 V,
VB = 0 V

A/ m

2 / 0.3

423 (+13% / -12%)

Vtlin

Ion

1. The threshold voltage is defined as gate-to-source bias at which:


|ID | = 10 nA*W / L
2. Normalized by Wdrawn, Ldrawn

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5.17 Medium-Oxide Native NFET Device


Table 5-14. Electrical Parameters for Medium-Oxide Native NFET Devices

Units

ZVT

1.8V

Dimensions

Value

WDes / LDes

NFET

Parameter

Definition

L and LACLV

0.006 0.0056

L and Ltol

0.006 0.0096

W and WACWV

0.00 0.016

W and Wtol

0.00 0.025

Tinv

nm

3.5 0.20

Tox_gl

nm

2.8 0.20

VD = 0.05 V, VB =
0V

5/5

-0.054/-0.099/-0.159

Vtsat

VD = 1.8 V, VB =
0V

2 / 0.7

-0.0083 / -0.063 / -0.123

Body
effect

VD = 0.05 V,
Vt-shift VB = 01
V

mV

2 / 0.7

18 / 19 / 17

VD = VG = 1.8 V,
VB = 0 V

A/ m

2 / 0.7

422 / 485 / 544

Vtlin

Ion

1. The threshold voltage is defined as gate-to-source bias at which:


|ID | = 100 nA*W / L
2. Normalized by Wdrawn, Ldrawn

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5.18 Thick-Oxide Native NFET Device


Table 5-15. Electrical Parameters for Thick-Oxide Native NFET Devices

Units

ZVT

2.5V

Dimensions

Value

WDes / LDes

NFET

Parameter

Definition

L and LACLV

0.010 0.0056

L and Ltol

0.010 0.0096

W and WACWV

0.00 0.016

W and Wtol

0.00 0.025

nm

5.91 0.40

Tinv
VD = 0.05 V, VB =
0V

5/5

-0.154 (+0.053 / -0.055)

Vtsat

VD = 2.5 V, VB =
0V

2 / 1.2

-0.205 (+0.055 / -0.057)

Body
effect

VD = 0.05 V,
Vt-shift VB =
01.25 V

mV

2 / 1.2

65 (+3 / -2)

A/ m

2 / 1.2

412 (+11% / -11%)

Vtlin

Ion

VD = VG = 2.5 V,
VB = 0 V

1. The threshold voltage is defined as gate-to-source bias at which:


|ID | = 100 nA*W / L
2. Normalized by Wdrawn, Ldrawn

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5.19 5V LDMOS Transistor Device


5.19.1 2.5V and 3.3V Thick-oxide 5V LDMOS Transistor Device
Table 5-16. Electrical parameters for 2.5V_DG 5V LDMOS transistor devices
Dimensions
Parameter

Definition

Vtlin

Value

Units

WDes / LDes

NFET

PFET

VD = 0.05 V, VB = 0 V,
VG@Id=50nA&W/L

5/0.28, NF=2

0.526 +/- 0.068

-0.513 +/- 0.07

Vtsat

VD = 5 V, VB = 0 V,
VG@Id=50nA&W/L

5/0.28, NF=2

0.45 +/- 0.066

-0.426 +/- 0.069

Body effect

VD = 0.05 V, Vt-shift VB = 01 V

5/0.28, NF=2

0.19 +/- 0.033

0.221 +/- 0.032

Ion

VD =5V, VG = 2.5 V, VB = 0 V

A/ m

5/0.28, NF=2

460 +/- 68

-260 +/- 39

Ioff

VD =5V, VG = VB = 0 V

pA/ m

5/0.28, NF=2

<1

<1

Ron

VD =0.1V, VG = 2.5 V, VB = 0 V

mohm-mm2

5/0.28, NF=2

4.5 +/- 0.9

10.5 +/- 2.1

5/0.28, NF=2

>8
Typical: 10.6

< -8
Typical: -10.7

BVdss

VG=VB = 0 V, VD@ID=1uA

Ron = {0.1V/[Id (A)]}*[S/D_pitch(mm)]*[W (mm)]

Table 5-17. Electrical parameters for 3.3V_DG 5V LDMOS transistor devices


Dimensions
Parameter

Definition

Vtlin

Value

Units

WDes / LDes

NFET

PFET

VD = 0.05 V, VB = 0 V,
VG@Id=50nA&W/L

5/0.4, NF=2

0.576 +/- 0.065

-0.574+/- 0.067

Vtsat

VD = 5 V, VB = 0 V,
VG@Id=50nA&W/L

5/0.4, NF=2

0.524 +/- 0.064

-0.503 +/- 0.066

Body effect

VD = 0.05 V, Vt-shift VB = 01 V

5/0.4, NF=2

0.24 +/- 0.029

0.294 +/- 0.028

Ion

VD =5V, VG = 3.3V, VB = 0 V

A/ m

5/0.4, NF=2

505 +/- 52

-305 +/- 45

Ioff

VD =5V, VG = VB = 0 V

pA/ m

5/0.4, NF=2

<1

<1

Ron

VD =0.1V, VG = 3.3V, VB = 0 V

mohm-mm2

5/0.4, NF=2

4.5 +/- 0.9

10.5 +/- 2.1

5/0.4, NF=2

>8
Typical: 10.6

< -8
Typical: -10.7

BVdss

VG=VB = 0 V, VD@ID=1uA

Ron = {0.1V/[Id (A)]}*[S/D_pitch(mm)]*[W (mm)]

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5.19.2 1.8V Medium-oxide 5V LDMOS Transistor Device


Table 5-18. Electrical parameters for 1.8V_EG 5V LDMOS transistor devices
Dimensions
Parameter

Definition

Vtlin
Vtsat

Value

Units

WDes / LDes

NFET

PFET

VD = 0.05 V, VB = 0 V,
VG@Id=50nA&W/L

5/0.28 (N), NF=2


5/0.28 (P), NF=2

0.504+/-0.062

-0.47+/-0.065

VD = 5 V, VB = 0 V,
VG@Id=50nA&W/L

5/0.28 (N), NF=2


5/0.28 (P), NF=2

0.48 +/- 0.062

-0.455+/-0.065

0.136 +/- 0.018

0.224 +/- 0.012

Body effect

VD = 0.05 V, Vt-shift VB = 01 V

5/0.28 (N), NF=2


5/0.28 (P), NF=2

Ion

VD =5V, VG = 1.8 V, VB = 0 V

A/ m

5/0.28 (N), NF=2


5/0.28 (P), NF=2

379+/-55

-157+/-24

pA/ m

5/0.28 (N), NF=2


5/0.28 (P), NF=2

<1

<1

mohm-mm2

5/0.28 (N), NF=2


5/0.28 (P), NF=2

3.3+/-0.66

8.4+/-1.68

5/0.28 (N), NF=2


5/0.28 (P), NF=2

>8
Typical: 11

< -8
Typical: -11

Ioff
Ron
BVdss

VD =5V, VG = VB = 0 V
VD =0.1V, VG = 1.8 V, VB = 0 V
VG=VB = 0 V, VD@ID=1uA

Ron = {0.1V/[Id (A)]}*[S/D_pitch(mm)]*[W (mm)]

5.20 Junction Diode


5.20.1 STI-Bounded Junction Breakdown Voltage
Note : Table 5-19 will be include leakage information in a future release.
Table 5-19. Reverse-Bias Breakdown Voltage
Device

Definition

Units

N-Well
Substrate

P+N-Well

N+P-Well

Low-Vt FET
Regular-Vt FET
High-Vt FET
Regular I/O FET

IL = 1 A,
2
Area = 200 x 150 m

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5.21 Vertical PNP Bipolar Transistor


Table 5-20 presents the electrical parameters used to characterize the vertical PNP bipolar transistor for typical
2
area 3.2x3.2m . Parameters are given for a PNP structure with regular-Vt wells. For applicable design rules, see
Section 3.19 Vertical PNP Bipolar Transistor Design Rules.
2

Table 5-20. Electrical Parameters for the Vertical PNP Bipolar Transistor (Emitter area=3.2x3.2m )
Parameter

Definition

Test Procedure

Units

Nominal

VBE

Base-emitter voltage

VBE at IE = 10 A

0.766 2%

BVCEO

Collector-emitter breakdown voltage

IC-force = 10 A, IB = 0

>9

Current gain

= IC / IB at VBE = 0.7V

1.22 20%

VBE

Transistor mismatch

mV

TBD

Ideality

1.020 3%

1. The ideality variation is 3%.

5.22 Resistors
5.22.1 Silicide-Blocked Resistors
40nm-LP offers four OP resistors: n+/p+ polysilicon and n+/p+ diffusion. These resistors are made by using the OP
mask to block silicidation.

5.22.1.1 Precision P+ Poly Resistor Electrical Parameters


Table 5-21. Electrical parameters of Precision P+ Poly resistor device
Precision P+ Poly
Resistor

Parameter

Definition

Unit

Rs

Sheet resistance

/sq

380 11%

Rend

End resistance

24 50%

Width bias

Length bias

TCRS1
TCRS2
TCRN1

Linear body temperature coefficient


Quadratic body temperature coefficient
Linear term temperature coefficient

0.006
-0.063
o

ppm/ C
o

ppm/ C
o

ppm/ C
o

1.41E-04
5.02E-07
-1.15E-04

TCRN2

Quadratic term temperature coefficient

ppm/ C

-8.57E-06

VCRS1

Linear body voltage coefficient

ppm/V

--

VCRS2

Quadratic body voltage coefficient

ppm/V

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5.22.2 Silicided Resistors


40nm-LP offers four silicide resistors: n+/p+ polysilicon and n+/p+ diffusion.

5.22.3 Electrical Parameters (at 25C)


End resistance, Rend, is used to account for contact and spreading resistance at the ends of the device based on
the design rules.
Table 5-22a. Electrical Parameters for Silicide-Blocked Resistors
OP Resistor
Parameter

Rs

Definition

Units

Sheet resistance

/sq.

N+
Diffusion

P+
Diffusion

N+
Polysilicon

P+
Polysilicon

110 15%

197 15%

173 20%

618 15%

1. W/L of the resistor used is 2/40

Table 5-22b. Electrical Parameters for Silicided Resistors


Silicided Resistor
Parameter

Rs

Definition

Units

Sheet resistance

/sq.

N+
Diffusion

P+
Diffusion

N+
Polysilicon

P+
Polysilicon

12 35%

8 35%

11 35%

8 35%

1. W/L of the diffusion/polysilicon resistor used is 0.06/25 and 0.04/25, repsectively

Table 5-22c. Electrical Parameters for N-well Resistors


N-well Resistor
Parameter
Rs1

Definition
Sheet resistance

Units
/sq.

Nwell under STI

Nwell over Active

1540 35%

500 35%

1. W/L of the n-well resistor used is 2/40.

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5.22.4 Resistance Calculation


The zero bias resistance is given by :
2

where,
R
WDes
T
LDes

= resistance in
= design with in m
= temperature difference to 25C
= design length in m

5.22.4.1 OP Resistor Capacitance


The capacitance associated with the polysilicon/ silicided OP resistor is the same as that for any polysilicon wiring
level (see Section 5-27 Wiring Capacitance Models). The total capacitance is divided in half, and each half is
assigned to one end of the resistor body inside the end resistor. For diffusion OP resistor junction capacitance,
see Section 5-20 Junction Diodes.
The total area for capacitance is given by :

where LOLP is the (RX overlap past OP) dimension for an n+diffusion or p+polysilicon OP resistor.

5.22.4.2 Polysilicon OP Resistor Use


Polysilicon OP resistors can be used I/O circuits; however, their maximum current ratings must be followed. Due
to a possible increase in temperature from an ESD event, the ESD guidelines should be considered when sizing
the width of polysilicon OP resistors.

5.22.4.3 Resistor Tolerance


OP resistor tolerance is given by :

where,
TRs
Rtotal
T W
TLop
TRend

= sheet resistance tolerance


= nominal total resistance
= W tolerance
= OP width tolerance
= end resistance tolerance

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5.23 Hierarchal Vertical Natural Capacitor (HCVNCAP)


Table 5-23. Summary of HCVNCAP DC data
Parameters

HCVNCAP(M1-M6)

APMOM(M1-M6)

Areadrawn (um x um)

W100xL150

W150.01xL150

Unit Capacitance (fF/um2)

3.95 20%

4.65 15%

Breakdown Voltage @ 1A (V)

>20

>20

Leakage Current @ 5V (A)

<10e-12

<10e-12

TC1 Absolute Value (ppm/C)

<10

<25

VC1 Absolute Value (ppm/V)

<1

<1

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5.24 NFET in N-Well Capacitor (NCAP)


5.24.1 Design Guidelines
In 40nm-LP, the design length and width are short enough to minimize the effect of n-well series resistance on the
frequency response of the capacitor and wide enough to minimize the effect of polysilicon series resistance.

Table 5-24. Electrical Parameters for the NFET in N-Well Capacitors


Parameter

Definition

Cacc_density

Total accumulation capacitance density

Device
geometry

L (m) x W (m) x number of fingers


2
Cmin

Tunability

Cacc /

Igate_USL

Accumulation leakage USL

Igate_target

Units

Accumulation leakage target

SGNCAP

EGNCAP

DGNCAP

14.35 15%

9.8 15%

6.3 15%

19.9 x 3.9 x 21

19.9 x 3.9 x 21

19.9 x 3.9 x 21

Ratio

6.9

3.6

fF/ m

nA/ m

0.0015

Negligible

nA/ m

1.4

0.0003

Negligible

GLOBALFOUNDRIES strongly recommends connecting all (PC touching RX) to a diffusion.


Notes:
1. Cacc density is measured in accumulation at Vdiffusion = -1.1V, -1.8 V and 2.5 V for SGNCAP, EGNCAP and
DGNCAP, respectively.
2. Cmin is measured in depletion at Vdiffusion = 0.6 V.
3. The total measured device capacitance reported here is a function of both area and fringe capacitance terms.
The nominal value equation for the capacitance of an NCAP at 25C is:

where,
CA
L
W
Ld
Wd

= capacitance (V) per area


= Ld - L
= W d - W
= Designed length
= Designed width
L, W are extracted from Table 5-6, Table 5-9 and Table 5-11 for SG, EG and DG NCAPs

respectively.
CL, CW and CF are fringe capacitance terms which are functions of the channel length (L), RX
width (W) and the number of individual devices wired in parallel F.

5.24.2 ACLV Considerations


GLOBALFOUNDRIES recommends spreading capacitors uniformly across the chip to reduce their effect on
neighboring FET channel length. Grouping capacitors together away from critical circuits is ineffective. The
2
maximum area of any block of capacitors should be less than 5mm , and each block should be at least 2mm away
from the next block to minimize the effect.

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5.24.3 Fuse Considerations


An NFET in n-well capacitor used as a decoupling capacitor is usually designed with a fuse that will open when an
excessive amount of current is drawn. The fuse is comprised of minimum M1 line connected to polysilicon or
diffusion through a minimum CA. It is designed to blow when, due to a defective capacitor, a current of about
20-30 mA passes through it. I the fuse does not open, electormigration will open it long before other lines I the
power distribution network are affected.
The following fuse design guidelines are preliminary and subject to change:
Use a minimum-width M1 line, preferably at least 50 m long.
Do not place M1 wiring and active FETs within 2.25 m of the fuse.
Make sure the long arm of the narrow M1 line connects to VDD: current must pass from the M1 line into the
PC shape to open the fuse line.
Keep the width of the series FET as wide as possible (but compatible with the maximum tolerable current)
to minimize the probability of fuse failure.
As a good design practice, all wiring leading to or from decoupling capacitors should be designed to withstand
currents from two failing capacitors.

5.24.4 Yield and Reliability : Product Reliability Impact


Because decoupling capacitors are connected directly between V DD and ground nets on a chip, an oxide defect
can result in a direct short between VDD and ground. This defect is limited in theory only by series resistance in the
power and ground nets. These currents could lead to chip failures due to electromigration in the power and ground
wiring or through reduction in local VDD.
The decoupling capacitor evaluated includes an NFET control device or a resistor in series with the decoupling
capacitor. The NFET limits the leakage current values to 20-40 mA per defect. Therefore, a chip can be
insensitive to decoupling capacitor defects if the power nets are designed to tolerate the maximum dc current from
one or more defective capacitor cells. Special circuits that monitor the voltage on the drain of the series NFET can
be designed to disconnect the failed decoupling capacitor.

5.24.5 Use in Off-Chip Drivers


Dual power-supply circuits (for example, 1.0 V and 2.5 V) must adhere to certain precautions to stay within the
maximum oxide voltage of the 40LP technology (nominal 1.0 V). The decoupling capacitor should be connected
between 1.0 V and 2.5 V, and not between 2.5 V and ground. Chip power-on and power-off sequences must be
followed to prevent the oxide capacitors from being exposed to high voltages.
Note: If the decoupling capacitor is connected between the 1.0 V and 2.5 V power supplies due to the low
gate-voltage overdrive (2.5-1.0 V) of the control FET, then the series FET resistance will be higher than that for a
single power-supply case and cause degradation of the decoupling capacitor frequency response.

5.24.6 NCAP HSPICE Models


Compact models implemented for the HSPICE simulator are available for medium-and thick-oxide NCAP devices.

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5.25 PFET in P-Well Capacitor (PCAP)


Table 5-25. Electrical Parameters for the PFET in P-Well Capacitors (PCAPs)
Parameter

Definition

Units

Cacc_density

Total accumulation capacitance density

Device geometry

L (m) x W (m) x number of fingers

Tunability

Cacc / Cmin

fF/ m

Ratio

Igate_USL

Accumulation leakage USL

nA/ m

Igate_target

Accumulation leakage target

nA/ m

SGPCAP

EGPCAP

DGPCAP

13.7 15%

9.7 15%

6.1 15%

19.9 x 3.9 x 21

19.9 x 3.9 x 21

19.9 x 3.9 x 21

6.5

4.7

3.6

0.6

1.25e-5

Negligible

0.12

2.5e-6

Negligible

Notes:
1. Cacc density is measured in accumulation at Vdiffusion = 1.1V, 1.8 V and 2.5 V for SGPCAP, EGPCAP and
DGPCAP, respectively.
2. Cmin is measured in depletion at Vdiffusion = -0.6 V.
3. The electrical parameters for PCAPs shown here are provisional device specifications and will be updated as
required after qualification. Contact your GLOBALFOUNDRIES technical representative before incorporating
any PCAP into your design.
3. The total measured device capacitance reported here is a function of both area and fringe capacitance terms.
The nominal value equation for the capacitance of an NCAP at 25C is:

where,
CA
L
W
Ld
Wd

= capacitance (V) per area


= Ld - L
= W d - W
= Designed length
= Designed width
L, W are extracted from Table 5-6, Table 5-9 and Table 5-11 for SG, EG and DG NCAPs

respectively.
CL, CW and CF are fringe capacitance terms which are functions of the channel length (L), RX
width (W) and the number of individual devices wired in parallel F.

5.26 Electrical Fuse


This section describes rules for the electrically programmed fuse (eFUSE).

5.26.1 eFUSE Structure


The eFUSE structure is documented in Section 3.28 Fuse Design Rules. Contact with your GLOBALFOUNDRIES
technical representative for the details of the design kit.

5.26.2 Power Requirements


The electrically programmable fuse (eFUSE) is constructed on polysilicon (PC level) in the STI region. The
complete eFUSE structure on PC is un-doped. Each eFUSE is programmed by a programming transistor (see
figure below). During eFUSE programming, the polysilicon resistance increases significantly. Table Fuse
programming and sensing are sensitive to voltage drops on the power grids. Table below presents the electrical
parameters for the eFUSE.
Note : Refer to the eFUSE design kit available from your GLOBALFOUNDRIES technical representative. Typical
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per fuse yield above 99.999% is expected in mature hardware.

5.26.3 eFUSE Programming, Sensing and Yield


eFUSE devices are programmed and sensed with ground, VDD and VFSOURCE applied to the chip as described in
the eFUSE kit. These conditions are preliminary and might be modified. The expected values will be determined
in Table 5-25.
During fuse sense, the maximum voltage that can appear across the fuse is VDD (the chip supply voltage) and the
maximum current through the fuse is ISENSE. The maximum duration time of this sense current during a single
fuse sense must no more than TSENSE and the next sense can happen only after another TSENSE has passed
resulting in a maximum current-on duty cycle of 50%. The maximum number of sense cycles is NSENSE cycles
as shown in Table 5-25. Contact your GLOBALFOUNDRIES technical representative before using the eFUSE
outside these sense conditions.
Note: Refer to the eFUSE design kit available from your GLOBALFOUNDRIES technical representative. Typical
per fuse yield above 99.999% is expected in mature hardware. ECC is required for applications with a yield
requirement greater than 99.999%.
Figure 5-3. eFUSE Programming Transistor

Table 5-26. Electrical Parameters for the eFUSE


1

Value
Parameter

Symbol

Units
Minimum

Typical

Maximum

VFSOURCE

1.62

1.8

1.98

IPROG

8.5

10.5

mA

TPROG

0.0018

0.002

0.0022

ms

RT0

90

120

170

Programmed eFUSE resistance

RFINAL

3000

TBD

TBD

Fuse sense current

ISENSE

TBD

TBD

TBD

mA

Fuse sense time

TSENSE

TBD

TBD

TBD

ns

TBD

TBD

TBD

TBD

TBD

TBD

Programming supply voltage


Programming transistor current

Programming time
Intact fuse resistance (fuse only, without FET)

Fuse sense duty cycle


Fuse sense operations

NSENSE

1. TBD. For the most recent data, contact your GLOBALFOUNDRIES technical representative.
2. The fuse programming current requirement at the instant the programming transistor is turned on, before the fuse resistance rises.

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5.27 Wiring Resistance Models


5.27.1 Contact and Via Resistance
Note: In Table 5-27, use the Maximum Resistance for Multiple Vias values for more than one via in parallel, such
as redundant vias or via farms.
Table 5-27. Contact and Via Resistance

Level

Via Height (m)

Maximum Resistance
(/via)

Via Diameter
(at via bottom)
(m)

Minimum
Resistance
(/via)

Nominal
Resistance
(/via)

Multiple Vias

Single vias

TCR (1/C)

CA over RX

0.220 0.0440

0.040 0.010

30

50

95

70

0.0023

CA over PC

0.120 0.0340

0.050 0.010

15

30

60

45

0.0023

Vx (V1 V6)

0.08000.0301

0.064 0.0159

1.5

4.32

7.15

12.00

0.00065

Jx (J0J3)

0.250 0.0863

0.126 0.0364

0.50

1.85

3.27

5.00

0.00081

Wx (WT, WA, WB,


WD, WE)

0.215 0.0674

0.135 0.0390

0.50

1.72

3.00

5.00

0.00084

OT

0.550 0.2076

0.324 0.0842

0.15

0.35

0.55

0.90

0.00135

GM

0.550 0.2022

0.324 0.0867

0.15

0.35

0.55

0.90

0.00135

JR

0.550 0.2022

0.324 0.0867

0.15

0.35

0.55

0.90

0.00135

VV

0.750 0.1008

2.700 0.225

0.015

0.06

0.24

0.24

0.00385

1. Via height physical dimension.

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5.27.2 Sheet Resistance and Film Thickness


Tables 5-28 and table 5-30 presents front-end-of-line (FEOL) and back-end-of-line (BEOL) sheet resistances and
thicknesses at 25C, respectively.
Table 5-28. FEOL Sheet Resistance and Film Thickness
Level

W min (m)

Sheet Resistance
(/sq.)

Thickness (m)

0.100.12

TCR (%/C)

11 +14 / -6

N+ diffusion bounded by PC and isolation

0.055

0.32

> 0.12

10 +6 / -5

0.100.12

15 +15 / -10

P+ diffusion bounded by PC and isolation

0.055

0.34

> 0.12

15 +15 / -10

0.100.15

15 +20 / -8

N+ diffusion bounded by PC

0.035

0.32

> 0.15

15 +10 / -8

0.100.15

50 +50 / -43

P+ diffusion bounded by PC

0.035

0.34

> 0.15

15 +10 / -8

0.070.09

11 +9 / -6

N+ diffusion bounded by isolation

0.055

0.32

> 0.09

12 +8 / -7

0.070.09

8 +7 / -3

P+ diffusion bounded by isolation

0.055

0.34

> 0.09

12 +8 / -7

0.040.56

11 +11 / -6

N+ PC

0.32

> 0.56

11 5

0.040.56

11 +11 / -6

P+ PC

0.32

> 0.56

11 5

Table 5-29. Resistance of Minimum Width, Minimum Space Wires at 25C

Metal Level

Wire
Resistance
per Unit
Length
(/m)

Wire Resistance
Tolerance 3 Limits
(/m)
Lower
Upper
Limit
Limit

Pre shrink
Min width

Post shrink
Min width

Wire Resistance
per Unit Length
(/SQ)

Wire Resistance Tolerance


3 Limits (/SQ)
Lower Limit
(/sq)

Upper Limit
(/sq)

M1

4.89

3.71

7.22

0.07

0.063

0.3081

0.2337

0.4549

Mx (x = 2 - 8)

4.58

3.44

6.86

0.07

0.063

0.2885

0.2167

0.4322

Lx (x = 1- 4)

0.985

0.661

1.930

0.14

0.126

0.1241

0.0833

0.2432

Bx (x = A, B,
D, E, or G)

0.483

0.383

0.653

0.14

0.126

0.0609

0.0483

0.0823

FA, FB

0.0609

0.0489

0.0808

0.4

0.36

0.0219

0.0176

0.0291

LB

0.00623

0.00502

0.00745

1.8

0.0112

0.0090

0.0134

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Table 5-30. BEOL Sheet Resistance and Film Thickness

Minimum Line
Width and
Tolerance (m)

Nominal Metal
Thickness (T)
and Tolerance
(m)

Tel
(m)

Bulk
Resis
tivity,
0
(-c
m)

-0.007

0.0630 0.0097

0.130 0.0218

-0.0120

1.80

0.039

0.12

0.30

86.0

0.00237

-0.0075

0.0640 0.0092

0.14 0.0269

-0.0150

1.80

0.039

0.12

0.30

86.0

0.00235

Bx (x = A,
B)

0.0135

-0.01

0.1530 0.0265

0.365 0.0416

-0.025

1.80

0.039

0.12

0.30

88.0

0.00307

Lx (x = 1
4)

-0.014

0.1260 0.0253

0.255 0.0884

-0.015

1.80

0.039

0.12

0.30

86.0

0.00288

FA, FB

0.036

-0.02

0.4320 0.0594

0.850 0.1495

-0.040

1.80

0.039

0.12

0.30

88.0

0.00348

LB

1.800 0.1800

2.80 0.27

-0.1

3.00

100

0.00385

Level

Wphys
per
Edge
(m)

Wel
per
Edge
(m)

M11

Mx (x =
2 8)

Electron
Mean
Free
Path,
(m)

Surface
Scatteri
ng
Coeffici
ent (p)

Grain
Scatteri
ng
Parame
ter (R)

Sidewa
ll angle

(degre
es)

TCR (for
minimum
line)
(1/C)

Line resistance can be calculated as:

The parameters 0, , p, R, T, Tel, Wphys, Wel, and for each metal level are given in Table 5-30.
The sidewall angle correction to Weff [the term - (Tel / tan)] is a net positive correction to the line width because
the electrical thickness bias Tel is a negative number.
WOPC for M1 and Mx (x = 2-6) is given in Table 5-31. These values are given per edge, so choose an entry from
the table for WOPC,left and again for WOPC,right.

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Table 5-31. WOPC


Line Width (m)
Space
TBD

TBD

TBD

TBD

s 0.120

TBD

TBD

TBD

TBD

0.105 s < 0.120

TBD

TBD

TBD

TBD

s < 0.105

TBD

TBD

TBD

TBD

5.27.2.1 Corrections for Systematic Variation in Line Width and Line Height
M1 and Mx metal levels and the 2x metal levels in an ultra low-k dielectric exhibit significant systematic variation in
metal line width and line thickness as a function of line width. The following corrections can be applied to line widths
and line heights to increase the accuracy of resistance and capacitance extraction.
Table 5-32. Systematic Variation Correction Parameters
Parameter

M1

Mx

2x in Ultralow-k

2x TEOS/
FTEOS

6x TEOS/
FTEOS

Reactive ion etch (RIE) lag constant


(Lag-max)

0.015

0.015

0.025

RIE lag scaling (Lscale)

0.126

0.128

0.252

0.306

0.864

RIE bias constant (Bias-max)

0.02

0.021

0.042

RIE bias scaling (Bscale)

0.126

0.128

0.252

0.306

0.864

On-Wafer Line Width Correction As a Function of Design Line Width (Etch Bias)

where Wmin is the minimum line width (design rule value) for the relevant metal level, and Bias-max and Bscale are
the values listed in Table 5-32.
That is, the corrected line width equals:

On-Wafer Line Thickness Correction As a Function of Design Line Width (RIE Lag)
Line-height corrections are added to the bottom of M1, Mx, and ultra low-k 2x metal levels (the top of Mx remains
unchanged). Corresponding corrections should be made to CA, V(x1), and B(x1) via heights for capacitance
extraction.

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That is, the corrected line height (thickness) equals:

where T is the relevant metal level thickness listed in Table 5-30, and Lag-max and Lscale are the values listed in
Table 5-32.
Line resistance can then be calculated as:

where corr is calculated with the line width Wcorr and with the thickness Tcorr.

5.28 Wiring Capacitance Models


5.28.1 Parameters for Capacitance Calculation
Actual wiring capacitance is the sum of four capacitance components: C up, Cdown, Cright, and Cleft. Each
component can be calculated as follows: calculate an initial value for each component by assuming that the
surrounding dielectric medium is uniform and has a relative dielectric constant equal to one. This calculation can be
done using an analytical formula or a two-dimensional simulation tool. The final value for each component can then
be obtained by multiplying the initial value by the corresponding effective dielectric constant given in Table 5-32.
For calculating Cup and Cdown, subtract the physical width bias from the drawn width.
Accurate calculations of capacitance with closely spaced electrodes require two- or three-dimensional simulation.
Simulate structures, such as bit lines, in which accurate prediction of capacitance is critical.
Catastrophic OPC can add a physical (on-wafer) bias to a metal line in some circumstances. This physical bias
should be taken into account when extracting or modeling capacitance (see the WOPC definition).
On-Wafer Via Thickness Correction As a Function of Design Line Width (RIE Lag)
Line-height corrections are added to the bottom of all metal levels (the top of the metal remains unchanged).
Corresponding corrections should be made to all via heights for capacitance extraction.
For all metal/via levels, where WDes, Wopc, and Wphy refer to the line width, the via-height correction is defined
by:

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That is, the corrected via height (thickness) equals:

where H is the via height listed in Table 5-22.

5.28.2 Wiring Capacitance Tracking


The tracking percentages listed below are for identical metal lines less than 1500 m long and less than 500 m
apart on the same wiring level:

M1 and Mx tracking is 5%
Mx_2(Bx) tracking is 10%

In addition, the lines must be symmetrical with respect to conductors crossing above and below and with respect to
adjacent lines on the same level. The lines are assumed to be minimum design width.

5.28.3 Quick Look-Up Wiring Capacitances (3D Model)


5.28.3.1 Interlevel Capacitance
The wiring capacitances for various design levels assume wiring at minimum pitch, at the same level, and with
100% metal coverage above and below. All parameters are assumed to be nominal. All values in the table are for
wafer dimensions.

Figure 5-4. Capacitance Calculation Model

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Table 5-33. Interlevel Capacitances


Wiring Levels
M1 over PC
under M2
(NESTED)
M2 over M1
under M3
(NESTED)
M3 over M2
under M4
(NESTED)
M4 over M3
under M5
(NESTED)
M5 over M4
under M6
(NESTED)

w=0.063, t=0.13,
sl=sr=0.063,
ha=0.080, hb=0.120,
angle=86
w=0.064, t= 0.140,
sl=sr=0.063
ha=0.080, hb=0. 080,
angle=86
w=0.064, t= 0.140,
sl=sr=0.063,
ha=0.080, hb=0. 080,
angle=86
w=0.064, t= 0.140,
sl=sr=0.063,
ha=0.080, hb=0. 080,
angle=86
w=0.064, t= 0.140,
sl=sr=0.063,
ha=0.080, hb=0. 080,
angle=86

Drawn

epup

epdown

epleft

C_up

C_down

C_left

C_total
(fF/m)

w = 0.07
s = 0.07

3.30

4.53

3.39

0.0470

0.0500

0.0750

0.248

w = 0.07
s = 0.07

3.68

3.68

2.75

0.0523

0.0518

0.0684

0.2410

w = 0.07
s = 0.07

3.68

3.68

2.75

0.0523

0.0518

0.0684

0.2410

w = 0.07
s = 0.07

3.68

3.68

2.75

0.0523

0.0518

0.0684

0.2410

w = 0.07
s = 0.07

3.68

3.68

2.75

0.0523

0.0518

0.0684

0.2410

M5 over M4
under FA
(NESTED)

w=0.064, t= 0.140,
sl=sr=0.063, ha=0.55,
hb=0. 080, angle=86

w = 0.07
s = 0.07

4.15

3.68

2.75

0.0113

0.0552

0.0844

0.2352

M5 over M4
under BA
(NESTED)

w=0.064, t= 0.140,
sl=sr=0.063,
ha=0.215, hb=0. 080,
angle=86

w = 0.07
s = 0.07

4.34

3.68

2.75

0.0233

0.0528

0.0800

0.2361

M6 over M5
under FA
(NESTED)

w=0.064, t= 0.140,
sl=sr=0.063, ha=0.55,
hb=0. 080, angle=86

w = 0.07
s = 0.07

4.15

3.68

2.75

0.0113

0.0552

0.0844

0.2352

M6 over M5
under L1
(NESTED)

w=0.064, t= 0.140,
sl=sr=0.063,
ha=0.25, hb=0. 080,
angle=86

w = 0.07
s = 0.07

3.47

3.68

2.75

0.0161

0.0530

0.0813

0.2317

FA over M5
under FB
(NESTED)

w=0.432, t=0.85,
sl=sr=0.288, ha=0.55,
hb=0.55, angle=88

w = 0.48
s = 0.32

4.12

4.11

3.83

0.0471

0.0468

0.1207

0.3354

FB over FA
under LB
(NESTED)

w=0.432, t=0.85,
sl=sr=0.288, ha=0.75,
hb=0.55, angle=88

w = 0.48
s = 0.32

4.40

4.11

4.00

0.0410

0.0469

0.1273

0.3427

L1 over M6
under FA
(NESTED)

w=0.126, t=0.255,
sl=sr=0.126, ha=0.55,
hb=0.25, angle=86

w = 0.14
s = 0.14

3.98

3.16

3.26

0.0184

0.0308

0.0817

0.2126

FA over L1
under LB
(NESTED)

w=0.432, t=0.85,
sl=sr=0.288, ha=0.75,
hb=0.55, angle=88

w = 0.48
s = 0.32

4.40

3.99

4.00

0.0410

0.0469

0.1273

0.3427

FA over M5
under LB
(NESTED)

w=0.432, t=0.85,
sl=sr=0.288, ha=0.75,
hb=0.55, angle=88

w = 0.48
s = 0.32

4.40

4.11

4.00

0.0231

0.0455

0.1335

0.3317

BA over M5
under LB
(NESTED)

w=0.153, t=0.365,
sl=sr=0.099, ha=0.75,
hb=0.215, angle=88

w = 0.17
s = 0.11

4.40

4.27

3.98

0.0172

0.0464

0.1602

0.3839

BA over M6
under LB
(NESTED)

w=0.153, t=0.365,
sl=sr=0.099, ha=0.75,
hb=0.215, angle=88

w = 0.17
s = 0.11

4.40

4.27

3.98

0.0172

0.0464

0.1602

0.3839

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5.28.3.2 Resistance and Capacitance Extraction Parameters


The polysilicon and diffusion area dimensions used to calculate resistance and capacitance. In the third column,
Wphys is calculated as follows:

Figure 5-5 on illustrates the design and cross section related to the PC and RX dimensions.
Figure 5-5. Extraction Parameters

5.28.4 CA-to-PC Capacitance


Capacitance is sensitive to alignment, which becomes important at (CA minimum space to PC).

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5.29 Matching Characteristics


Device mismatch describes the differences in electrical behavior between otherwise identical devices. There
are two types of device mismatch:

Short-distance mismatch, or pair mismatch, is a mismatch between neighboring devices within 1 m from each
other. The mechanisms responsible for pair mismatch are mainly independent random variations of physical
properties, such as implant nonuniformities, Leff and W eff; gate-oxide thickness; and a finite number of dopant
atoms. Pair mismatch is characterized in terms of the differences of the measured parameter p (for example,
Vt, K / K, and R) between the neighboring devices.

Long-distance mismatch is observed in devices with distances greater than 100 m between each other. The
most prominent mechanisms responsible for long-distance mismatch are edge effects caused by asymmetrical
topology; striation effects indicating periodic spatial variation of the measured parameter; and gradient effects
describing variations across a wafer, which have long periods compared to a chip. Long-distance mismatch is
characterized in terms of absolute values of parameters dependent on the on-chip device location compared to
the chip mean value of the parameter.

5.29.1 Recommended Design Rules


Some device matching recommendations cannot be implemented in the minimum design rules (hard rules) verified
by design rule checking. For analog designs where good matching behavior between FETs or passive components
is important, the recommended rules (soft rules) in Section 4.1 Recommended Nonminimum Design Rules for
Yield Enhancement result in better matching.

5.29.2 Recommended Guidelines


1. Use the square-root area model for transistors, resistors, and capacitors. If a matching constant is not yet
available for the considered technology, use the matching constant from the previous technology generation. Note
that large devices have better matching results than small devices.
2. Do not match transistors, resistors, or capacitors with a different geometry or with different geometrical shapes
of equal area.
3. Orient the matched transistors, resistors, and capacitors in either the x- or y-direction. Do not mix horizontal and
vertical lines, especially for narrow devices.
4. Use common centroid (nested or interdigitated) design structures (see Figure 5-6) rather than stretched or
isolated design structures for better matching results. Common centroid structures minimize gradient effects

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Figure 5-6. Common Centroid

5. Do not match isolated devices (for example, PC or RX lines without a neighboring PC or RX line within 1 m) to
nested narrow devices.
6. Ensure that the current flows through the devices in the same direction.
7. Avoid floating gates by supplying the M1 connected to PC with tie-down diodes. Omitting the tie-down diodes
generates threshold voltage shifts due to the antenna effect.
8. Use the same PC to CA spacing and number of contacts for matched devices.
9. Use similar wiring connections to prevent variations in connection resistance.
10. Use a BFMOAT structure for polysilicon resistors to prevent noise coupling through the substrate.
11. Use square shapes for top and bottom capacitor plates to minimize the influence of fringing capacitance.
However, for RF applications, an asymmetric width-to-length ratio of top to bottom plates can result in a higher
Q-factor.
12. Use bipolar transistors rather than CMOS transistors for better mismatch behavior; the bipolar matching
constants are typically an order of magnitude lower than their CMOS counterparts.
13. Place matched devices on a common isothermal contour to prevent mismatch due to temperature differences
caused by thermal sources on the chip.
14. Ensure equal metal coverage of the matched pair with respect to metal lines by either:
a. avoiding running metal lines over the matched pair or
b. guaranteeing that both transistors are identically covered with metal.
15. Ensure equal metal coverage of the matched pair with respect to fill structures by avoiding accidental
placement of fill structures in metal levels over the matched pair.
16. Keep the metal antenna ratio to a minimum, preferably tying the gates to diodes at M1. If metal antennas occur
at M1, make the ratio small and equivalent for the matched devices, and tie the gates to diffusions at M2.
17. Ensure that metal wiring over the gates for each metal level covers the same percentage of the device active
area (PC over RX) on matched devices.
18. Ensure that matched devices are identical with respect to placement of the n-well relative to the source and
drain to prevent introducing additional threshold voltage mismatch due to a different distance to the n-well edge.
19. For matching device fingers in multifingered device structures, do not build devices by stacking numerous
polysilicon gates in RX (active area shape); the devices adjacent to the RX edges parallel to the gates do not have
good matching with devices in the interior of the active area. This mismatch is due to the modification of device
characteristics that results from mechanical stress created by the isolation oxide.

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5.29.3 Transistor Mismatch


5.29.3.1 Mismatch of Neighboring Devices (Pair Mismatch)
The widely accepted mismatch models (1 value) for threshold voltage, Vt, and transconductance, K, are inversely
proportional to device area:

where:
Mvta = matching coefficient proportional to the oxide thickness and number of doping atoms in the
depletion layer
W = device width
L = device length
n = power of area dependency
Mka = matching coefficient
In modeling, n is set to 0.5 and the device area is calculated with a drawn width, W, and an effective channel length,
Lp = Ldrawn Lnominal, where Lnominal is the nominal L listed in the table of electrical parameters for each device.
In simulation, the 1 value of the threshold voltage mismatch of a transistor pair, V is characterized or modeled
using the equation above. The 1 value of the current mismatch of a transistor pair is then determined by the
threshold voltage mismatch and the current factor mismatch.
t

The 1 value for single transistors, opposed to paired transistors, must be considered by taking into account
the factor 2 . The threshold voltage variation of a single transistor is given by:

and the variation of the mobility of a single transistor is described by the absolute value of the current factor
variation:

An analytical expression derived by Mizuno and others predicts a linear dependence of the standard variation of
the threshold voltage, V on the gate-oxide thickness, Tox, and a weak dependence of the channel doping, NA. This
physical model is based on the assumption of homogeneous channel doping:
t

5.29.3.2 Threshold Voltage and Current Mismatch Coefficients for Separations Less than
200 m
The standard deviation of the distribution of the extracted threshold voltage (Vt) and transconductance (K)
mismatch is implemented in the compact device models as:

1.

T. Mizuno, J. Okamura, A. Toriumi, Experimental study of threshold voltage fluctuation due to statistical variation of channel
dopant number in MOSFETs, IEEE Trans. Electron Devices, Vol. 41, p. 2216, 1994

where:
Mvta, Mvtal,
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= fitting coefficients that differ for each device type

Mka Mkal

W = drawn device width


Lp = Ldrawn Lnominal
The Mvtal and Mkal coefficients indicate that, as channel length decreases, matching degrades faster than the inverse
square root of the area.
The transistor matching characterization values in Table 5-34 are hardware-based with linear fitting of the
measured data. These are not modeling coefficients.
Table 5-34. Transistor Matching Characterization
Device

Avtlin (mV-m)

Aldlin (%-m)

Avtsat (mV-m)

Aldsat (%-m)

1.1V Low-Vt SG NMOS

3.95

0.76

4.54

0.75

1.1V Low-Vt SG PMOS

2.95

0.57

3.56

0.72

1.1V Regular-Vt SG NMOS

4.33

1.05

4.96

0.96

1.1V Regular-Vt SG PMOS

3.12

0.76

3.69

0.85

1.1V High-Vt SG NMOS

4.69

1.08

5.04

1.18

1.1V High-Vt SG PMOS

3.05

0.73

3.39

0.91

1.1V Zero-Vt SG NMOS

7.72

0.87

10.38

1.8V EG I/O NMOS

6.25

0.64

7.19

0.70

1.8V EG I/O PMOS

3.77

0.48

4.65

0.60

1.8V EG I/O Zero-Vt NMOS

8.57

0.37

10.82

2.5V DG I/O NMOS

11.38

0.86

11.71

0.78

2.5V DG I/O PMOS

6.41

0.90

6.95

1.11

2.5V DG I/O Zero-Vt NMOS

3.16

4.97

Estimate the difference in current between a matched pair of devices in saturation by:

The devices which were characterized to develop the models for current and Vt matching had no M1 or M2 wiring
placed over the gates, were very far from well boundaries, and were all connected to diodes at M1. There is some
data to indicate that systematic device mismatch problems can occur if the guidelines in Section 5.27.2
Recommended Guidelines on page 215 are not followed for layout of circuits where device matching is critical.
At channel lengths below the minimum nominal, the mismatch becomes underestimated by the equations in this
section. For back biases other than those given in the table 5-35, the coefficients can be obtained by linear
interpolation.
To calculate the Vt mismatch distribution at end of life, see Section 6.3.7 Using Device Degradation Data. Note also
that mismatch parameters could be altered drastically by stress build up in packaging.
A quick look-up table for the 1 threshold voltage (Vt) and Gm mismatch distribution values for regular- Vt FETs is
given in Table 5-35.

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Table 5-35. Regular FET 1 Threshold Voltage and Gm Mismatch Distribution


Design Width, W (M)

Design Length, L (M)

Regular NFET
1 Vto (mV)

Regular PFET

1 Gm (%)

1 Vto (mV)

22.62

45.47

19.15

43.84

16.35

35.91

12.33

17.38

5.95

8.02

b
v
v
b
v
b

1 Gm (%)

b
v
v
b
v
b

0.15

0.04

61.70

9.72

0.2

0.04

51.98

0.3

0.04

39.59

0.04

28.83

0.04

18.81

0.15

0.12

32.36

13.67

24.83

6.63

0.3

0.12

26.03

12.01

17.70

4.66

0.12

21.45

7.24

9.10

2.50

0.12

6.98

2.81

4.30

1.28

0.5

12.08

7.15

6.94

2.50

6.53

2.45

3.06

0.92

3.11

1.49

3.34

0.47

8.79
7.74
5.02
2.50

5.29.4 N-Well Proximity Effect


Table 5-36 reports Vtsat shifts caused by the NW proximity effect. For the thin-oxide a device with W / L = 0.3 m /
0.04 m is used; for the medium-oxide EG device W / L = 0.4 m / 0.15 m is used & for the thick-oxide DG device
W / L = 0.4 m / 0.27 m is used. The devices have a single NW edge close to the device, in the direction
perpendicular to the gate and at the NW to RX distance specified in the table.
Table 5-36. NW Proximity Effect
Delta Vt (mV)
Minimum Design Rule

1.5 x Minimum Design Rule

2.0 x Minimum Design Rule

80

120

160

Low-Vt (NFET / PFET)

17 / 14

17 / 16

17 / 17

Regular-Vt (NFET /
PFET)

17 / 13

17 / 15

17 / 16

High-Vt (NFET / PFET)

17 / 13

17 / 14

17 / 15

220

330

440

64 / 44

55 / 37

45 / 29

220

330

440

67 / 40

61 / 30

48 / 22

Device Type
NW to RX (nm)
Thin-oxide

NW to RX (nm)
Medium -oxide
High-speed I/O EG
(EG)
(NFET / PFET)
NW to RX (nm)
Thick-oxide
(DG)

Regular I/O DG (NFET /


PFET)

5.29.5 Resistors Mismatch


5.29.5.1 Pair Mismatch
Geometry Model
The standard deviation, of the relative resistance variation R R of a pair of directly neighboring resistors is
proportional to the inverse of the square root of the active device area WxL . R is the mean value of the resistance
of the considered neighboring resistors:
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is the matching constant for a pair of resistors.

Measurement Procedure
The matching behavior shows no bias dependence for typical analog bias conditions. The matching behavior is
extracted from measurements with a 100 mV voltage drop over the resistor under test.
Matching Constants
The constants listed in Table 5-37 correspond to a 1 standard variation. Matching constants of diffusion resistors
are yet to be defined.
Table 5-37. Resistor Pair Matching Constants
Resistor

Units

AR

% m

3.725

% m

1.203

% m

0.521

% m

0.315

% m

1.341

% m

1.519

N Polysilicon resistor (unsalicided)


P Polysilicon resistor (unsalicided)
N Diffusion resistor (unsalicided)
P Diffusion resistor (unsalicided)
N Polysilicon resistor (salicided)
P Polysilicon resistor (salicided)

Physical Model
An analytical expression has been derived that predicts the linear dependence of the standard variation of the
relative resistance variation R / R from the polysilicon grain size:

where denotes the ratio between the resistance part of the grain boundary to the total resistance of the grain.

5.29.6 Capacitors Mismatch


The mismatch of capacitors is described experimentally by an inverse square root area dependence with a small
offset BC C which is possibly due to variations of the oxide thickness:

where AC C is the matching constant, and the area is determined by the designed length and width

5.29.7 Parametric Uncertainty for Small-Geometry Devices


There is substantial uncertainty in device parameters that is inherently associated with device size. There are
dimensional variations (in length, width, and oxide thickness) that contribute to the tolerance, but the dominant
source of variation in minimum-geometry devices is related to the device area and the statistical fluctuation in
doping. This phenomenon is often characterized by measuring "mismatch", but it is actually an uncertainty inherent
to small dimensions.

5.29.7.1 SRAM Cell Analysis


SRAM standby leakage current. The leakage current of the cell consists of subthreshold current of one pullup
PFET, one pulldown NFET, and one transfer NFET, as well as junction leakage, gate leakage, and gate induced
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drain leakage (GIDL) components. The effective total subthreshold leakage of an ensemble of devices is
effectively larger than that of the median device. The cell leakage calculation must take into account the distribution
of threshold voltages that occur with some frequency in the array.
SRAM cell stability. The mismatch between the pulldown and the word-line device is dominated by the statistical
sampling effect.
SRAM cell writability/readability. The current-handling capability of the slowest worst-case cell depends strongly on
the value of the threshold voltage.

5.29.7.2 Low-Power Logic Circuits


Devices of width less than 0.5 m have an increased Vt tolerance due to the sampling effect, and devices of width
less than 0.5 m are significantly affected. Standby current and timing should be assessed using the statistical
sampling model

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6. Reliability Design Rules and Model


Available FEOL models were derived using GLOBALFOUNDRIES F7 40LP Bulk process L1 exit reliability
qualification data.
Note: BEOL model based reliability information would be available in 4Q10. SER Reliability Physical test data
update would be available by end of 1Q11

6.1 Guidelines for Optimal Reliability


Note: The following guidelines do not replace the need for a thorough study of all the rules in this manual. They are
intended to provide a brief summary of design practices that result in a more robust final product.
Recommendations:

Stay within the specified limits of the power supply: V DD


is 1.1 0.11 V for thin-oxide devices, 1.8 0.18 V
for medium-oxide devices and 2.5 0.25 V for thick-oxide devices. Uses above or below these voltage ranges
are not supported in this design manual. For voltage applications outside of these ranges, contact your
GLOBALFOUNDRIES technical representative for further discussion.

Use power supplies with tighter tolerance when possible. Most reliability mechanisms are strongly voltage
dependent.

Stay within the specified temperature range: -40C to 125C.

Use minimum design dimensions only when necessary.

Use minimum device lengths only when necessary. Many reliability mechanisms are strongly length
dependent.

Design all circuits to function at the worst-case design burn-in conditions.

Review wearout mechanism design rules:

max

Hot carriers

Critical circuits are those with highly loaded devices, high duty factors, critical matching, analog
function, or bidirectional operation.

Minimize switching times and currents in circuits.

Electromigration

Critical circuits are those with highly loaded devices or high duty factors.

Position contacts to polysilicon between RX shapes (shallow trench isolation [STI]).

Include a chip guard ring around the entire chip.

Avoid large areas of thin-oxide capacitors. Such areas increase the likelihood of defect-related chip
failure.

Use dc standby current screens to detect defects. Chips should be designed with minimal dc standby current.
If dc current is required for a particular application, then that current should be brought to a separate pad.

If device matching is a concern, place devices in close proximity with the same orientation. Allow for at least the
minimum expected mismatch specified in section 6.3.5

Vertical interconnects are mechanical and electrical weak points. Maximize areas of vertical interconnects by
using as much contact and via stud area as possible and by overlapping contacts and vias with as much metal
as possible.

Review all device uses not expressly permitted in this manual with your GLOBALFOUNDRIES technical
representative.

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6.2 Reliability Screening


Four reliability screens require the designers attention. All systems do not require optimal reliability and need not
pass all four screens. The four screens are:

Dynamic voltage screen (DVS)


Enhanced voltage screen (EVS)
Supply current (IDD) screen
Burn-in (100% of production) screens of the final packaged product

To achieve minimum reliability confidence, either the first three screens or the last screen must be applied. For
maximum reliability, all four screens must be applied.

6.2.1 Burn-In
All circuits must be designed to function at the worst-case design burn-in conditions. GLOBALFOUNDRIES
nominal
requirement for burn-in conditions is 1.4 times VDD
and 140C (Tjstress). Therefore, the following conditions
should be used to assess functionality at burn-in:

VDD is 1.54V for 1.1 V circuits, 1.98 V for 1.8V circuits, 2.75 V for 2.5 V circuits and 3.63 V for 3.3 V circuits.

Temperature is 140C (Tjstress).

Worst-case Lp or Leff.

Tcycle is 200500 ns.

Trise,fall is 60 ns.

Other variables are at nominal conditions.

Any deviation from these conditions must be discussed with your GLOBALFOUNDRIES technical representative.
The standard devices in I/O circuits that drive and receive voltages higher than 1.8 V cannot have more than
2.16 V (Vmax+10%) across their drain-to-source terminals during burn-in. The thick-oxide devices in I/O circuits
that drive and receive voltages higher than 2.5 V cannot have more than 3.0 V across their drain-to-source
terminals during burn-in. Similarly, the thick-oxide devices in I/O circuits that drive and receive voltages higher than
3.3 V cannot have more than 3.96 V across their drain-to-source terminals during burn-in.
Burn-in function at the indicated elevated conditions requires a robust voltage distribution (including n-well and
substrate contacts) and patterns that prevent significant amounts of simultaneous switching.
Temperature control becomes a problem when the integrated circuits supply too much heat compared to the oven.
Power dissipation over 3 W (average) might need to be corrected with special burn-in modes.

6.2.2 Wafer Screening


DVS, EVS, and IDD screens are typically executed as part of the wafer test activities. Support for the wafer
screening options must be negotiated with GLOBALFOUNDRIES through your GLOBALFOUNDRIES technical
representative. The DVS stresses by writing with high pattern coverage when the supply voltage is 1.4 to 1.7 VDD
(maximum, actual based on product testing). EVS bumps the supply voltage to 1.7 to 2.0 VDD (maximum, actual
based on product testing) at the completion of each DVS pattern. Supply current (I DD) is used as the main indicator
of DVS/EVS failure along with a loss of functionality.
EVS is extremely effective with preburn-in reliability shorting-mode defects. The normally dominant shorting mode
is reduced to a minority compared to open mode. Additional defect reduction is afforded because highly defective
wafers can be identified and scrapped. In many cases, EVS has been successfully substituted for burn-in.

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6.2.2.1 Wafer Screening Design Practices


Adherence to the following design practices for voltage screening is highly recommended. EVS does not restrict
channel length.

Static data integrity with VDD/inputs at 2 VDD (maximum target, actual based on product testing).

Dynamic functionality with VDD/inputs at 1.7 VDD (maximum target, actual based on product testing);
Tcycle is 2001000 ns.

Experience has shown that products properly designed for the burn-in conditions above meet the
static/dynamic requirements for EVS/DVS.

Supply low IDD states with good node toggle and without dc current. Every potential dc path from V DD to ground
should be blocked by at least one NFET or PFET with a VGS equal to 0. Supply true/complement states for
embedded SRAM and all latches.

Pass-gate circuitry design must satisfy this dc path blockage requirement. For example, the design must be a
pass gate feeding a latch or a fully complementary pass gate design, or have an NFET pass-gate pullup (half
latch).

Grounded PFET circuitry design must also be dc free. For example, there should be a test pin to undo
grounding of PFETs and an extra NFET pulldown with a gate tied to the same test pin; thus, with the test pin
high, the PFET is off and the NFET ties the potentially floating node to ground.

The design of the multiplexer circuitry must be free of dc paths and floating nodes (indeterminate states).

Input and I/O circuitry must be designed so that input highs no higher than VDD can be received without dc
paths during EVS where VDD is projected at 2.4 V.

As with burn-in, DVS requires functionality at accelerated conditions of voltage and temperature. Whoever is
responsible for wafer test needs to verify this functionality on the earliest available hardware. With products
becoming ever more complex, the conditions for this early assessment should be discussed with your
GlobalFounries technical representative.

6.3 Front-End-of-Line (FEOL) Reliability Design Rules


6.3.1 Hot Carrier Effects
Note: Hot carrier injection can have a significant impact on circuit performance and functionality. It is imperative
that circuit designers carefully review their designs for hot carrier degradation. Cumulative degradation and
process variation must be taken into account for both burn-in and field operation.
Minimum Leff typically produces the largest hot carrier shifts but might not be the most sensitive condition for circuit
operation and performance. For example, chips with a longer Leff that just meet time-zero performance targets
might degrade less than minimum Leff chips. With little or no performance margin, these chips are more likely to fail
than chips with a shorter Leff, large degradation, and large time-zero performance margin.

6.3.2 Hot Carrier Mechanism


Hot carriers are holes or electrons that have been accelerated to a high energy by local electric fields, as well as a
number of secondary mechanisms. If such a carrier has kinetic energy in excess of the silicon-insulator barrier
height, it might surmount the barrier and enter the insulator. Once in the insulator, the electron or hole can become
trapped. High energy carriers can also produce interface states. The accumulation of trapped charges causes a
shift in the threshold voltage (Vt) of the device, and the accumulation of interface states can reduce device drain
current, degrade subthreshold slope, and increase device leakage.
Hot carriers are categorized into two types, depending on the origin of the carrier: channel hot carriers (CHC) and
substrate hot carriers (SHC). Channel hot carriers are further broken down into conducting (gate voltage >
threshold voltage) and nonconducting (gate voltage ~ 0).
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The NFET channel conducting hot carrier effect is dominated by the generation of interface states. Significant
degradation occurs when the gate voltage is above Vt and VDS is high. The PFET channel conducting hot carrier
effect is due to a mixture of interface state generation and charge trapping, and is more complex than NFET
behavior. Significant degradation occurs when the gate voltage is between V t and VDS and when VDS is high.
Device degradation is characterized by both an increase in threshold voltage and a reduction in device drain
current over time. The device damage is localized near the drain, resulting in asymmetrical post-stress device
characteristics.
Care must be taken when operating devices with persistent drain currents. In these cases, V DS must be kept low or
the associated circuits must be designed to tolerate significant degradation.

6.3.2.1 Hot Carrier Device Concerns


The following specific NFET uses must be examined in detail:

Burn-in conditions

Bidirectional devices (stressing a device in both directions is more severe than twice the stress time in one
direction)

DC current flow

Heavily loaded circuits such as off-chip drivers (OCDs) and clock drivers

Circuits such as OCDs that can experience voltage overshoots or undershoots

Mixed-voltage interface circuits or any circuit using greater than 2.4 V for thin-oxide devices, 3.6 V for medium
oxide (EG) devices or 5 V for thick-oxide (DG) devices

Circuits with long rise and/or fall times such as OCDs

Circuits where Vt or ID matching is critical

6.3.2.2 Conducting Hot Carriers: N-Channel Devices


The followings are the models of the conducting NFET channel hot carrier effect. The models were derived at worst
dc case (VGS ~ VDS). This is the maximum dc degradation point for for all oxide devices for all Leff (lower or higher
than nominal) values. However, in actual use, the degradation peaks near VGS ~ VDS / 2, even for low Leff because
the dependence of the degradation on VGS is not very strong for low Leff. When VGS equals VDS, VDS is normally
significantly lower.
This model does not include saturation effects, which tend to reduce the degradation above 50%. Insignificant W
dependency was observed in device degradation perspective. For For temperatures other than 125C, corrections
must be applied as indicated in the model. Bent gate devices do not exhibit significantly higher degradation
compared to straight gate devices.
Degradation Equation
The degradation in saturation current, Ion (@ Vds=Vgs=VDD), for the thin-oxide (SG), medium-oxide (EG) and
thick-oxide (DG) NFET devices is given by:
1.1V Thin-oxide (SG) RVT NFET:

Idsat (%) 8505.27 * L1.65 * exp(18.43 / VDS ) * exp(0.03 / KT ) * t 0.425


1.8V Medium-Oxide (EG) NFET:

Idsat (%) 311.14 * L5.02 * exp(35.71 / VDS ) * exp(0.0034 / KT ) * t 0.485


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Where:
L is the drawn channel length in um, VDS is the applied drain voltage in volt, K is the Boltzmans constant
(8.62E-05 eV/Kelvin), T is the temperature in Kelvin, t is the dc mean time in hours.
The model parameters are summarized in Table 6-1.
Table 6-1. NFET Conducting Hot Carrier Model Parameters

Devices

VDD [V]

Thin-oxide SG
NFET

1.1

Medium-oxide
EG NFET

1.8

Thick-oxide
DG NFET

2.5

Direction

A (mean)

VAF

Ea

8505.27

-1.65

-18.43

-0.03

0.425

311.14

-5.02

-35.71

0.0034

0.485

Target: Q410

Target: Q410

Target: Q410

Target: Q410

Target: Q410

Forward

Note: For the thin-oxide NFET, Ion degradation is calculated for the regular-Vt (RVT) device. The actual Ion shift is
slightly different for the high-Vt and low-Vt NFET devices.
Time Calculations
Hot carrier effects occur in NFET devices when VDS is close to VDD and appreciable ID is flowing. For typical CMOS
circuits, these conditions occur only during switching transients. In this case, equivalent stress time (t eq) can be
approximated by:

where:
tuse is the chip / circuit operating time in hrs and duty factor (Df) is a function of ITR, TTR and SF and can be
expressed as

where:
ITR = ratio of gate voltage rise time (1090%) to total cycle time
TTR = ratio of drain voltage fall time (1090%) to gate voltage rise time (1090%)
SF = switching factor (that is, the fraction of cycles in which the NFET switches on: rising input, falling
output)
tuse = actual use time in hours
Based on real silicon data, hot carrier duty factor as well as transition time / duration at different VDS are
demonstrated in below Table 6-2a and Table 6-2b.

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Table 6-2a. Thin-Oxide (SG) RVT NFET Hot Carrier Duty Factor

VDS [V]

DC teq
(T0.1)
[Yrs]

DC teq
(T50) [hrs]

tuse [Yrs]

Max. Permissible
Duty Factor
[=(T0.1/10)*100]

CLK time [ns]

Transition Time
[ps] (=D.
Factor*CLK time)

1.21

0.60

0.31

13721.17

10

6.01

60.10

1.23

0.34

0.31

7762.359

10

3.40

34.00

1.25

0.19

0.31

4358.399

10

1.91

19.09

1.28

0.08

0.31

1932.891

10

0.85

8.47

1.3

0.05

0.31

1147.753

10

0.50

5.03

Table 6-2b. Medium-Oxide (EG) NFET Hot Carrier Duty Factor

VDS [V]

DC teq
(T0.1)
[Yrs]

DC teq
(T50) [hrs]

tuse [Yrs]

Max. Permissible
Duty Factor
[=(T0.1/10)*100]

CLK time [ns]

Transition Time
[ps] (=D.
Factor*CLK time)

1.98

2.11

0.14

28488.03

10

21.10

211.00

1.46

0.14

19712.09

10

14.60

146.00

2.1

0.25

0.14

3375.359

10

2.50

25.00

2.2

0.05

0.14

675.0717

10

0.50

5.00

2.3

0.01

0.14

135.0143

10

0.10

1.00

Narrow Device Correction


Under the same stress environment, no significant difference was observed between narrow width (<0.7um) and
wide width (1um & above) device saturation current degradation. Therefore, no width correction is required.
Device Characteristics
The observed effect of hot carrier injection on an NFET device is dependent on the measurement conditions
applied after stress. Reverse mode refers to the situation where a device is measured with its source and drain
connections reversed relative to those during stress. Thus, the reverse saturation degradation is important when a
device is used bidirectionally, as in a pass gate. As of today, device characteristics based on reverse saturation
degradation is not available. Once data collection and characterization would complete, reliability performance
would be demonstrated in this section. Pls contact with your GLOBALFOUNDRIES representative for the
availability of the DM update.
Thin-Oxide Device Example
An inverter circuit is operated for 100 000 hours, where:
Input rise time = 100 ps
Output fall time = 200 ps
Cycle time = 1 ns
SF = 1/4
VDD = 1.21 V

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Lp = 0.0 4 m (nominal)
T0.1 @ 1.21V = 0.2Yrs (=teq)
T0.1 @ 1.21V=10Yrs
Df = 2%
F(TTR)=0.02/(0.1X0.25)=0.8 and Input/Output voltage transition time @ 1.21V = 20ps

Teq=0.2 Yrs meaning, for 10 Yrs of chip (circuit) operating time, equivalent hot carrier stress time would be
approximately 0.2 Yrs (for Idsat=10%).
Calculation of t0.1 / t50:
= 0.31 (based on actual data)
t0.1 = t50 * exp (-3.09*)

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6.3.2.3 Conducting Hot Carriers : P-Channel Devices


The PFET channel hot carrier effect causes interface state generation and charge trapping. Significant degradation
occurs when VGS approaches VDS. Device degradation reduces device drain current over time. The device damage
is localized near the drain, resulting in asymmetrical post-stress device characteristics.
The following is a model of the conducting PFET channel hot carrier effect.
Degradation Equation
The degradation in saturation current, Ion (@ Vds=Vgs=VDD), for the thin- and thick-oxide PFET device is given by:
-1.1 V Thin-Oxide (SG) RVT PFET:

Idsat (%) 1434.87 * L0.48 * exp(8.42 / VDS ) * exp(0.051 / KT ) * t 0.224


-1.8V Medium-Oxide (EG) PFET:

Idsat (%) 1667.89 * L1.76 * exp(20.55 / VDS ) * exp(0.0744 / KT ) * t 0.266

Where:
L is the drawn channel length in um, VDS is the applied drain voltage in volt, K is the Boltzmans constant
(8.62E-05 eV/Kelvin), T is the temperature in Kelvin, t is the dc mean time in hours.
The model parameters are summarized in Table 6-3.
Table 6-3. PFET Conducting Hot Carrier Model Paramaters

Devices

VDD [V]

Thin-oxide SG
PFET

-1.1

Medium-oxide
EG PFET

-1.8

Thick-oxide
DG PFET

-2.5

Direction

A (mean)

VAF

Ea

1434.87

-0.48

-8.42

-0.051

0.224

1667.89

-1.76

-20.55

-0.0744

0.266

Target:
Q410

Target:
Q410

Target:
Q410

Target:
Q410

Target:
Q410

Forward

Note: For the thin-oxide PFET, Ion degradation is calculated for the regular-Vt device. The actual Ion shift is slightly
different for the high-Vt and low-Vt PFET devices.

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Time Calculations
Hot carrier effects occur in PFET devices when VDS is close to VDD and appreciable ID is flowing. For typical CMOS
circuits, these conditions occur only during switching transients. In this case, equivalent stress time (t eq) can be
approximated by:

where:
tuse is the chip / circuit operating time in hrs and duty factor (Df) is a function of ITR, TTR and SF and can be
expressed as

where:
ITR = ratio of gate voltage rise time (1090%) to total cycle time
TTR = ratio of drain voltage fall time (1090%) to gate voltage rise time (1090%)
SF = switching factor (that is, the fraction of cycles in which the PFET switches on: rising input, falling
output)
tuse = actual use time in hours
Based on real silicon data, hot carrier duty factor as well as transition time / duration at different VDS are
demonstrated in below Table 6-4a and Table 6-4b.
Table 6-4. Thin-oxide (SG) RVT PFET Duty Cycle Factor

DC teq
(T0.1)
[Yrs]

DC teq
(T50) [hrs]

tuse [Yrs]

Max. Permissible
Duty Factor
[=(T0.1/10)*100]

CLK time [ns]

Transition Time
[ps] (=D.
Factor*CLK time)

1.21

0.2

1.23

0.12

0.38

5668.69

10

2.00

20.00

0.38

3401.214

10

1.20

1.25

12.00

0.07

0.38

1984.041

10

0.70

7.00

1.28

0.04

0.38

1133.738

10

0.40

4.00

1.3

0.02

0.38

566.869

10

0.20

2.00

VDS [V]

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Table 6-4b. Medium-oxide (EG) PFET Duty Cycle Factor

DC teq
(T0.1)
[Yrs]

DC teq
(T50) [hrs]

tuse [Yrs]

Max. Permissible
Duty Factor
[=(T0.1/10)*100]

CLK time [ns]

Transition Time
[ps] (=D.
Factor*CLK time)

1.98

209.9

0.31

4792115

10

2099.00

20990.00

142.09

0.31

3243981

10

1420.90

14209.00

2.1

22.58

0.31

515511.9

10

225.80

2258.00

2.2

4.24

0.31

96801.18

10

42.40

424.00

2.3

0.92

0.31

21004.03

10

9.20

92.00

VDS [V]

Narrow Device Correction


Under the same stress environment, no significant difference was observed between narrow width (<0.7um) and
wide width (1um & above) device saturation current degradation. Therefore, no width correction is required.
Device Characteristics
The observed effect of hot carrier injection on a PFET device is dependent on the measurement conditions applied
after stress. Reverse mode refers to the situation where a device is measured with its source and drain
connections reversed relative to those during stress. Thus, the reverse saturation degradation is important when a
device is used bidirectionally, as in a pass gate. As of today, device characteristics based on reverse saturation
degradation is not available. Once data collection and characterization would complete, reliability performance
would be demonstrated in this section. Pls contact with your GLOBALFOUNDRIES representative for the
availability of the DM update.
Thin-Oxide Device Example
An inverter circuit is operated for 100 000 hours, where:
Input rise time = 100 ps
Output fall time = 200 ps
Cycle time = 1 ns
SF = 1/4
VDD = 1.21 V
Lp = 0.0 4 m (nominal)
T0.1 @ 1.21V = 0.2Yrs (=teq)
T0.1 @ 1.21V=10Yrs
Df = 2%
F(TTR)=0.02/(0.1X0.25)=0.8 and Input/Output voltage transition time @ 1.21V = 20ps

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Teq=0.2 Yrs meaning, for 10 Yrs of chip (circuit) operating time, equivalent hot carrier stress time would be
approximately 0.2 Yrs (for Idsat=10%).
Calculation of t0.1 / t50:
= 0.31 (based on actual data)
t0.1 = t50 * exp (-3.09*)

6.3.2.4 Nonconducting Hot Carriers : N-Channel Devices


The nonconducting stress mode is one in which VGS equals zero and VDS is high. NFET devices in which significant
subthreshold or punchthrough current flows can exhibit hot carrier effects. The physical mechanism is similar to the
conducting NFET.
Based on 45nm tech. non-condcuting experience, conducting degradation mechanism still dominates. Therefore,
non-conducting hot carrier based device current degradation mechanism should be at minimum level or no
concern from chip operating lifetime perspective. But to substantiate our claim, we would collect limited stress data
to compare with conducting data and final conclusion would be made based on this. This info would be available in
later update version. Pls contact with your GLOBALFOUNDRIES representative for the non-conducting hot carrier
degradation update.

6.3.2.5 Nonconducting Hot Carriers : P-Channel Devices


Based on 45nm tech. non-condcuting experience, conducting degradation mechanism still dominates. Therefore,
non-conducting hot carrier based device current degradation mechanism should be at minimum level or no
concern from chip operating lifetime perspective. But to substantiate our claim, we would collect limited stress data
to compare with conducting data and final conclusion would be made based on this. This info would be available in
later update version. Pls contact with your GLOBALFOUNDRIES representative for the non-conducting hot carrier
degradation update.
Temperature dependency of hot carrier induced device current degradation can be evaluated using the model 7
model parameters.

6.3.3 Gate Dielectric Integrity


Gate dielectric integrity is mainly driven by random process defects. Therefore, reliability failure rates depend on
the total gate-oxide area. To reduce the impact of reliability failures caused by these defects, the following rules
must be observed. The more recommended rules one follows, the lower the impact of gate-oxide defects on overall
chip reliability.
Below is a list of two general categories of capacitors and the reliability rules that must be applied.

Decoupling capacitors
Large area capacitors used for decoupling between VDD and ground must be designed as n-well to
substrate capacitors. Alternative designs, such as the one described in Section 5.19 NFET in N-Well
Capacitor (NCAP) and PFET in P-Well Capacitor (PCAP) on page 215, require prior approval by
GLOBALFOUNDRIES.

Capacitors used in leakage-sensitive analog circuitry (for example, phase-locked loops)


Large area thin-oxide capacitors must be designed by connecting small area (161.0000 m maximum for
2
polysilicon) plates in parallel. However, it is recommended that 31.5000 m plates be used instead.
2

All polysilicon gates (FETs and capacitors) must meet the antenna design rules described in Section 3.7
Antenna Design Rules on page 87.

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It is recommended that circuitry be implemented to enable voltage screens at wafer final test to reduce
reliability impact during product life.
To minimize the contribution of gate-to-diffusion related failures, capacitors must be designed to
minimize the gate-to-diffusion perimeter (that is, place polysilicon edges over isolation oxide where
possible.)
The total thin-oxide capacitor area must be negligible (< 2%) relative to the total chip thin-oxide area
(capacitors plus devices).

6.3.4 Vmax and Vos for 1.8 nm, 2.8 nm and 5,2 nm Gate Dielectrics
The CMOS 40LP 1.8 nm gate dielectric has been qualified for a maximum use voltage of 1.32 V at a temperature
2
of 125C, a total oxide area of 100 mm , a lifetime (Power-law based) of 100 KPOH, and a 100% duty factor. The
CMOS 40LP 2.8 nm gate dielectric has been qualified for a worst-case voltage of 1.98 V. The CMOS 5.2nm gate
dielectric would be qualified (pls check your GLOBALFOUNDRIES representative for the 2.5V, 5.2nm reliability
info) for a worst-case voltage of 2.75V. Exceeding these maximum conditions can result in severe device
degradation and gate-oxide failure. Additional limits on the applied voltage are described in Section 5 Electrical
Parameters and Models on page 195.
The maximum permitted voltages across the gate dielectric are defined as follows:
Vmax

Maximum permitted dc voltage without transients (overshoot or undershoot). See figure below.

Vos

Maximum permitted transient voltage when used with a maximum high level of V h
(Vh < Vmax).

Figure 6-1. Overshoot and Undershoot

a. Overshoot

b. Undershoot

The equations below calculate the maximum voltages as a function of lifetime, KPOH; maximum junction
temperature, Tj; and total gate area for each device type listed in. These equations are valid only for junction
temperatures above 30C. The values at 30C should be used for applications below 30C.

AA AT 100 1 N
Vmax = Vref --------------------------------- KPOH D
f

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AA AT AV 100 KPOH D f + t os
Vos = Vh ---------------------------------------------------------------------------------------------------t os

AA =

Area mm
----------------------------A ref

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1N

1
-----B

Ea
Eb

1
1 - + -----------------------1
1 - 2
AT = exp ------------------------ ------------------------------- -------- ------------------------------- -------

5
273 + Tj C 398
398
8.6210
273 + T j C
8.6210

Vh N
AV = --------V
ref

tos = KPOH Sf Dos


where:
Df= fraction of the product lifetime with a dielectric voltage at Vh or switching to Vh
Sf= fraction of the total cycles, where:
overshoot occurs when a switch to Vh occurs
undershoot occurs when a switch to the low level occurs
Dos= fraction of a switching cycle where the voltage across the dielectric exceeds Vh
The constants Vref, N, Aref, B, Ea, and Eb are listed in below Table 6-5 for each device type.
Table 6-5. Maximum Voltage Parameters for 1.8 nm, 2.8 nm and 5,2 nm Gate Dielectrics
Vref

Aref [um2]

Ea

Eb

1.8 nm NFET

1.21/1.32

48.01

0.24

1.21

0.4494

1.8 nm PFET

1.21/1.32

40.36

0.24

1.20

0.5119

2.8nm NFET

1.98

48.41

1.7

1.63

0.374

2.8nm PFET

1.98

40.20

1.7

1.54

0.5397

5.2 nm NFET

2.75 / 3.63

Q410

Q410

Q410

Q410

5.2 nm PFET

2.75 / 3.63

Q410

Q410

Q410

Q410

Device

Lifetime / voltage estimation model (Power-law):

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1.1V Thin-oxide NFET:

Yrs 3.17 E 13 V

48.01

0.24
exp 0.4494
K Temp. APr oduct

1
1.21

0.24
exp 0.5119
K Temp. APr oduct

1
1.20

1.7
exp 0.3740
K Temp. APr oduct

1
1.63

1.7
exp 0.5397
K Temp. APr oduct

1
1.54

Ln1 F

1
1.21

1.1V Thin-oxide PFET:

Yrs 9.06 E 09 V

40.36

Ln1 F

1
1.20

1.8V Medium-oxide NFET:

Yrs 1.68E 20 V

4841

Ln1 F

1
1.63

Ln1 F

1
1.54

1.8V Medium-oxide PFET:

Yrs 1.39 E 16 V

40.20

2.5V Thick-oxide NFET:

Q410

Note: Pls check with your GLOBALFOUNDRIES representative for the update

2.5V Thick-oxide PFET:

Q410

Note: Pls check with your GLOBALFOUNDRIES representative for the update

Where:
Tau is in Yrs, V is in volts, Ea in eV, K (Boltz. Const.) = 8.625E-5 eV/Kelvin, Temp. in Kelvin, A product in um2, F is Failure Rate

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6.3.5 Threshold Voltage Stability


6.3.5.1 Substrate Hot Carriers
The substrate hot carrier mechanism refers to the device degradation that occurs as a result of thermally generated
carriers in the depletion regions of reverse-biased junctions. These carriers can be injected into the gate oxide of a
device, which results in threshold voltage shifts. Based on 45nm tech. experience, no significant shifts during the
high voltage and high temperature stresses are expected in 40nm tech.

6.3.5.2 Ionic Instability


The presence of ionic contaminants in metal-oxide semiconductor (MOS) devices introduces parametric
instabilities. Referring to 45nm technology, the threshold voltage shifts caused by these mechanisms are listed in
Table 6-6. No ionic shifts have been observed to date in the CMOS 40nm technology, so the data in 6-6 is based
on theoretical line control capabilities.
Table 6-6 represents the maximum total shifts expected due to substrate hot carriers and ionic contamination.
Nonionic shifts for PFETs are not included and must be treated independently. All circuits must be designed to
tolerate the combined maximum shifts of all mechanisms.
Table 6-6. End-of-Life Vt shifts (100 000 Power-On Hours)

Device Type

Maximum Vt Shift

Maximum Vt Mismatch

NFET

10 mV

10 mV

PFET

10 mV

10 mV

6.3.6 Nonionic Instability


The PFET device exhibits an increase in nonmobile positive charge during symmetric (source equals drain) stress.
This shift is called negative bias temperature instability (NBTI), and results in larger magnitude saturation drain
current and threshold voltages over time
For a thin-oxide (SG) PFET (nominal):

Idsat (%) 0.243 * L0.176 * W 0.197 * exp(4.9VGS / tox) * exp(0.07 / KT ) * t 0.145


For a medium-oxide (EG) PFET (nominal):

Idsat (%) 0.304 * L0.164 * W 0.03 * exp(4.54VGS / tox) * exp(0.05 / KT ) * t 0.152


For a thick-oxide (DG) PFET (nominal):
Model development work would be completed by 4Q10, pls contact with your GLOBALFOUNDRIES
representative for the update.
where:

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Idsat = saturation drain current shift in %


Boltzmanns constant (8.62 10 eV/K)
-5

k =

T = stress temperature in Kelvin


Vg = gate-to-source stress bias in volts
tox = gate dielectric thickness in nanometers (tox applies to all oxide thicknesses)
t = time in hrs (that is, total time in the on state)
WD = design width in microns
LD = design length in microns
These models were developed under a constant dc gate bias with V DS at 0 V. For typical ac conditions (such as
digital applications) in which the gate bias switches off at least 10% of the time, some correction factor of 0.6 to the
dc model can be applied. Note that in analog applications modes such as power off that apply high gate bias and
no drain bias realize 100% of the dc model predictions.

6.3.7 Using Device Degradation Data


The threshold voltage shifts and current degradation values presented in this section are not all directly
additive.
Degradation for different VD bias conditions at a given stress mode, such as peak substrate current or peak gate
current, in equations that are not linear in time cannot be added linearly. The hot carrier and nonionic stability
mechanisms fall into this category. To calculate total degradation for more than one stress condition within a given
stress mechanism, one must linearize the degradation for each condition by raising it to the 1/n power, where n is
the exponent in the time term (assuming all stress conditions have the same n). This linearized degradation can
then be added and the result converted back to a final degradation by raising it to the nth power. This calculation is
summarized below:
1n

tot = 1

1n

+ 2

1n n

+ 3

Vt (stability) is additive. Use Vt (ionic) plusVt (nonionic).


PFET degradation from negative bias temperature instability and hot carrier mechanisms are directly additive.
(Apply the threshold shift and the current degradation.)
To add NFET degradation from conducting and nonconducting mechanisms, use the following approximation:
2

tot = C + NC

12

For bidirectional stress, the degradation from forward and reverse stresses should be directly added.

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6.3.8 Forward-Bias Injection Threshold Shift


A forward-bias injection threshold shift (FITS) refers to the trapping of carriers injected from forward-biased
junctions. Individual device degradation due to a FITS is highly design-dependent. Use of circuits that result in
forward-biased junctions is not recommended because of FITS, hot carrier, and latchup concerns.

6.3.9 P+Polysilicon OP Resistor Temperature Rise and Resistance Change


Near a P+ polysilicon OP resistor, the copper contacting lines in the vicinity of the resistor reach approximately the
same temperature as the resistor itself. In order to calculate the current density expected in the wire contacting the
resistor, the temperature rise of the resistor due to self-heating must be considered. Once that temperature rise is
determined, the copper electromigration rules must be used to determine the current density expected in the wires
contacting the resistor. Adjustments are available to account for temperature and duty cycle.
Silicon test data based resistance change related reliability model info would be available later on, pls contact with
your GLOBALFOUNDRIES counterpart for the update.

6.3.10 Soft Error Rate


In this section, all dimensions are actual wafer dimensions.
A soft error is a spontaneous, irreproducible error or change in stored information that does not damage the chip.
SRAM cells, DRAM cells, latches, and dynamic logic circuits are known to experience soft errors; however, other
circuits might also be susceptible. These errors typically result in a system error or crash, program error, or loss of
data integrity. In a memory element, a soft error occurs when a transient current spike flips a bit. Soft errors result
from naturally occurring ionizing radiation, including alpha particles from the radioactive decay of heavy elements
10
and by-products of collisions between cosmic rays and atoms in the chip. B concentrations are controlled in the
10
process used to reduce the soft error rate (SER) from the thermal neutron B reaction well below the high energy
cosmic ray-induced SER.
SER Reliability Physical test data update would be available by end of 1Q11, please contact with your
GLOBALFOUNDRIES counter parts for the update.

6.4 Back-End-of-Line (BEOL) Reliability Design Rules


6.4.1 Electromigration (EM)
Electromigration refers to the gradual degradation of interconnects due to the combined effects of current and
temperature. The following rules give designers the information needed to ensure that electromigration has a
negligible impact on the reliability of 40nm CMOS Low Power designs.
The rules do not address protection of circuits against extraordinary current/temperature situations like
electrostatic discharge, electrical overloads, or latchup.

6.4.1.1 Design Analysis Strategy


Electromigration is analyzed by dividing interconnect networks into simplified elements: metal lines of a given width,
contacts and vias that serve as interlevel connections to lines, and flip chip solder balls that connect the chip to the
package. It is a designer's duty to make sure that the electromigration rules are followed for all elements of the
design.
Designers should include the following activities in their design methodology:

Use the electromigration rule adjustments 6.4.1.11 EM Rule Adjustments to determine the current limits for the
circuit application being considered
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Use the capacitive load of the circuit and the operating frequency to calculate the currents expected in the
metal lines (see 6.4.1.3 Equivalent Current Formulas) for comparison to the current limits. This simple check
can be performed for each circuit node capacitance listed in the chip timing simulations.

Use a circuit simulator (for example, ASX or SPICE) to calculate the currents in the metal interconnects where
an EM problem is suspected or where greater accuracy is required. Particular attention should be paid to the
following cases (this is not an exhaustive list):
Off-chip drivers, which might have to drive very large loads
Power buses; check for hot spot where demands for current from several circuits might accumulate along
the length of a bus line
Any circuit where a dc current is present

Because the EM rules are generic, they contain imbedded assumptions that might be overly conservative for
particular designs. Thus, in addition to general adjustments of the rules based on different applications, a limited
number of exceptions that allow marginal violation of the rules might be allowed in particular design circumstances.
Contact your GLOBALFOUNDRIES technical representative for assistance.

6.4.1.2 Application Assumptions and Rule Adjustments


The rules as listed are based on an assumed product life of 100 000 hours and an assumed junction temperature
of 110C. Adjustment factors for other lifetimes and temperatures are given. When applications are more stringent,
the adjustment factors must be applied. When applications are less stringent, adjustment factors should be used
only when it is certain that the designs are never used at more stringent conditions.

6.4.1.3 Equivalent Current Formulas


Current operating
frequency (fsw)

1 t sw

Equivalent average
dc current (Idc)

s - tsw i t dt
-----t sw 0

Operating switching
time (tsw)

Minimum time between successive current switching operations

RMS current (Irms)

(For the case of a pure ac current, Idc is zero)

t sw 2

sf sw

i t dt

Switching factor (s)

Fraction of operating cycles over the life of the product during which time a given
circuit switches

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6.4.1.4 Equivalent DC Average Current Translations into Capacitances


When simple static CMOS circuits are used to charge and discharge capacitances, the following formula links the
Idc limit and the Irms limit to the maximum capacitive load on the circuit output:
Idc
Cmax = ------------------------s fsw V

For the case of pure ac current:


I rms
C max = -----------------------------------------------------s fsw f sw V

where is the time duration of the current pulse.


These equations are approximate and their accuracy must be assessed by the designer prior to use. They do not
account for the crossover current that flows directly from VDD to ground while a circuit is switching, nor do they
separate gate capacitance from parasitic capacitances or account for circuits with large leakage through keeper
devices. If these effects add significant current, then the equations above must be modified to include them.

6.4.1.5 EM Failure Types and Corresponding Currents


Rules are given to protect against two types of current-induced failures: standard EM and local-heating enhanced
EM. For standard EM, the rules define a maximum Idc. For local-heating enhanced EM, the rules define a maximum
Irms. The values of any calculated Idc or Irms in any simplified elements of an interconnection network must not
exceed the values given in the following tables.

6.4.1.6 General Rules at 110C and 100 KPOH


Table 6-7 provides the maximum permitted Idc and Irms values for each wiring level. Note that an Idc limit is not stated
for PC because standard electromigration should not be a concern for this level. Examples for these rules are listed
in 6.4.1.9 Examples of General Rules at GLOBALFOUNDRIES recommends using additional vias beyond the
minimum requirement where possible.
Notes:
1. The maximum permitted current is always the smaller of the line limit (Table 6-8) or the via limit (Table 6-9)
2. Idc limit should never exceed the Irms limit. If the calculated Idc limit is higher than the Irms limit, use the Irms limit as
the maximum limit

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Table 6-7. General Idc Current Limits at 110C


Metal
Level

Idc (mA)

Irms (mA (1x)

PC

Irms limit

0.164 1.903 WDes 0.189 WDes

M1

0.887(WDes 0.00485)

4.22(WDes 0.023) 2.29

4.03
WDes 0.023

3.63
WDes 0.023

Idc (mA)
Wmin

Irms (mA)
Wmin

0.232

0.232

0.052

1.71

0.054

1.58

M2

4.06(WDes 0.023) 1.46

M3

4.06(WDes 0.023) 1.06

3.35
WDes 0.023

0.054

1.51

4.06(WDes 0.023) 0.58

2.85
WDes 0.023

0.054

1.39

0.913(WDes 0.0046)

M4

M5

M6

Lx

1.597(WDes 0.01265)

5.36(WDes 0.036) 0.38

2.65
WDes 0.036

0.181

1.05

BA

3.608(WDes 0.01325)

7.74(WDes 0.084) 0.37

2.73
WDes 0.084

0.504

2.88

Fx

8.520(WDes 0.0297)

11.8(WDes 0.06) 0.21

3.428

11.53

LB

5.077(WDes 0.09)

17.18(WDes 0.2) 0.109

8.682

50.34

1.

2.49
WDes 0.06

2.30
WDes 0.2

The following rules assume no lines have metal holes in them.

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6.4.1.7 Idc Exceptions to the General Rules for Vias


Error! Reference source not found.Table 6-8 describes the exceptions to the general Idc rules for vias. The
ermitted Idc limit per via is listed in the table. For multiple vias, the permitted Idc current is given by the permissible
current per via times the number of vias. For stacked vias or any other configuration of lines and vias, the current
through any single via must not exceed the values listed in the table.
Table 6-8. Maximum Idc Current Limit for Vias at 110C

Level

Idc Current Limit per Via (mA)

CA

0.049

Vx (1x vias)

0.049

Jx (2x vias)

0.23

WT (2x vias)

0.23

OT, GM, JR (6x Vias)

1.31

VV

20.5

6.4.1.8 Idc Exceptions to the General Rules for Short Line Lengths
Line lengths < 20 m with widths < (2 Wmin) can have increased Idc values. Any line within these limits can
operate at higher Idc limits. The via Idc limits in Table 6-15 do not apply to these lines.
To calculate the Idc limit for a line length <20 m with actual width < (2 Wmin), use the calculated Idc values from
Table 6-9, and adjust for use temperature and time in Table 6-15. I and Table 6-16
Table 6-9. Maximum Idc Current Limit for Short Length Application
Metal Level

Maximum Idc (mA)

Via Level

Maximum Idc
(mA/via)

M1

Imax=1.54(WDes - 0.040)

CA

0.13

Mx

Imax=1.68(WDes - 0.042)

Vx

0.14

Lx

Imax=2.86(WDes - 0.101)

Wx

0.60

BA

Imax=4.11(WDes - 0.002)

WT

TBD

If Idc is less than the maximum current limit, apply the following equation:
For M1 and Mx Levels

I dc (ShortLength) I dc (Calculated ) (20 / Length) not to exceed maximum current limits


,
For BA and Lx Levels

I dc (ShortLength) I dc (Calculated ) (10 / Length) , not to exceed maximum current limits


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If Idc is greater than Imax due to time and temperature adjustments, then short line-length adjustments do not
apply. The result of the short line-length adjustment must not exceed the maximum current limits.
For proper implementation of electromigration design rules, the following conditions must be met:

Line Idc, see Table 6-7, with adjustments for time, temperature, and short length

Maximum Idc current limit for vias in Table 6-8, with adjustments for time, temperature, and short length

Line Irms, see Table 6-7

6.4.1.9 Examples of General Rules at 110C / 100 000 Power-On Hours


The following tables give examples of the general rules on fully nested lines. The use current is limited by the width
of the underlying metal and the number of vias used.
The permissible limit for the use current per via is given in the preceding tables. For use of multiple vias, the
permissible current values equal the permissible current per via times the number of vias. For stacked vias or any
other configuration of lines and vias, the current through any single via must not exceed the values provided in the
preceding tables. For current flowing from a single via or an array of vias (into the line) in two directions, the current
value in either direction must not exceed the limit given. The current limit for the line rule, given in Error! Reference
ource not found., must not be violated in any case.
Table 6-10. Examples of Contacts (CA/M1) at 110C
Metal Width (Design)

Maximum Idc (mA)

Idc Range (mA)

Single CA contact

WDes <0.061

I max 0.887(Wdes 0.00485)

< 0.049

Single CA contact

W Des> 0.061

0.049

Multiple contacts

WDes> 0.061

See notes (below)

Layout

Notes:
1. Imax is determined by the lower value of the following two equations:
Imax = Via Imax nVias

or

I max 0.693(Wcorr 0.0065)

2. Imax adjustments still should be made for:

Temperature delta from 110C

End-of-life delta from 100 000 POH

Duty cycle less than 100% (average dc current)

3. If L < 20 and W Des (2 Wmin ) (design width), and Idc <short line-length adjustment Imax, apply the
short-length rule to the adjusted Imax. Short line-length adjustments must not exceed maximum current limits.
4. Never exceed the Irms current value.
5. For current split in multiple line directions out of the contact, Imax can be calculated for each line current
separately, but the via (Imax) must be maintained.

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6.4.1.10 Flip Chip Rules


Flipchip terminal pad types are defined as follows:
Positive flipchip pad
(VDD pad)

Flip chip pad at a higher voltage potential than the chip metallization, with
electron current flowing from the chip to the package.

Negative flipchip pad


(ground pad)

Flip chip pad at a lower voltage potential than the chip metallization, with electron
current flowing from the package to the chip.

Table 6-11. Design Rules for flip chip Terminals at 110C for Ceramic Packages

1.

Design Size

Flip chip Pad Size

Line into flip chip Pad

47.0

73

LB

WDes of Line into flip chip Maximum Idc per fllip chip
Pad (m)
(mA)For organic packages,
128

215.4

For organic packages, CMOS55LPE supports a 150 mA current for a 47 m chip via diameter, 97% lead (Pb)/3% tin (Sn) high-melt
solder flip chip with plated nickel-barrier UBM attached to an organic carrier with eutectic Pb/Sn solder. For flip chip terminals joined
to organic packages based on a different material, ball-limiting metallurgy (BLM) structure, or diameter, consult your
GLOBALFOUNDRIES technical representative for guidance regarding the maximum current.

Note: Wiring from flip chip must be sufficiently wide to satisfy the Idc and Irms limits from Error! Reference source
ot found., including considerations for HOLE shapes. If the total required width of the line into the flip chip pad
exceeds the maximum permitted wire width, then multiple wires are required to achieve the target current.
Note: The flip chip terminal rules are in a form similar to all other vias. If the metal line going into the flip chip pad
is less than the width, W, specified in Table 6-11. Desig, use the general rules for the metal line to determine the
maximum current permitted. The upper bound of 290 mA per flip chip applies to all flip chip types (positive,
negative, and signal). The maximum Idc limit for flipchips is established by EF D/295A, and the maximum line width
below a flip chip is established by BTV D/N65V. Contact your GLOBALFOUNDRIES technical representative if you
need further information. In the case of signal pads, the Irms for the metal line is the limiter.
Figure 6-2. Example of flip chip / LB

LB

W > 128 m

FV

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Table 6-12. Electromigration and Redundancy for flipchip Terminals at a 110C Operating
Temperature
Maximum Idc (mA) Target
Carrier and
Attach Solder

Ceramic

Organic with
eutectic solder

1.
2.

flip chip Size

Rule 910
(Octagon
dimension D in
m)

97% Pb/3% Sn flip chip with


TiW/Cr/Cu/Cu UBM

97% Pb/3% Sn flip chip with


Ni-Barrier TiW/Cr/Cu/Cu UBM

Grade 11

Grade 32

Grade 11

Grade 32

3 mil

40

111

134

111

134

4 mil

47

149

178

149

178

5 mil

47

149

178

149

178

4 mil

47

74

111

5 mil

47

74

111

Reliability grade 1 = 10 failures in time (FITs) per module or 1 FIT per package, where 1 FIT = 1 ppm for 1000 power-on hours,
module = silicon chip + package, and package = flip chip interconnect + carrier + associated hardware.
Reliability grade 3 = 100 FITs per module or 10 FITs per package.

Because current limits are determined in terms of failures in time (FITs), it is expected that failure rates increase
with operating hours. For example, if the failure rate is 10 FITs per module (grade 3) or 10 ppm per 1000 operating
hours, then it follows that products with 40 KPOH have 10 ppm 40 = 400 ppm and products with 100 KPOH have
10 ppm 100 = 1000 ppm.
Note that flip chip redundancy can be used to enable a higher current-carrying limit, assuming the following:

A set of n flip chip pads is considered redundant when the failure of an arbitrary (n 1) pad creates voltage and
current shifts that do not cause the chip to malfunction.

Unlimited use (over the product lifetime) is enabled only when the failure of an arbitrary (n 1) pad does not
cause the currents on the remaining pads to exceed the maximum current limit (corresponding to more than
20C of localized joule heating).

Table 6-13 shows an example of flip chip redundancy using standard 97% Pb/3% Sn flip chips with a 47 m via
diameter on ceramic.

Table 6-13. Flip chip Redundancy Example


Maximum Idc (mA
Number of Redundant flip chips

Current Increase (%)


Grade 1

Grade 3

149

178

156

186

160

193

15

171

204

20

178

215

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6.4.1.11 EM Rule Adjustments


The Idc limits in the preceding tables can be adjusted for cases with product lifetimes other than 100 000 power-on
hours and junction temperature limits other than 110C as indicated in Table 6-14 through Table 6-16
Note: No adjustment for the local-heating EM (Irms) is permitted.

Table 6-14. Adjustment Factors for Idc Only for Temperature and Time
Adjustment For

Multiplier

Temperature for Cu Wiring, including contacts, metals, and vias as


well as negative flip chips using the TV/TD option, where the wires into
the flip chip pad are Cu

Time for Cu Wiring, including contacts, metals, and vias as well as


negative flip chips using the TV/TD option, where the wires into the flip
chip pad are Cu

F EOL

act ual

0.909
110000
= --------------------------------------------------
10000 + EOL

actual

act ual

0.588
110000
= --------------------------------------------------
10000 + EOL

actual

act ual

0.555
110000
= --------------------------------------------------
10000 + EOL

actual

Temperature for VV/LB, including negative flip chips using the VV/LB
option with wires, where the wires into the flip chip pad are LB

Time for VV/LB, including negative flip chips using the VV/LB option,
where the wires into the flip chip pad are LB

F EOL

Temperature positive flip chips only VDD pad

Time positive flip chips only VDD pad

F EOL

Using the temperature and lifetime adjustment factors to justify higher current usages should be contemplated only
when the lower application end-of-life or temperature is certain. Designing with such a derivation in effect
inherently limits the applications of the product.

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Idc limit for interconnects for a given junction temperature, T, and for a given product lifetime, EOL actual, can be
calculated using the following relation:
Idc T EOLactual = Idco F T F EOLactual

where Idco = Idc limit at 110 C for 100 000 POH product lifetime. The values of F(T) and F(EOLactual) for contacts,
vias, and lines are given in Table 6-15 and Table 6-16
Table 6-15. Idc Temperature Adjustment Factors
Temperature (C)

Cu Multiplier

Al Multiplier

Positive flip chip Multiplier

50

99.60

14.13

7.87

60

41.20

8.51

5.31

70

17.97

5.27

3.65

80

8.21

3.35

2.57

90

3.92

2.20

1.84

100

1.94

1.46

1.34

110

1.00

1.00

1.00

120

0.53

0.70

0.75

125

0.39

0.58

0.66

Table 6-16. Idc Time Adjustment Factors


Power On Hours (POH)

Cu Multiplier

Al Multiplier

Positive flip chip Multiplier

40 000

2.05

1.59

1.55

50 000

1.73

1.43

1.40

75 000

1.26

1.16

1.15

100 000

1.00

1.00

1.00

110 000

0.924

0.950

0.953

150 000

0.711

0.802

0.812

200 000

0.556

0.684

0.698

6.4.2 Metal Corrosion


For corrosion protection, no exposed metal lines (other than wire-bond pads, if applicable) are permitted. In
addition, all edges must be protected with a triple crackstop to prevent oxidation.

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7. SRAM Device and Design Information


7.1 General Remark
This manual should be used in conjunction with the 45nm Generic Shrinkable (GLOBALFOUNDRIES 40LP)
Design Rule Manual, YI-DM00085. All general design and reliability rules, logic design models, layout guidelines,
definitions and chip design submission requirements are contained in the current release of the
GLOBALFOUNDRIES 40LP Design Manual and are not repeated in this document.
Note: Currently the GLOBALFOUNDRIES 40LP technology supports single orientation of the SRAM gates
(Horizontal, notch down). Please contact development engineering prior to implementing a dual oriented design.
A standard and dense one port SRAM cell and dual port cells are offered in GLOBALFOUNDRIES 40LP.
Table 7-1. GLOBALFOUNDRIES 40LP SRAM Device Dimensions
40LP Cells
Device

0.299 m
(299)

0.374 m
(374)

0.589 m
(589)

Wd (m)

Ld (m)

Wd (m)

Ld (m)

Wd (m)

Ld (m)

Access (NFET)

0.110

0.060

0.148

0.060

0.160

0.057

Pull Down
(NFET)

0.145

0.058

0.224

0.058

0.315

0.055

Load (PFET)

0.070

0.058

0.083

0.058

0.060

0.055

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Figure 7-1. Single Port SRAM Device

Figure 7-2. Dual Port SRAM Device

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7.2 Physical Design Information


7.2.1 Design Scale and Grid
SRAM designs are based on a 1nm grid.

7.2.2 Mask and Design Levels


Only those mask levels, which are different from the base GLOBALFOUNDRIES 40LP design manual are listed in
the table below. Please refer to the GLOBALFOUNDRIES 40LP design manual for the remaining mask levels.
Table 7-2. Mask Levels, Design Levels, and Graphic Design System II (GDSII) Stream Layers

Mask
Layer

Design
Level

GDSII
Layer
No.

NV2

NV

12

30

Vt adjustment for nFET halo.

Open

PV2

PV

12

31

Vt adjustment for pFET halo.

AD2

AD

12

100

ZP2

SRAM
_NPRE

200

68

1.
2.

GDSII
Data Shape Description
Type

Minimum
Line (m)

Minimum
Space (m)

RX

.140

.140

Open

RX

.140

.140

Vt adjustment for p-well implant for the Access Nfet.

Open

RX

.360

.280

Memory Cell N Predope

Open

PC

.460

.360

On
Aligns to
Wafer1

Blocked = resist will be covering the regions after exposure, where the layer is drawn/generated. On wafer is a combination of resist
and mask tone.
Required for the GLOBALFOUNDRIES 40LP cells.

7.2.3 Design and Utility Levels


Only those levels, which are different from the base GLOBALFOUNDRIES 40LP design manual are listed in the
table below. Please refer to the GLOBALFOUNDRIES 40LP design manual for the remaining levels.
Table 7-3. Design Levels, Utility Levels, and GDS Stream Layers

Design Level

GDSII
GDSII
Description
Layer No. Data Type

Related layer

CELLSNR

63

103

Marker shape used in SRAM cell to denote step and repeat. Used
by some DRC tools for SRAM waiver handling.

CAREC

14

88

Rectangular CA contact.

CAMINI

14

188

Mini contact

Within CELLSNR

DNS_SRAM

12

230

Marker shape to allow LVS to identify GF299 SRAM cells.

Within CELLSNR

DPR_SRAM

12

232

Marker shape to allow LVS to identify GF589 dual-port SRAM cell. Within CELLSNR

LRG_SRAM

212

38

Marker shape to allow LVS to identify GF374 SRAM cells.

Within CELLSNR

OUTLINE_NCELL0

62

67

Optional marker shape needed to create Array Descriptor File


(ADF) rules for bitfail mapping.

Within CELLSNR

OUTLINE_RCELL0

62

69

Optional marker shape needed to create Array Descriptor File


(ADF) rules for bitfail mapping.

Within CELLSNR

OUTLINE

62

21

Marker shape to define the edge of cell.

SRAMHVT

12

142

Marker shape to allow LVS to identify HVT SRAM cells.

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Design Level

CHRT_STRAP

GDSII
GDSII
Description
Layer No. Data Type

200

13

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Related layer

Marker shape used by DRC tool for SRAM strap cell related waiver
Within CELLSNR
handling.

7.2.4 Mask Alignment Sequence and Metallization Options


The following shows only the difference in the alignment sequence over the base GLOBALFOUNDRIES 40LP
design manual. Please refer to the GLOBALFOUNDRIES 40LP design manual for the full mask alignment
sequence and BEOL metallization options.
| <= RX
| ...
| <= AD
| ...
| <= PC
| ...
| <= NV
| <= PV
| ...
| <= OP

7.2.5 Design of Single Port and Dual Port SRAM cells


The layouts for the 0.299 m (GF299), 0.374 m (GF374) and 0.576 m (GF589) cells are shown in Figures 7-3
through 7-5 respectively. The RX, NW, PC, CA, M1, V1, M2, V2, and M3 levels are displayed in these figures.
2

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Figure 7-3. Layout for 0.299cell (GF299)

RX

FEOL for 0.299 cell (GF299)


CAREC

CAMINI

BEOL for 0.299 cell (GF299)

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Figure 7-4. Layout for 0.374 cell (GF374)

FEOL for 0.374 cell (GF374)

BEOL for 0.374 cell (GF374)

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Figure 7-5. Layout for 0.589 cell (GF589)

FEOL for 0.589 cell (GF589)

BEOL for 0.589 cell (GF589)

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7.2.6 Truth Table

SRAMHVT*
(12/142)

AD
(12/100)

DNS_SRAM
== Waivers
(12/230)

LRG_SRAM
== Waivers
(212/38)

DPR_SRAM
== Waivers
(12/232)

RF_SRAM
== Waivers
(212/64)

CELLSNR
== Waivers dg
(63/103)

Table 7-4. GLOBALFOUNDRIES 40LP Truth Table

Pass Gate Device (PG)


model card: DSRNFETWL

Pull Down Device (PD)


model card: DSRNFETPD

Pull Up Device (PU)


model card: DSRPFETPU

Pass Gate Device (PG)


model card: SRMNFETWL

Pull Down Device (PD)


model card: SRMNFETPD

Pull Up Device (PU)


model card: SRMPFETPU

Pass Gate Device (PG)


model card: DPRNFETWL

Pull Down Device (PD)


model card: DPRNFETPD

Pull Up Device (PU)


model card: DPRPFETPU

Structure
GF299 GF40LP area minimized Cell

GF374 GF40LP Single Port Cell

GF589 GF40LP Dual Port Cell

Note: Footnotes for GF40LP SRAM Truth Table


Model Card Definitions:
Model card DSR = Dense SRAM GF299
Model card SRM = Single Port GF374
Model card DPR = Dual Port GF589

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7.3. SRAM Physical Design Rules


7.3.1 Design Rule Abbreviations
Only those abbreviations, which are different from the base GLOBALFOUNDRIES 40LP design manual, are listed
in the table below. Please refer to the GLOBALFOUNDRIES 40LP design manual, same subject, for the remaining
abbreviations.
Table 7-5. Design Rule Checking Abbreviations
Abbreviation

Definition

CAREC end

CAREC end is defined as a (CAREC touching CELLSNR) edge with length= 0.060 m,

CAREC side

CAREC side is defined as a (CAREC touching CELLSNR) edge with length= 0.153 m,

Table 7-6. SRAM Ground-rule Waivers

Rule

Description

GF40LP
Ground
Rule

GF40LP-SRAM
Waived Value

SRJX00

JX minimum width

0.180

0.140

SRJX01b

JX minimum enclosed area (m2).

0.110

0.090

SRJX03

RX n+ junction minimum within JX.

0.070

0.040

SRJX05

RX p+ junction minimum space to JX

0.070

0.038

SRJX03a

RX minimum overlap of JX.


(This check doesnt include the region covered by layer of
CELLSNR)

0.100

SRJX370

(Gate not over JX) minimum space to JX.

0.080

0.038

SRJX371

Gate minimum within JX.

0.080

0.040

SR10

NFET gate minimum gate width.

0.115

0.11

SR11

PFET Gate minimum width

0.12

0.06

SR51

RX minimum area

0.031

0.016

SR51a

RX minimum area (with all the inner RX edge length <0.21


m) (m2).
(This check doesnt include the region covered by layer of
CELLSNR)

0.055

SR52

RX minimum space & notch

0.08

0.064

SR52b

(RX with width>0.12 m) minimum space with run length


0.14 m

0.100

0.080

SR102

PC minimum space & notch

0.1

0.07

SR104a

NFET gate minimum space (run length > 0.000 um) over RX

0.14

0.118

SR104b

PFET gate minimum space (run length > 0.000 um) over RX

0.13

0.118

SR104d

Gate with gate length >0.08 m) minimum space (run length >
0.000 m) over RX

0.14

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Description

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GF40LP
Ground
Rule

GF40LP-SRAM
Waived Value

0.12

Comment

(This check doesnt include the region covered by layer of


CELLSNR)
SR104e

(Gate_side for gates with channel length < 0.08 m) minimum


space to PC (run length > 0.000 m.
(This check doesnt include the region covered by layer of
CELLSNR)

SR110.1

RX overlap past PC when W1 larger than 0.017um


(This check doesnt include
1. the region covered by layers of CHRT_STRAP
2. the PC over RX region touching with CAREC)

0.06

0.056

Figure 3-1

SR110.2

RX overlap past PC when W1 less than or equal to 0.017um


(This check doesnt include
1. the region covered by layers of CHRT_STRAP
2. the PC over RX region touching with CAREC)

0.06

0.03

Figure 3-1

SR111.1

PC minimum overlap past RX when the region doesnt covered


by layer of CHRT_STRAP
(This check doesnt include the PC over RX region touching
with CAREC)

0.07

0.055

SR111.2

PC minimum overlap past RX when the region covered by


layer of CHRT_STRAP
(This check doesnt include the PC over RX region touching
with CAREC)

0.07

0.05

SR111a

PC minimum overlap past RX when PC to RX inner vertex


distance <= 0.100 m
(This check doesnt include
1. the region covered by layers of CHRT_STRAP
2. the PC over RX region touching with CAREC)

0.09

0.055

SR113

(PC not over RX) minimum space to RX.


(This check doesnt include
1. the region covered by layers of CHRT_STRAP
2. RX PC common run length 0.010)

0.03

0.03

SR119a

PC over RX vertex is prohibited.


(This check doesnt include the region covered by layer of
CELLSNR)

SR121

PC can straddle RX only at 90.000-deg.


(This check doesnt include the region covered by layers of
CHRT_STRAP )

SR125

PC over RX must divide RX into two or more diffusion regions.


(This check doesnt include the PC over RX region touching
with CAREC)

---

---

---

SR250

NW min width

0.34

0.274

SR260

RX p+ junction minimum within NW.

0.08

0.040

SR261a

RX n-well contact within NW.

0.08

0.040

SR265

RX n+ junction minimum space to NW.

0.08

0.040

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Rule

Description

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GF40LP
Ground
Rule

GF40LP-SRAM
Waived Value

SRJZ01

JZ min area

0.11

0.09

SRJZ02

JZ minimum space and notch

0.18

0.140

SRJZ03

RX p+ junction minimum within JZ. If RX straddles a butted


JZ, the butted diffusion rules apply.

0.07

0.038

SRJZ05

RX n+ junction minimum space to JZ

0.07

0.040

SRJZ03a

RX minimum overlap of JZ.


(This check doesnt include the region covered by layer of
CELLSNR)

0.100

SRJZ370

(Gate not over JZ) minimum space to JZ.

0.08

0.040

SRJZ371

Gate within JZ

0.08

0.038

SR501a

M1 min area

0.021

0.015

SR501aSE

(M1 width all edges less than 0.17 m) minimum area (m2)
(This check doesnt include the region covered by layers of
CELLSNR)

0.055

SR503_or

For (M1_end with length < 0.09 m), the M1_end must meet
rule SR503a or SR503b

SR503a

M1_LE minimum space to M1 for run length > 0 m

0.080

0.07

SR503b

M1_LS minimum space to M1 for run length > 0 m

0.080

0.07

SR553b_V1

V1 minimum space (for V1 on different nets with run length >


0)

0.11

0.108

SR570

M1 minimum overlap past V1 must meet rule 570a and 570b


or SR570c and SR570d

SR570c

V1 must be within M1.

0.01

0.006

SR570d

M1 minimum overlap past V1 for at least two opposite sides


with the other two sides 0.010 m (rectangular enclosure).

0.02

0.015

SR601a_M2

M2 min area

0.027

0.019

SR601aSE_M2 (M2 with all edges length less than 0.21 m) minimum area
(m2)

0.06

0.019

SR610_V2

M2 overlap past V2 must meet rules 610a and SR610b

SR610b_V2

M2 minimum overlap past V2 for two opposite sides with the


other two sides 0.000 m, (Rectangular enclosure)

0.03

0.02

SR611_V1

M2 overlap past V1 must meet rules 611a and 611b or


611a_or and SR611b_or

SR611b_or_V1

M2 minimum overlap past V1 for two opposite sides with the


other two sides 0.010 m, (Rectangular enclosure)

0.02

0.015

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7.3.2 Additional SRAM Design Rules


Table 7-7. Additional SRAM Design Rules

Rule

Note(s)

Description

GF40LP Design

NV01

NV must be within CELLSNR AND JX.

NV02

NV minimum width.

NV03

NV minimum space.

PV01

PV must be within CELLSNR AND JZ.


(This check doesnt include the region covered by layers of CHRT_STRAP)

PV02

PV minimum width.

PV03

PV minimum space.

ZP01

SRAM_NPRE must be within CELLSNR AND JX.

ZP02

SRAM_NPRE minimum width.

ZP03

SRAM_NPRE minimum space.

AD01

AD minimum space

AD02

AD minimum width.

0.360

AD03

AD minimum area.

0.190

AD04

AD must be within CELLSNR.

CAREC01

(CAREC touching CELLSNR) exact width.

0.06

CAREC02

(CAREC touching CELLSNR) exact length.

0.153

CAREC03

(CAREC touching CELLSNR) minimum space.

0.074

CAREC04

(CAREC touching CELLSNR) minimum space to CA.

0.073

CAREC04c

(CAREC touching CELLSNR) minimum space to CAMINI.

0.073

CAREC06

(CAREC touching CELLSNR) end minimum space to RX.

0.065

CAREC06a

(CAREC touching CELLSNR) side minimum space to RX.

0.065

CAREC07

(CAREC touching CELLSNR) end minimum space to PC.

0.035

CAREC07a

(CAREC touching CELLSNR) side minimum space to PC.

0.075

CAREC08

(CAREC touching CELLSNR) minimum space to M1.

0.055

CAREC09

CAREC must touch CELLSNR.

CAREC10

(CAREC touching CELLSNR) end overlap past PC

0.006

CAREC11

PC overlap (CAREC touching CELLSNR) side

0.005

CAMINI01

CAMINI exact width and length.

0.054

CAMINI02

(CAMINI over RX) minimum space to PC.

0.032

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Note(s)

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Description

GF40LP Design

CAMINI03

(CAMINI over PC) minimum space to RX.

0.040

CAMINI04

CAMINI minimum within PC.

0.001

CAMINI05

CAMINI center to center distance.

0.155

CAMINI06

CAMINI center to CA center distance.

0.16

CAMINI07

CAMINI minimum within RX.

0.003

CAMINI08

CAMINI must be within M1.

0.003

CAMINI08a

M1 minimum overlap CAMINI for two opposite sides with the other two sides 0.000
m, (Rectangular enclosure)

CAMINI09

CAMINI over GATE is prohibited

CAMINI10

CAMINI must touch RX or PC

CAMINI11

CAMINI must be within CELLSNR.

SRAM00

CELLSNR edge cross RX, PC, CA is not allowed


RX, PC, CA straddle CELLSNR is not allowed

(Gate covered by CELLSNR) must be on the same orientation.

SRAM107a

. All SRAM poly orientation must be horizontal with notch down. This note is not checked by DRC.

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7.3.3 SRAM Design Hierarchy


Placement of the CELLSNR marker level should be in the SRAM topcell for all cells which are part of the SRAM,
but does not include cells which are not part of the SRAM array block. Failure to place CELLSNR appropriately can
lead to errors in design finishing and DRC checking.
Figure 7-6. SRAM design rules

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7.4. Electrical Parameters


7.4.1 Electrical Parameters for GLOBALFOUNDRIES 40LP GF299 SRAM Cell
7.4.1.1 Available SRAM Field-Effect Transistors
Only the FETs, which are in addition to those offered in the GLOBALFOUNDRIES 40LP technology, are listed in
the table below. Please refer to the GLOBALFOUNDRIES 40LP design manual same subject for the remaining
FETs.
Table 7-8. Available Field-Effect Transistors in the GF299 SRAM Cell
Design levels1

FET Name

Model Name

VDD (V)

Tinv(nm)

SRAM word line NFET

DSRNFETWL

1.1

2.4

CELLSNR, DNS_SRAM, AD, SRAMHVT, NV

SRAM pull down NFET

DSRNFETPD

1.1

2.4

CELLSNR, DNS_SRAM, SRAMHVT, NV

SRAM pull up PFET

DSRPFETPU

1.1

2.6

CELLSNR, DNS_SRAM, SRAMHVT, PV

1.

For details see the Design Truth Table in section 2 of the GLOBALFOUNDRIES 40LP design manual.

7.4.1.2 Channel Length Variation


Please refer to the GLOBALFOUNDRIES 40LP design manual for channel length variations.
7.4.1.3 Channel Width Variation
Please refer to the GLOBALFOUNDRIES 40LP design manual for channel width variations.

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7.4.1.4 GLOBALFOUNDRIES 40LP GF299 SRAM Cell


Note: Models are expected to be updated in the future. Contact your GLOBALFOUNDRIES technical
representative prior to using the models.
Table 7-9. Electrical Parameters for SRAM NFET / PFET Devices in the GF299 SRAM Cell

Parameter

Definition

Unit

Transfer NFET

Pull Down
NFET

Pull Up
PFET

Ld

Design Length

0.060

0.058

0.058

0.005

0.005

0.000

Wd

Design Width

0.110

0.145

0.070

0.000

0.000

0.000

Vtlin

VD=0.05, VG=1.1, VS=0.0, VB=0.0, T=25C

mV

550

540

549

Vtsat

VD=1.1, VG=1.1, VS=0.0, VB=0.0, T=25C

mV

481

441

476

Idsat

VD=1.1, VG=1.1, VS=0.0, VB=0.0, T=25C

40.3

56.2

11.1

Ioff (drain)

VD=1.1, VG=0.0, VS=0.0, VB=0.0, T=25C

pA

1.1

4.2

2.3

Iread

VD=1.1,VG=1.1, VS=0.0, VB=0.0, T=25C

23.8

7.4.1.5 GF299 SRAM Cell Stability


Table 7-10. GF299 1 Vt Matching within Cell

Cell

GF299

Voltage (V)

Temperature
(C)

Word Line
NFET (mV)

Pull Down
NFET (mV)

Pull Up
PFET (mV)

1.1

25

58

56

56

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7.4.2 Electrical Parameters for GLOBALFOUNDRIES 40LP GF374 SRAM Cell


7.4.2.1 Available SRAM Field-Effect Transistors

Only the FETs, which are in addition to those offered in the GLOBALFOUNDRIES 40LP technology, are listed in
the table below. Please refer to the GLOBALFOUNDRIES 40LP design manual same subject for the remaining
FETs.
Table 7-11. Available Field-Effect Transistors in the GF374 SRAM Cell

FET Name

Model Name

SRAM word line NFET

Design levels1

VDD (V)

Tinv(nm)

SRMNFETWL

1.1

2.4

CELLSNR, LRG_SRAM,AD,SRAMHVT, NV

SRAM pull down NFET

SRMNFETPD

1.1

2.4

CELLSNR, LRG_SRAM,SRAMHVT, NV

SRAM pull up PFET

SRMPFETPU

1.1

2.6

CELLSNR, LRG_SRAM,SRAMHVT, PV

1.

For details see the Design Truth Table in section 2 of the GF40LP design manual.

7.4.2.2 Channel Length Variation


Please refer to the GLOBALFOUNDRIES 40LP design manual for channel length variations.
7.4.2.3 Channel Width Variation
Please refer to the GLOBALFOUNDRIES 40LP design manual for channel width variations.
7.4.2.4 GLOBALFOUNDRIES 40LP GF374 SRAM Cell

Note: Models are expected to be updated in the future. Contact your GLOBALFOUNDRIES technical
representative prior to using the models.
Table 7-12. Electrical Parameters for SRAM NFET / PFET Devices in the GF374 SRAM Cell at nominal Vdd
Parameter

Definition

Unit

Transfer NFET

Pull Down
NFET

Pull Up
PFET

Ld

Design Length

0.060

0.058

0.058

0.005

0.005

0.000

Wd

Design Width

0.148

0.224

0.083

0.000

0.000

0.000

Vtlin

VD=0.05, VG=1.1, VS=0.0, VB=0.0, T=25C

mV

558

550

559

Vtsat

VD=1.1, VG=1.1, VS=0.0, VB=0.0, T=25C

mV

490

439

490

Idsat

VD=1.1, VG=1.1, VS=0.0, VB=0.0, T=25C

56.1

88.4

14.9

Ioff (drain)

VD=1.1, VG=0.0, VS=0.0, VB=0.0, T=25C

pA

4.1

11.8

0.4

Iread

VD=1.1,VG=1.1, VS=0.0, VB=0.0, T=25C

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7.4.2.4 GF374 SRAM Cell Stability
Table 7-13. GF374 1 Vt Matching within Cell

Cell
GF374

Voltage (V)

Temperature
(C)

Word Line
NFET (mV)

Pull Down
NFET (mV)

Pull Up
PFET (mV)

1.1

25

50

46

60

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7.4.3 Electrical Parameters for GLOBALFOUNDRIES 40LP GF589 SRAM Cell


7.4.3.1 Available SRAM Field-Effect Transistors

Only the FETs, which are in addition to those offered in the GLOBALFOUNDRIES 40LP technology, are listed in
the table below. Please refer to the GLOBALFOUNDRIES 40LP design manual section 5 for the remaining FETs.
Table 7-14. Available Field-Effect Transistors in the GF589 SRAM Cell

Design levels1

FET Name

Model Name

VDD (V)

TINV (nm)

SRAM word line NFET

DPRNFETWL

1.1

2.4

CELLSNR, DPR_SRAM, AD, SRAMHVT, NV

SRAM pull down NFET

DPRNFETPD

1.1

2.4

CELLSNR, DPR_SRAM, SRAMHVT, NV

SRAM pull up PFET

DPRPFETPU

1.1

2.6

CELLSNR, DPR_SRAM, SRAMHVT, PV

1.

For details see the Design Truth Table in section 2 of the GF40LP design manual.

7.4.3.2 Channel Length Variation


Channel Length Variation
Please refer to the GLOBALFOUNDRIES 40LP design manual for channel length variations.
7.4.3.3 Channel Width Variation
Please refer to the GLOBALFOUNDRIES 40LP design manual for channel width variations.

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7.4.3.4 GF40LP GF589 SRAM Cell


Table 7-15. Electrical Parameters for SRAM NFET / PFET Devices in the GF589 SRAM Cell at nominal VDD
Parameter

Definition

Unit

Transfer NFET

Pull Down
NFET

Pull Up
PFET

Ld

Design Length

0.057

0.055

0.055

0.005

0.005

0.005

Wd

Design Width

0.160

0.315

0.060

0.000

0.000

0.000

Vtlin

VD=0.05, VG=1.1, VS=0.0, VB=0.0, T=25C

mV

560

537

527

Vtsat

VD=1.1, VG=1.1, VS=0.0, VB=0.0, T=25C

mV

475

431

450

Idsat

VD=1.1, VG=1.1, VS=0.0, VB=0.0, T=25C

53.5

115.3

12.1

Ioff (drain)

VD=1.1, VG=0.0, VS=0.0, VB=0.0, T=25C

pA

5.5

29.9

0.2

Iread

VD=1.1,VG=1.1, VS=0.0, VB=0.0, T=25C

38.7

Iread_dual

VD=1.1, VG=1.1, VS=0.0, VS=0.0, T=25C

29.3

7.4.3.5 GF589 SRAM Cell Stability


Table 7-16. GF589 1 Vt Matching within Cell
Cell

Voltage (V)

Temperature
(C)

Word Line
NFET (mV)

Pull Down
NFET (mV)

Pull Up
PFET (mV)

GF589

1.1

25

53

39

50

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7.5. Reliability Design Rules and Models


SRAM circuits are sensitive to PFET Vt shifts due to NBTI. This shift leads to a shift in Vmin and will result in
shift (derived from NBTI equations) is a function of lifetime and operating conditions. To avoid reliability fails in the
field, it is highly recommended that a Vmin guardband is added to the product test which is based on the NBTI
equations for worst case application conditions plus 1 sigma variation. For example, a lifetime of 100 KPOH, 1.32
V, 125C, 50% duty cycle yields 88 mV guardband. The Vmin test at the pin should then be 1.08 V 88 mV 1
sigma variation. Additional guardbanding may be required for other reasons on any specific product.
Dispositioning product to this guardband may either be repair or reject. If you have additional questions, please
contact your GLOBALFOUNDRIES technical representative.

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8. RF Device and Design Information


8.1 Technology Introduction
8.1.1 General Remark
This section covers the 40nm-LP Analog and RF Device feature.

8.1.2 Features
Please refer to the section 1.2.

8.1.3 Ordering Information


Please refer to the section 1.3.

8.1.4 Chip Design Checklist


Please refer to the section 1.4.

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8.2 Physical Design Information


8.2.1 Design Scale and Grid
Please refer to the section 2.1.

8.2.2 Mask and Design Levels


Please refer to the section 2.2.

8.2.3 Nondesign Mask Levels


Please refer to the section 2.3.

8.2.4 Design and Utility Levels


Please refer to the section 2.4.

8.2.5 Data Preparation Levels


Please refer to the section 2.5.

8.2.6 Kerf design levels


Please refer to the section 2.6.

8.2.7 Reference level


Please refer to the section 2.7.

8.2.8 Mask Alignment Sequence and Metallization Options


Please refer to the section 2.8.

8.2.9 Design Preparation


Please refer to the section 2.9.

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8.2.10 Truth Tables


The truth-values presented in Table 8-1 and Table 8-2 are provided as a physical design aid for the listed structures. The truth table values are defined as follows:
0 The design or generated level must not touch the structure
1 The design or generated level must cover or match the structure
x The design level does not affect the structure (Table 8-1) or the generated level might not be present depending on the design levels

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Low=Vt

RX
NW
T3
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5VHVFET
VNCAP2
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QT
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CHRT_RFFET

Structure

Table 8-1. Design Truth Table

Low-Vt NFET

1 0 x 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1

Low-Vt PFET

1 1 x 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1

Regular-Vt NFET

1 0 x 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1

Regular-Vt PFET

1 1 x 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1

High-Vt NFET

1 0 x 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1

High-Vt PFET

1 1 x 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1

ADNFET

1 0 x 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 1 0

ADPFET

1 1 x 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 1 0

1.8 V HSIO
NFET

1 0 x 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1

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RX
NW
T3
LVT_OR2
XW
LW
HVT_OR2
NR
PR
PC
EG
DG
ZVT
EGV
DGV
OVERDRIVE
VPNP
JX
JZ
OP
SBLK
NCAP_OR VAR3
PCAP_OR VAR3
BFMOAT
EFUSE
BIPOLAR
ED
NWRES
BPNWR
PRES
DRES
POLY_SAL
DIFF_SAL
TIEDOWN
CELLSNR
RF_SRAM
AD
ESD_xxx1
ESDSCR_HBM
RXEXCLUD
HCVNCAP
VNCAPHV
5VHVFET
VNCAP2
DIODE
MIM_NI
HT
QT
LBTRANS
TRANSMIS
M1_BLKPEX
OUTLINE_RF
CHRT_RFFET

Structure

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1.8 V HSIO
PFET
1.5 V HSIO
NFET
1.5 V HSIO
PFET
1.8 V DG I/O
NFET
1.8 V DG I/O
PFET
2.5 V DG I/O
NFET
2.5 V DG I/O
PFET
3.3 V DG I/O
NFET
3.3 V DG I/O
PFET
Triple-well NFET
T3
Medium-Oxide
5V LDNMOS
Medium-Oxide
5V LDPMOS
2.5V Thick-Oxide
5V LDNMOS
2.5V Thick-Oxide
5V LDPMOS

1 1 x 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1
1 0 x 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1
1 1 x 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1
1 0 x 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1
1 1 x 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1
1 0 x 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1
1 1 x 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1
1 0 x 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1
1 1 x 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1
1 0 1 x x x x x x 1 x x 0 x x x 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 1 1 1
1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 1 0 0 x x x 0 0 1 1 1
1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 1 0 0 x x x 0 0 1 1 1
1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 1 0 0 x x x 0 0 1 1 1
1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 1 0 0 x x x 0 0 1 1 1

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Zero-Vt
Medium-Oxide Voltage
Thick-Oxide Voltage
Overdrive Voltage
Vertical PNP Device
N+ S/D Implant
P+ S/D Implant
Silicide Block

High-Vt

Active Area
N-Well
N-band for isolated P-well
Low=Vt

[YI-DM00085]
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RX
NW
T3
LVT_OR2
XW
LW
HVT_OR2
NR
PR
PC
EG
DG
ZVT
EGV
DGV
OVERDRIVE
VPNP
JX
JZ
OP
SBLK
NCAP_OR VAR3
PCAP_OR VAR3
BFMOAT
EFUSE
BIPOLAR
ED
NWRES
BPNWR
PRES
DRES
POLY_SAL
DIFF_SAL
TIEDOWN
CELLSNR
RF_SRAM
AD
ESD_xxx1
ESDSCR_HBM
RXEXCLUD
HCVNCAP
VNCAPHV
5VHVFET
VNCAP2
DIODE
MIM_NI
HT
QT
LBTRANS
TRANSMIS
M1_BLKPEX
OUTLINE_RF
CHRT_RFFET

Structure

Spec ID:
Revision:
Page:

3.3V Thick-Oxide
5V LDNMOS
3.3V Thick-Oxide
5V LDPMOS

1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 1 0 0 x x x 0 0 1 1 1
1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x 1 0 0 x x x 0 0 1 1 1

N+ junction

1 0 0 x x x x x x 0 x 0 x x x x x 1 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 x x x 0 0 0 x x x 0 0 0 1 0

N+ junction T3

1 0 1 x x x x x x 0 x x x x x x x 1 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 x x x 0 0 1 x x x 0 0 0 1 0

N+ tie down
diode
N+ tie down
diode T3

1 0 0 x x x x x x 0 x 0 x x x x x 1 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x 0 x x x 0 0 0 x x x 0 0 0 1 0
1 0 1 x x x x x x 0 x x x x x x x 1 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x 0 x x x 0 0 1 x x x 0 0 0 1 0

N-well contact

1 1 0 x x x x x x 0 x x x x x x 0 1 0 0 0 x 0 0 0 x 0 0 0 0 0 0 0 0 x x 0 0 0 x x x 0 0 0 x x x 0 0 0 1 0

Substrate
contact

1 0 0 x x x x x x 0 x x x x x x x 0 1 0 0 0 x 0 0 x 0 0 0 0 0 0 0 0 x x 0 0 0 x x x 0 0 0 x x x 0 0 0 1 0

P+ junction

1 1 0 x x x x x x 0 x 0 x x x x 0 0 1 0 x 0 0 0 0 x 0 0 0 0 0 0 0 0 x x x x 0 x x x 0 0 0 x x x 0 0 0 1 0

P+ tie down
diode
Triple-well
contact T3
Thin-oxide NCAP
Medium-oxide
NCAP
Thick-oxide
NCAP

1 1 0 x x x x x x 0 x 0 x x x x 0 0 1 0 x 0 0 0 0 x 0 0 0 0 0 0 0 1 x x x x 0 x x x 0 0 0 x x x 0 0 0 1 0
1 0 1 x x x x x x 0 x x x x x x 0 0 1 0 0 0 x 0 0 x 0 0 0 0 0 0 0 0 x x 0 0 0 x x x 0 0 1 x x x 0 0 0 1 0
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 0 1 0
1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 1 0
1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 0 1 0

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APMOM Marker
5V LDMOS
RF HCVNCAP
RF Well diode
MIM marking layer
MIM Top Plate
MIM Bottom Plate
Rflin marking layer
transmis marking layer
RF FET Marking
RF Marking
RF FET Marking

NFET-in-N-well Capacitor
PFET-in-P-well Capacitor
Highly Resistive Substrate
Electrical PC Fuse
Bipolar Transistor
ESD Implant
N-well Resistor
N-well over Active Resistor
Polysilicon Resistor
Diffusion Resistor
Salicide Poly Resistor
Salicide Diffusion Resistor
Tie Down Diode Marker
SRAM Cell Marker
SRAM Marker
Pass Gate
ESD Marker

Polysilicon
Medium Oxide
Thick Oxide
Zero-Vt
Medium-Oxide Voltage
Thick-Oxide Voltage
Overdrive Voltage
Vertical PNP Device
N+ S/D Implant
P+ S/D Implant
Silicide Block

High-Vt

Active Area
N-Well
N-band for isolated P-well
Low=Vt

[YI-DM00085]
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RX
NW
T3
LVT_OR2
XW
LW
HVT_OR2
NR
PR
PC
EG
DG
ZVT
EGV
DGV
OVERDRIVE
VPNP
JX
JZ
OP
SBLK
NCAP_OR VAR3
PCAP_OR VAR3
BFMOAT
EFUSE
BIPOLAR
ED
NWRES
BPNWR
PRES
DRES
POLY_SAL
DIFF_SAL
TIEDOWN
CELLSNR
RF_SRAM
AD
ESD_xxx1
ESDSCR_HBM
RXEXCLUD
HCVNCAP
VNCAPHV
5VHVFET
VNCAP2
DIODE
MIM_NI
HT
QT
LBTRANS
TRANSMIS
M1_BLKPEX
OUTLINE_RF
CHRT_RFFET

Structure

Spec ID:
Revision:
Page:

Thin-oxide PCAP
Medium-oxide
PCAP
Thick-oxide
PCAP
Hyper-abrupt
Varactor

1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 x x x 0 0 0 1 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x 0 0 0 1 0

Inductor

x x x x x x x x x x x x x x x x x x x x x x x x 0 x x x 0 x x 0 0 0 0 0 x 0 0 x 0 0 0 0 0 0 0 0 0 0 0 1 0

HCVNCAP

x x x x x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x x x 0 0 x 0 0 x 1 0 x 1 0 0 0 0 0 0 0 1 0

APMOM

x x x x x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x x x 0 0 x 0 0 x 0 1 x 1 0 0 0 0 0 0 0 1 0

MIM

1 x x x x x x x x x x x x x x x x x x x x x x x 0 x x x x x x x x 0 0 0 x 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0

ESD NFET

1 0 0 0 0 0 0 0 0 1 x x 0 x x x x 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 0 0 0 x x x 0 0 0 1 0

ESD NFET w/
ESD IMPLANT

1 0 0 0 0 0 0 0 0 1 x x 0 x x x x 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 0 0 0 x x x 0 0 0 1 0

ESD PFET

1 1 0 0 0 0 0 0 0 1 x x 0 x x x x 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 0 0 0 x x x 0 0 0 1 0

ESD triple-well
NFET T3

1 0 1 0 0 0 0 0 0 1 x x 0 x x x x 1 0 0 1 0 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 0 0 0 x x x 0 0 0 1 0

ESD N+ junction

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 0 0 0 x x x 0 0 0 1 0

ESD N+/PW
diode

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 0 0 0 x x x 0 0 0 1 0

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Hierarchal Vncap marker


APMOM Marker
5V LDMOS
RF HCVNCAP
RF Well diode
MIM marking layer
MIM Top Plate
MIM Bottom Plate
Rflin marking layer
transmis marking layer
RF FET Marking
RF Marking
RF FET Marking

NFET-in-N-well Capacitor
PFET-in-P-well Capacitor
Highly Resistive Substrate
Electrical PC Fuse
Bipolar Transistor
ESD Implant
N-well Resistor
N-well over Active Resistor
Polysilicon Resistor
Diffusion Resistor
Salicide Poly Resistor
Salicide Diffusion Resistor
Tie Down Diode Marker
SRAM Cell Marker
SRAM Marker
Pass Gate
ESD Marker

Polysilicon
Medium Oxide
Thick Oxide
Zero-Vt
Medium-Oxide Voltage
Thick-Oxide Voltage
Overdrive Voltage
Vertical PNP Device
N+ S/D Implant
P+ S/D Implant
Silicide Block

High-Vt

Active Area
N-Well
N-band for isolated P-well
Low=Vt

[YI-DM00085]
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RX
NW
T3
LVT_OR2
XW
LW
HVT_OR2
NR
PR
PC
EG
DG
ZVT
EGV
DGV
OVERDRIVE
VPNP
JX
JZ
OP
SBLK
NCAP_OR VAR3
PCAP_OR VAR3
BFMOAT
EFUSE
BIPOLAR
ED
NWRES
BPNWR
PRES
DRES
POLY_SAL
DIFF_SAL
TIEDOWN
CELLSNR
RF_SRAM
AD
ESD_xxx1
ESDSCR_HBM
RXEXCLUD
HCVNCAP
VNCAPHV
5VHVFET
VNCAP2
DIODE
MIM_NI
HT
QT
LBTRANS
TRANSMIS
M1_BLKPEX
OUTLINE_RF
CHRT_RFFET

Structure

Spec ID:
Revision:
Page:

ESD SCR

1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x 0 0 0 0 0 x x x 0 0 0 1 0

ESD SCR T3

1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x 0 0 0 0 0 x x x 0 0 0 1 0

ESD vertical
PNP bipolar
ESD vertical
NPN bipolar T3

1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 0 0 0 x x x 0 0 0 1 0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 x 0 0 0 0 0 x x x 0 0 0 1 0

Singlecpw

x x x x x x x x x x x x x x x x x x x x x x x x 0 x x 0 0 x x x x x x x x 0 0 x 0 0 x 0 0 x x x 0 1 0 1 0

Couplecpw

x x x x x x x x x x x x x x x x x x x x x x x x 1 x x 0 0 x x x x x x x x 0 0 x 0 0 x 0 0 x x x 0 1 0 1 0

Singlewire

x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 x x x x x x x x 0 0 x 0 0 x 0 0 x x x 0 1 0 1 0

Couplewire

x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 x x x x x x x x 0 0 x 0 0 x 0 0 x x x 0 1 0 1 0

rfline

x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 x x x x x x x x 0 0 x 0 0 x 0 0 x x x 0 1 0 1 0

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[YI-DM00085]
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Table 8-2. Data preparation Truth Table

Open

Open

Open

Open

Open

Open

Open

JP

NV

PV

GN Open

Open

JN

GP

DE

DF

ZP

DG Blocked

OP

SM Open

SMT Strain

Open
IP

Silicide

Open
IN

Blocked

Open
PR

Thick-oxide

Open
NR

Polysilicon

Open
CV

Thick-oxide

Medium-oxide

Blocked
BV

SRAM

DG/IO

EG/IO

LW Open

High-Vt

Regular-Vt

XW Open

Low-Vt

N3

Regular-Vt
NFET

Regular-Vt
PFET

1.8V HSIO
NFET

1.8V HSIO
PFET

1.5V HSIO
NFET

Open

NW Open

Blocked

Halo/Extension Implant

BF

Device

Well Implant

Vt Adjustment Halo Implant

Low-Vt NFET

Low-Vt PFET

High-Vt NFET

High-Vt PFET

AD NFET

AD PFET

GLOBALFOUNDRIES Confidential

Spec ID:
Revision:
Page:

Open

Open

Open

Open

Open

Open

Open

JP

NV

PV

GN Open

Open

JN

GP

DE

DF

ZP

DG Blocked

OP

SM Open

SMT Strain

Open
IP

Silicide

Open
IN

Blocked

Open
PR

Thick-oxide

Open
NR

Polysilicon

Open
CV

Thick-oxide

Medium-oxide

Blocked
BV

SRAM

DG/IO

EG/IO

LW Open

High-Vt

Regular-Vt

XW Open

Low-Vt

N3

1.5V HSIO
PFET

1.8V DG I/O
NFET

1.8V DG I/O
PFET

2.5V DG I/O
NFET

2.5V DG I/O
PFET

3.3V DG I/O
NFET

3.3V DG I/O
PFET

Triple-well
NFET T3

N+ junction
T3

N+ tie down
diode

N+ tie down
diode T3

Open

NW Open

Blocked

Halo/Extension Implant

BF

Device

Well Implant

Vt Adjustment Halo Implant

[YI-DM00085]
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N+ junction

GLOBALFOUNDRIES Confidential

Spec ID:
Revision:
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Open

Open

Open

Open

Open

Open

Open

JP

NV

PV

GN Open

Open

JN

GP

DE

DF

ZP

DG Blocked

OP

SM Open

SMT Strain

Open
IP

Silicide

Open
IN

Blocked

Open
PR

Thick-oxide

Open
NR

Polysilicon

Open
CV

Thick-oxide

Medium-oxide

Blocked
BV

SRAM

DG/IO

EG/IO

LW Open

High-Vt

Regular-Vt

XW Open

Low-Vt

N3

P+ tie down
diode

Triple-well
contact T3

Medium-oxid
e NCAP

Thick-oxide
NCAP

Medium-oxid
e PCAP T3

Thick-oxide
PCAP T3

Hyper-abrupt
Varactor

Open

NW Open

Blocked

Halo/Extension Implant

BF

Device

Well Implant

Vt Adjustment Halo Implant

[YI-DM00085]
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N-well contact
Substrate
contact

P+ junction

Inductor
Hierarchal
VNCAP

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Spec ID:
Revision:
Page:

Open

Open

Open

Open

Open

Open

Open

JP

NV

PV

GN Open

Open

JN

GP

DE

DF

ZP

DG Blocked

OP

SM Open

SMT Strain

Open
IP

Silicide

Open
IN

Blocked

Open
PR

Thick-oxide

Open
NR

Polysilicon

Open
CV

Thick-oxide

Medium-oxide

Blocked
BV

SRAM

DG/IO

EG/IO

LW Open

High-Vt

Regular-Vt

XW Open

Low-Vt

N3

Open

NW Open

Blocked

Halo/Extension Implant

BF

Device

Well Implant

Vt Adjustment Halo Implant

[YI-DM00085]
[14]
303 of 330

APMOM

MIM

eFuse

ESD NFET

ESD PFET
ESD
Triple-Well
NFET T3
ESD N+/PW
Diode

ESD SCR

ESD SCR T3
ESD vertical
PNP bipolar
ESD vertical
NPN bipolar
T3

Singlecpw

GLOBALFOUNDRIES Confidential

Blocked
Open
Open
Open
Open
Open
Open
Open
Open
Open

Open
Open
Open

CV
NR
PR
IN
IP
JN
JP
NV
PV

GN Open
Open

BV

GP
DE
DF
ZP

DG Blocked
OP

SM Open

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

rfline

GLOBALFOUNDRIES Confidential

SMT Strain

Silicide

Thick-oxide

Polysilicon

Thick-oxide

Medium-oxide

SRAM

DG/IO

EG/IO

High-Vt

Regular-Vt

Low-Vt

Well Implant
Vt Adjustment Halo Implant

Blocked

Open

LW Open

Blocked

XW Open

couplewire
N3

singlewire
NW Open

coulecpw
BF

Device

Spec ID:
Revision:
Page:
[YI-DM00085]
[14]
304 of 330

Halo/Extension Implant

Spec ID:
Revision:
Page:

[YI-DM00085]
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8.3 Physical Design Rules


8.3.1 Design Rules Abbreviations
Please refer to the section 3.1.

8.3.2 MIM Capacitor Design Rules


MIM is still under development, please contact with GLOBALFOUNDRIES technical representative.
The 40NM-LP technology offers Metal-insulator-metal (MIM) capacitor, which is built in the TEOS/FTEOS
dielectric below the UTM18x copper wiring layer. The MIM capacitor is formed by two metals (Ta), there are bottom
plate (QT) and top plat (HT). The immediate metal below last copper wiring layer (Culast-1 wiring level) is
prohibited to generate metal fill below MIM bottom plate (QT).
Table 8-3. MIM scheme
MIM Option Scheme
BEOL Option

10

11

12

5L1x_1T18x_LB

5L1x_1T6x_1T18x_LB

6L1x_1T6x_1T18x_LB

eSPL (LKMNOP)

B40015

B40011

B40042

Culast wiring level

3A

3A

3A

Last Via

3T

3T

3T

QT

QT

QT

HT

HT

HT

QE

QE

QE

M5

FA

FA

Stack

MIM capacitor
(Option)

Culast-1 wiring level

Figure 8-1. Cross section of MIM capacitor

Note: Customers should draw MxEXCLUD (Mx = Culast-1 wiring level) to prohibit metal fill beneath QT.

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Spec ID:
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[YI-DM00085]
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Table 8-4. MIM capacitor Design Rules


Rule

Notes

Description

Design

HCAP0

HT must be within QT

1.0

HCAP1b

HT maximum width

100.0

HCAP1c

HT maximum area (mm2)

0.01

HCAP2

HT minimum space and notch

1.72

HCAP2a

HT must be an orthogonal rectangle

HCAP3

3A over HT maximum width

1.8

HCAP3a

Minimum ratio of [Jx over HT) / [Jx over (QT not over HT)], where Jx = 3T

0.5

HCAP3b

Maximum ratio of [Jx over HT] / [Jx over (QT not over HT)], where Jx = 3T

1.5

HCAP4a

Jx minimum within HT, where Jx = 3T

0.6

HCAP4c

(Jx over HT) minimum space and notch, where Jx = 3T

0.6

HCAP4f

HT must touch at least two Jx polygons, where Jx = 3T

HCAP5c

HT minimum space to adjacent 3A (metal above).

0.72

QCAP0

QT must touch HT

QCAP1a

QT maximum width

105.0

QCAP1b

QT maximum area (mm2)

0.012

QCAP2

QT minimum space and notch

1.0

QCAP2a

QT must be an orthogonal rectangle

QCAP4a

Jx minimum within (QT not over HT), where Jx = 3T

0.72

QCAP4b

Jx minimum space to HT, where Jx = 3T

0.72

QCAP4c

(Jx over QT) minimum space and notch, where Jx = 3T

0.6

QCAP4f

(QT not over HT) must touch at least two Jx polygons, where Jx = 3T,

QCAP5b

QT minimum space to Mx, where Mx is 1x, 2x or 6x metal immediately below QT

0.72

QCAP5c

QT must be within Mx_EXCLUD, where Mx is 1x, 2x or 6x metal immediately below QT

0.0

QCAP5d

QT is prohibited over Mx, where Mx is 1x, 2x or 6x metal immediately below QT

Mx minimum density (%) within (size QT by 150um) where Mx is 1x, 2x or 6x metal


immediately below QT

10

QCAP6a

Notes:
1. GLOBALFOUNDRIES strongly recommends a grid design with horizontal and vertical 3A lines and a via at each intersection. The 3A lines
need not be equally spaced, but the line width must adhere to this rule.
2. The maximum size of HT is 100um x 100um, the maximum size of QT is 105um x 105um.
3. GLOBALFOUNDRIES strongly recommends to draw a wide support wire around QT in MLAST1x or MLAST6X layer below QT to
compensate the low metal density under QT for reaching 10% in a 150um x 150um checking window.

GLOBALFOUNDRIES Confidential

Spec ID:
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Figure 8-2. MIM capacitor Design Rules

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Spec ID:
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Figure 8-3. Recommended MIM cell layout

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Spec ID:
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8.3.3 UTM18x Metal and Via Design Rule (Copper Inductor Design Rule)
This section description UTM18x Metal (3um thickness) and Via design rule. Designer can use 3T/3A for UTM18x
Metal and Via layout. Please contact with GLOBALFOUNDRIES technical representative.
Table 8-5. 3A and 3T Design Rules
Rule

Notes

Description

Design

UTM18x50

3T exact width and length.

0.36

UTM18x53a

3T minimum space.

0.34

UTM18x 53b

3T minimum space for vias on different nets.

0.44

UTM18x 53c

3T minimum space, when 3T has three or more neighbors.

0.54

UTM18x 57

3T must be an orthogonal rectangle.

UTM18x 60

3T not (HT or QT) must be within the metal below (that is MLAST1x or MLAST6x).

0.02

UTM18x 60a

3T not (HT or QT) must be within the metal below (that is MLAST1x or MLAST6x) on two
opposite sides with the other two sides 0.020 um.

0.08

UTM18x 61a

3T must be within 3A.

0.1

UTM18x 72aR

[(MLAST1X or MLAST6x) and 3A intersections touching 3T] must have at least two 3T vias.

{[(MLAST1X or MLAST6x) and 3A intersections)] touching 3T]} must have at least [(Two 3T
vias with
{[(MLAST1X or MLAST6x) and 3A intersections)] touching 3T} must have at least 2 3T vias if
3.0 um,
and area > 30.0 um2)

UTM18x 72fR

UTM18x 72iR

UTM18x 90

3TBAR exact width.

0.4

UTM18x 90a

3TBAR minimum length.

1.2

UTM18x 91

3TBAR minimum space

1.2

UTM18x 91a

3TBAR minimum space to 3T with touching prohibited.

1.2

UTM18x 93

3TBAR must be within (crack-stop ring, GUARDRNG, or IND).

UTM18x 00

3A minimum width.

UTM18x 00b

3A maximum width.

25

UTM18x 01a

3A minimum area (um ).

UTM18x 02

3A minimum space and notch.

UTM18x 04a

3A minimum space to (3A with width > 6 um) for run length >0.

2.0

UTM18x 04b

(3A with width > 6 um) minimum space and notch for run length >0.

2.8

UTM18x 11

3A vertex minimum within IND.

UTM18x 12

(CHIPEDGE touching OA) touching 3A is prohibited.

Notes:
1. Exact length and width requires 3T to be an orthogonal rectangle.
2. This rule is covered by the grid check (Rule S1), the acute angle check (Rule S6), and the exact width and length via check.

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Figure 8-4. UTM18x Metal and Via Design Rule

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8.4 Design for Manufacturability


Please refer to the section 4.

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8.5 Device Electrical Parameters


8.5.1 Available Devices
Table 8-6. Available RF Field-Effect Transistors
FET Name

Model
Name

VDD (V)

LDesmin (m)

Unique Design Levels1

Tox_eq (nm)

Regular-Vt NFET

nfet_rf

1.1

0.040

1.8

JX

Regular-Vt PFET

pfet_rf

1.1

0.040

1.8

NW,JZ

Low-Vt NFET

lvtnfet_rf

1.1

0.040

1.8

JX, LVT

Low-Vt PFET

lvtpfet_rf

1.1

0.040

1.8

NW,JZ,LVT

High-Vt NFET

hvtnfet_rf

1.1

0.040

1.8

JX, HVT

High-Vt PFET

hvtpfet_rf

1.1

0.040

1.8

NW, JZ,HVT

1.5V HSIO NFET (28A)

egvnfet_rf

1.5

0.100

2.8

EG, JX

1.5V HSIO PFET (28A)

egvpfet_rf

1.5

0.100

2.8

NW, EG, JZ

1.8V HSIO NFET (28A)

egnfet_rf

1.8

0.150

2.8

EG, JX

1.8V HSIO PFET (28A)

egpfet_rf

1.8

0.150

2.8

NW. EG, JZ

1.8V Medium-oxide 5V LDNMOS

egldnfet_rf

1.8

0.150

2.8

EG, JX, 5VHVFET

1.8V Medium-oxide 5V LDPMOS

egldpfet_rf

1.8

0.150

2.8

NW. EG, JZ, 5VHVFET

1.8V I/O NFET dgv

dgvnfet_rf

1.8

0.250

5.2

DG, JX, DGV

1.8V I/O PFET dgv

dgvpfet_rf

1.8

0.250

5.2

NW, DG, JZ, DGV

2.5V I/O NFET

dgnfet_rf

2.5

0.270

5.2

DG, JX

2.5V I/O PFET

dgpfet_rf

2.5

0.270

5.2

NW, DG, JZ

2.5V Thick-oxide 5V LDNMOS

dgldnfet_rf

2.5

0.270

5.2

DG, JX, 5VHVFET

2.5V Thick-oxide 5V LDPMOS

dgldpfet_rf

2.5

0.270

5.2

NW, DG, JZ, 5VHVFET

3.3V I/O NFET overdrive

dgxnfet_rf

3.3

0.550

5.2

DG, JX, OVERDERIVE

3.3V I/O PFET overdrive

dgxpfet_rf

3.3

0.440

5.2

NW, DG, JZ, OVERDRIVE

3.3V Thick-oxide 5V LDNMOS

dgxldnfet_rf

3.3

0.550

5.2

3.3V Thick-oxide 5V LDPMOS

dgxldpfet_rf

3.3

0.440

5.2

DG, JX, 5VHVFET,


OVERDRIVE
NW, DG, JZ, 5VHVFET,
OVERDRIVE

Notes:
1. Additional masks beyond the base feature-required front-end-of-line (FEOL) levels (that is, RX, NW, ZP, PC, PH, BH, TJ, JX and JZ).
2. Higher HC degradation is expected on larger pitch (>440nm) for DGPFET for the same minimum Ldes.

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Table 8-7. Other Available Devices
Device Name

Unique Design Levels1

Model Name

Capacitors
Thin-oxide NCAP

ncap_rf

NCAP

Medium-oxide NCAP

egncap_rf

EG, NCAP

Thick-oxide NCAP

egncap_rf

DG, NCAP

Thin-oxide PCAP

pcap_rf

PCAP

Medium-oxide PCAP

egpcap_rf

EG, PCAP

Thick-oxide PCAP

dgpcap_rf

DG, PCAP

HCVNCAP

hcvncap_rf

HCVNCAP

MIM Cap (std nitride)

mimcap

MIM_NI, QT, HT

RF ESD Vertical PNP BiPolar

esdvpnp_rf

ESD_xxx3

RF ESD Vertical NPN BiPolar

esdvnpn_rf

ESD_xxx3

RF ESD N+ Junction

esdndsx_rf

ESD_xxx3

RF ESDSCR Dual Well Version

esdscr_dw_rf

ESD_xxx3

RF ESDSCR Triple Well Version

esdscr_tw_rf

ESD_xxx3

ESD

Inductor (all inductors support all stacks except where otherwise noted)
native Cu spiral inductor(6x)

indp

IND

analog metal spiral inductor (3um)

indp

IND

native Cu symmetric inductor (6x)

symindp

IND

analog metal symmetric inductor (3um)

symindp

IND

bodpad

Stacked Transformer

stackedxformer

Interleave Transformer

interxformer

Balun

balun

Single RC wire

single_rc

TRANSMIS

Coupled RC wire

coupled_rc

TRANSMIS

Single Coplanar WG

singlecpw

TRANSMIS

Coupled Coplanar WG

coupledcpw

TRANSMIS

rfline

rfline

LBTRANS

Single Microstrip (modeling and pcells)

singlewire

Double Microstrip (modeling and pcells)

coupledwires

Triple-Well NFET Low-Vt

Triple-Well NFET Regular-Vt

Triple-Well NFET High-Vt

Misc
WB bondpad
Transformer

Wire Models

Triple Well FETs (No additional models required)

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Device Name

Unique Design Levels1

Model Name

Triple-Well 1.8V HSIO NFET

Triple-Well 1.8V NFET dgv

Triple-Well 2.5V NFET

Triple-Well 3.3V NFET overdrive

Notes:
3. ESD_xxx is defined as either ESD_HBM or ESD_CDM

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8.5.2 Metal-Insulator-Metal (MIM) Capacitor


Table 8-8. Electrical Parameters for MIM capacitor

Parameter
CA

Definition
Area component of capacitance

Units
fF/um2

2.5

CP

Perimeter component of capacitance

fF/um

0.306

Rs_bot

Sheet resistance of bottom plate

/sq

TBD

Rs_top

Sheet resistance of top plate

/sq

TCC1

Linear Temperature Coefficient

Value

TBD
o

ppm/ C
o

42.9

TCC2

Quadratic Temperature Coefficient

ppm/ C

-0.01033

VCC1

Linear Voltage Coefficient

ppm/V

12.17

VCC2

Quadratic voltage coefficient

ppm/V

BV

Breakdown voltage

Note:
unit capacitance calculation base on device draw size with 10% shrink down.
Unit capacitance = total capacitance/(draw_width *0.9*draw_length*0.9) (fF/um2)

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8.5.3 Wiring Resistor Model


Table 8-9. Via resistances

Level
3T (Via to 3A
in TEOS)

Via Height
(um)
0.6800.11
84

Via Diameter
(at via bottom)
(um)

Minimum
Resistance
(/via)

Nominal
Resistance
(/via)

Maximum Resistance
Single Via

Multiple Vias

0.3240.0867

0.15

0.35

0.55

0.90

TCR
(1/C)
0.00135

Table 8-10. Wire resistances in an Array of Minimum Width, Minimum Space wires at 25C
Metal Level

Wire Resistance per Unit Length


( /um)

3A (3um Metal in TEOS)

0.0031

Wire Resistance Tolerance


/um
0.0007

Percent (%)
18.0

Table 8-11. BEOL sheet resistance and film thickness

Level

3A (Single
Damascene
18x inductor
thick wiring in
TEOS)

Wphys
per Edge
(um)

Wel per
Edge
(um)

W0 (must
be > um)

Wlimit
(must be
> um)

-0.035

N/A

N/A

Minimum
Line
Width
and
Toleranc
e
1.950
0.263

Thickness
(um)

3.30
0.3687

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Tel
Total
(um)

Sheet
Resistance,
RS (/sq.)

-0.04

0.0050
0.0010

TCR
(1/C)

0.003

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Appendix A. General Introduction


40nm-LP design rule is based on 40nm technology node. The customer is designing at 45nm
(drawn design level) but actual silicon will be at 40nm geometry through a 10% optical shrink on
the mask data.

Please refer / confirm with the GLOBALFOUNDRIES representative before


using the Design Manual.

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Appendix B. Design Flow for Tapeout to 40nm-LP


B.1 Design methodology
Designers must evaluate the following items and it is the designers responsibilities to make
sure that design simulation and physical verification is validated before delivery to foundry. Initial
design must be layout on 1nm grid.
Design Flow

Chip Specification

Schematic Capture

45nm Level

Pre-Layout Simulation
- 40nm models

45nm GDS
- CDL: 45nm

Physical Verification - DRC/LVS


LPE/RCX -> PLS
- RC Models : 40nm
- Post Layout Simulation : 40nm models

CAD2Mask 0.9X Shrink

40nm Level

Customer

Foundry

40nm Tapeout

B.1.1 Design flow

All IP libraries are required to run timing and power characterization with the provided 40nm-LP spice
models(with embedded scaling factor) to evaluate the impact on device performance.

BEOL RC delay impact analysis is also required. PEX extraction decks (with embedded scaling factor) are
provided as part of the kit package. Please refer to 40nm-LP design manual BEOL section for details.

For specific BEOL stack support, please refer to 40nm-LP design manual.

To ensure design functionality and manufacturing margin, designers need to perform full-chip timing and
power analysis after incorporating of 40nm-LP library timing models and interconnect RC. Any timing/EM
violations that arise should be fixed.

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Appendix C. Designer Guidelines


Layout is drawn at 40nm-LP design rules, while models and parasitic extraction models (PEX)
are developed to reflect 40nm effects.

C.1 Guideline to usage of SPICE Model


40nm logic and SRAM models are provided by foundry, which can be used for circuit pre-layout
simulation and post-layout simulation, verification and re-timing.
1) Design migration: At pre-layout simulation stage, shrink factor must be implemented in
the SPICE model in order to scale the dimension in the netlist since the netlist device size
is in 45nm dimension (etc. drawn layout dimension). At post-layout simulation stage, LVS
will extract device size based on layout dimension and PEX will take care of parasitic
extraction scaling. The device dimension is still in 45nm dimension, but parasitics is
extracted based on 10% shrunk layout. As a result, shrink factor =0.9 should be added in
the model for the scaling of the device geometry in the 45nm netlist for 40nm simulation.
With this extraction flow, both pre-layout simulation and post-layout simulation scale
settings are the same. Thus, it is easier for design integration and LVS back-annotation
for debugging.
2) Since the SPICE model has included scaling function within the model, the netlist should
not have option scale statement in order to avoid double shrink.

C.1.1 SPICE syntax for scaling (HSPICE only)


This section shows the example of the scaling syntax in SPICE model:
param
+ shrink_factor = 0.9
+ sg_comp = 4e-9
~
.subckt nfet 1 2 3 4 w=0 l=0 as=0 ad=0 ps=0 pd=0 nrd=0 nrs=0
+ sa=0 sb=0 sd=0 sca=0 scb=0 scc=0
~
* *_scale parms are used in subckt in place of l, w, as, ad, ps, pd, sa, sb, and sd
.param l_scale='l*shrink_factor + 4e-9 * (shrink_factor == 0.9 && l != 0)'
+
+

w_scale='w*shrink_factor'
as_scale='as*shrink_factor*shrink_factor - w_scale*(4e-9/2)*(shrink_factor == 0.9 && as != 0)'

+
+

ad_scale='ad*shrink_factor*shrink_factor - w_scale*(4e-9/2)*(shrink_factor == 0.9 && ad != 0)'


ps_scale='ps*shrink_factor - 4e-9*(shrink_factor == 0.9 && ps != 0)'

+
+

pd_scale='pd*shrink_factor - 4e-9*(shrink_factor == 0.9 && pd != 0)'


sa_scale='sa*shrink_factor - (4e-9/2)*(shrink_factor == 0.9 && sa != 0)'

sb_scale='sb*shrink_factor - (4e-9/2)*(shrink_factor == 0.9 && sb != 0)'

sd_scale='sd*shrink_factor - 4e-9*(shrink_factor == 0.9 && sd != 0)'


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~
main 1 2 3 4 nfet l=l_scale w=w_scale ad=ad_scale as=as_scale pd=pd_scale ps=ps_scale nf=nf
+ nrd=nrd nrs=nrs dtemp=dtemp sa=sa_scale_f sb=sb_scale_f sd=sd_scale_f
~
.ends nfet

C.2 PEX Extraction Guideline


Designers perform parasitic extraction as per their normal design flow. No additional scaling
switches or options need to be applied during runtime. Scaling command is embedded in PEX
runset. Scaling will only apply to the parasitic RC effects, device parameters will not be scaled.
Designer must assess RC delay impact (40nm-LP RC layout extraction)

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Appendix D. Design Hierarchy Guidelines


Following the guidelines below can significantly reduce hierarchical verification run time and debugging effort.
1. Ignoring these guidelines can adversely impact mask processing and data preparation turnaround.
2. Reuse as many circuits as possible in your design. For example, if a two-way NAND gate is needed, reuse
one that is already designed, if possible.
3. Place all the shapes that comprise a circuit in the same cell. For example, do not create transistors by
bumping polysilicon (PC) from over RX in one cell to over RX in another cell. Place the NW and JX shapes
in the cell where the transistors are formed.
4. Confirm that the design rules are followed correctly in each cell. For example, do not place contacts in a
cell without metal covering them.
5. When necessary, intrude on a lower cell (as low in the hierarchy as possible). For example, do not use the
top (prime) cell to program decoders. Place programmed decoders in the next highest level of hierarchy.
6. Strive for rectangular-shaped circuits. L-shaped circuits have multiple intrusions that slow down the
checker.
7. Do not make any changes in the prime cell that impact transistor width, length, or connectivity in the bottom
cell.
8. Build large hollow structures, like substrate rings that intrude on the entire chip, by placing four cells (for
example, top, left, right, and bottom) in the prime cell. In this structure, there is no interference from any
shapes other than those nearby.
9. Avoid using special characters in cell names. Use alphanumeric (az and 09) cell names, level names,
and port names. Always begin the name with an alphabetic character.
10. Make wiring connections as low in the hierarchy as possible. The closer a connection is to the prime cell,
the more difficult it is to debug.
11. Avoid hierarchy holding levels, where only transformations but no actual shapes occur. Some design
tools will spend time trying to resolve shapes where none exist.
12. Avoid too much hierarchy. For example, do not design a circuit with each shape residing in its own cell.
13. Output only one prime cell.
14. Nest each large discrete design component, such as a cache or floating-point unit, as an individually
named model, especially if the structure occupies a large fraction (20% or more) of the chip. Also nest
repeated subunits of large discrete design components as individually named models.
15. Avoid overlapping large models. For example, do not use overlapping registration marks to align models.
2
16. For large chips (> 200 mm ), provide preliminary design data for mask processing a soon as it is available.

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Appendix E. Definitions of Process-Related Terms


BEOL

Back end of line; all processing steps for metal and via levels starting with M1.

Bias

The difference between the nominal wafer dimension and the design dimension: Bias
= Wafer Nominal Design Dimension.

bias si0gn

A positive bias means that the dimension of the image on the wafer is larger than the
corresponding design shape. A negative bias means that the dimension of the image
on the wafer is smaller than the corresponding design shape.

design minimum

The minimum design dimension permitted by photo, etch, fill, and electrical considerations. This is the design minimum given in the design rules in Section 3 Physical
Design Rules.

far BEOL

Far back end of line; the processing steps for wire-bond pads and flip-chip
packages.

FEOL

Front end of line; all processing steps up to and including contacts.

FIT

Failure in time; the number of failures per 10 device hours.

Foreshortening

When a more negative bias exists at the end of a narrow line than at the sides.

Hole

Where the resist is removed by the photo process.

Island

Where the resist remains after the photo process.

net bias and tolerance

The bias and tolerance used in physical design rules. For bias, this is the algebraic sum
of the component biases. For tolerance, this is the root-sum-square (RSS) of the
component tolerances. Components include photo, etch, slope, and film thickness.

SER

Soft-error rate.

Tolerance

Variation in the process gives rise to variation in the feature dimension specified in the
design rule tables. The extent of this variation above or below the nominal is called the
tolerance. Tolerance as used in this document means net tolerance. The tolerance
specified in this document is a 3 value. For calculating design rules, this tolerance is
multiplied by 4/3 to arrive at a 4 value, which is approximated to be the 4.5 for a
batch population used in the Motorola 6 methodology.

total bias

Same as net bias.

wafer nominal

The nominal or target dimension of a design shape as measured on the wafer.

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Appendix F. Design Services Design Rules


GLOBALFOUNDRIES Tapeout Center performs design services as a standard part of the 40nm-LP tape-out and
release process.
Note

This appendix is for information only; not for designers use.

Table C-1. RXFILL and PCFILL Rules


Rule

Notes

Description

Design

DS100

RXFILL must not touch (RXFILL, RX, PC, RXEXCLUD, PCFUSE, LOGOBND, PROTECT,
KERFEXCL, RXING)

DS101

RXFILL space to (RX, RXING)

0.640

DS102

RXFILL space to (PC, RXEXCLUD, LOGOBND, PROTECT, KERFEXCL)

0.200

DS104

RXFILL space to PCFUSE

3.000

DS105

RXFILL space

0.200

DS106

[RXFILL not touching (BFMOAT, IND)] exact width

0.400

DS108

[RXFILL touching (BFMOAT, IND)] exact width

0.400

DS110

RXFILL within NW

0.240

DS111

RXFILL space to NW

0.240

DS199

RXFILL must be within CHIPEDGE

0.000

DS200

PCFILL must not touch (PCFILL, RX, PC, PCEXCLUD, PCFUSE, LOGOBND, PROTECT,
KERFEXCL, PCING)

DS201

PCFILL space to (PC, PCING)

0.640

DS202

PCFILL space to (RX, PCEXCLUD, LOGOBND, PROTECT, KERFEXCL)

0.200

DS204

PCFILL space to PCFUSE

3.000

DS205

PCFILL space

0.280

DS206

[PCFILL not touching (BFMOAT, IND)] exact width

0.320

DS208

[PCFILL touching (BFMOAT, IND)] exact width

0.400

DS213

xxFILL must be square, where xx = RX of PC

DS299

PCFILL must be within CHIPEDGE

0.000

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Table C-2. Metal Fill Rules


Rule

Notes

Description

Design

DS500

MxFILL must not touch (MxFILL, Mx, MxEXCLUD, LOGOBND, PROTECT, KERFEXCL),
where Mx = M1 - M7, BA, BB, BD, BE, BG, FA, FB, LB

DS502

MxFILL space to PCFUSE with touching prohibited, where Mx = M1, M2

3.000

DS503

MxFILL space to K1 with touching prohibited, where Mx = M1, M2

0.750

DS504

MxFILL must not touch MxING, where Mx = M1- M7

DS511

MxFILL space to (Mx, MxING), where Mx = M1- M7

0.414

DS512

MxFILL space to (MxEXCLUD, LOGOBND, PROTECT, KERFEXCL), where Mx = M1 M7

0.200

DS515

MxFILL space, where Mx = M1 M7

0.200

DS516_or

Either DS516a or DS516b must be satisfied

DS516a

(MxFILL not touching IND) exact width, where Mx = M1 M7

0.400

DS516b

(MxFILL not touching IND) exact width, where Mx = M1 M7

0.234

DS518

(MxFILL touching IND) exact width, where Mx = M1 M7

0.270

DS521

0.480

DS522

0.320

DS524

DS525

0.400

0.800

0.540

BxFILL space to (Bx, BxING), where Bx = B1 B4, BA, BB, BD, BE, BG.
LxFILL space to (Lx, LxING), where Lx = L1 L4
BxFILL space to (BxEXCLUD, LOGOBND, PROTECT), where Bx = B1 B4, BA, BB, BD, BE,
BG.
LxFILL space to (LxEXCLUD, LOGOBND, PROTECT), where Lx = L1 L4
BxFILL must not touch BxING, where Bx = B1 B4, BA, BB, BD, BE, BG.
LxFILL must not touch LxING, where Lx = L1 L4
BxFILL space, where Bx = B1 B4, BA, BB, BD, BE, BG. LxFILL space, where Lx = L1 L4
(BxFILL not touching IND) exact width, where Bx = B1 B4, BA, BB, BD, BE, BG.
(LxFILL not touching IND) exact width, where Lx = L1 L4
(BxFILL touching IND) exact width, where Bx = B1 B4, BA, BB, BD, BE, BG.
(LxFILL touching IND) exact width, where Lx = L1 L4

DS526

DS527

DS561

FxFILL space to Fx, where Fx = FA, FB

1.600

DS562

FxFILL space to (FxEXCLUD, LOGOBND, PROTECT, KERFEXCL), ,where Fx = FA, FB

1.600

DS565

FxFILL space, where, Fx = FA, FB

1.600

DS566

(FxFILL not touching IND) width exact, where Fx = FA, FB

3.200

DS567

(FxFILL touching IND) width exact, where Fx = FA, FB

2.160

DS581

UxFILL space to Fx, where Ux = UA, UB

1.600

DS582

UxFILL space to (UxEXCLUD, LOGOBND, PROTECT, KERFEXCL), where Ux = UA, UB

1.600

DS585

UxFILL space, where, Ux = UA, UB

1.600

DS586

(UxFILL not touching IND) width exact, where Ux = UA, UB

3.200

DS587

(UxFILL touching IND) width exact, where Ux = UA, UB

2.160

DS591

LBFILL space to LB

2.560

DS592

LBFILL space to (LBEXCLUD, LOGOBND, PROTECT, KERFEXCL)

2.560

DS593

LBFILL space to IND with touching prohibited

2.560

DS595

LBFILL space

3.200

DS596

LBFILL exact width

6.400

DS598

xxFILL must be square, where xx = all metal levels

DS599

xxFILL must be within CHIPEDGE, where xx = all metal levels

0.000

DSRF561

3AFILL minimum space to 3A.

4.8

DSRF562

3AFILL minimum space to (3AEXCLUD, KERFEXCL, LOGOBND, PROTECT).

2.4

DSRF565

3AFILL minimum space.

2.4

DSRF566

3AFILL not touching IND exact width.

7.2

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DSRF568
DSRF581

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Description

Design

3AFILL touching IND exact width.

4.16

MxFILL minimum space to QT with touching prohibited, where Mx = Culast-1 wiring level =
metal level immediately below last copper wiring level.

0.8

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Table C-3. Via Fill Rules


Rule

Description

Design

DS700

VxFILL must not touch (VxFILL, VxEXCLUD, LOGOBND, PROTECT, KERFEXCL, VxING), where Vx =
V1 V5, W0 W3, J0 J3

DS711

VxFILL must be within MxFILL, where Vx = V1 V5 and Mx = metal level below Vx

0.065

DS712

VxFILL must be within MyFILL, where Vx = V1 V5 and My = metal level above Vx

0.065

DS713

VxFILL space, where Vx = V1 V5

0.130

DS714

VxFILL exact width, where Vx = V1 V5

0.070

DS715

VxFILL space to VxING, where Vx = V1 V5

0.480

DS721

WxFILL must be within BxFILL, where Wx = W1 W3 and Bx = metal level below Wx.
JxFILL must be within LxFILL, where Jx = J1 J3 and Lx = metal level below Jx.

0.130

DS722

WxFILL must be within ByFILL, where Wx = W1 W3 and By = metal level above Wx.
JxFILL must be within LyFILL, where Jx = J1 J3 and Ly = metal level above Jx.

0.130

DS723

WxFILL space, where Wx = W0 W3, JxFILL space, where Jx = J0 J3

0.260

DS724

WxFILL exact width, where Wx = W0 W3. JxFILL exact width, where Jx = J0 J3

0.140

DS725

W0FILL must be within MxFILL, where Mx = MLAST1X = metal level below W0.
J0FILL must be within MxFILL, where Mx = MLAST1X = metal level below J0.

0.030

DS726

WxFILL space to WxING, where Wx = W0 W3


JxFILL space to JxING, where Jx = J0 J3

0.480

DS798

xxFILL must be square, where xx = V1 V5, W0 W3

DS799

xxFILL must be within CHIPEDGE, where xx = V1 V5, W0 w3

0.000

Table C-4. Local Pattern Density Rules


Rule

Notes

Description

Design

DS911

Density (RX, RXFILL) with 125 m tiling within CHIPEDGE


Exemptions : tile touching (LOGOBND, PROTECT, IND)

20%

DS921D

Density (PC, PCFILL) with 125 m tiling within CHIPEDGE


Exemptions : tile touching (LOGOBND, PROTECT, IND)

15%

DS922

Density (PC, PCFILL) within CHIPEDGE

15%

DS953D

Density (Mx, MxFILL) with 100 m tiling within CHIPEDGE, where Mx = M1 M4, B1 B4, BA,
BB, BD, BE, BG, L1 L4, FA, FB, UA, UB
Exemptions : tile touching (LOGOBND, PROTECT, IND)

10%

DS954

Density (LB, LBFILL) within CHIPEDGE

30%

1. D rules DS921D and DS953D are treated as recommended rules, except they must be coded in DRC and violations must be reported to
the Waiver Review Board.

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Table F-5. Predicted Density (Page 1 of 3)


Reference Rule

Notes

Boolean Description

Where
A = rx_ds102 = [union (RXEXCLUD, PC, KERFEXCL, LOGOBND, PROTECT)] sized by +DS102
B = rx_ds101 = [union (RX, RXING)] sized by +DS101
C = rx_ds104 = (PCFUSE sized by +DS104)
D = rx_nw_excl = difference (nw_ds111, nw_ds110)
nw_ds110 = [difference (NW, N3) sized by DS110]
nw_ds111 = [difference (NW, N3) sized by +DS111]
E = rx_bfm_x = difference [(BFMOAT sized by +DS102), (BFMOAT sized by DS102)]
F = rx_ind_x = difference [(IND sized by +DS102), (IND sized by DS102)]
DS40PD
1
G = rx_limit = (DS106 + I)
H = rx_slivr = I / 6
I = rx_pitch = [(DS106 + DS105)/3]
rx_fill_zone = difference {[CHIPEDGE sized by (DS102/2)], union (rx_no_fill, IND, BFMOAT)}
rx_fill_bfmoat = difference [(BFMOAT not over IND), rx_no_fill]
rx_fill_ind = difference (IND, rx_no_fill)
rx_no_fill = [union (A, B, C, D, E, F)]sized by G/2} sized by -(I/2 - H)
rx_predicted(T) = density (RX) + [0.40 density (rx_fill_zone)] + [0.20 density (rx_fill_bfmoat)] + [0.20
density (rx_fill_ind)]
Where
A = pc_ds202 = [union (PCEXCLUD, RX, KERFEXCL, LOGOBND, PROTECT)] sized by +DS202]
B = pc_ds201 = [union (PC, PCING) sized by +DS201]
C = pc_ds204 = (PCFUSE sized by +DS204)
E = pc_bfm_x = difference [(BFMOAT sized by +DS202), (BFMOAT sized by DS202)]
F = pc_ind_x = difference [(IND sized by +DS202), (IND sized by DS202)]
G = pc_limit = (DS206 + I)
DS42PD
1
H = pc_slivr = I / 6
I = pc_pitch = [(DS206 + DS205)/3]
pc_fill_zone = difference {[CHIPEDGE sized by (DS202/2)], union (pc_no_fill, IND, BFMOAT)}
pc_fill_ind = difference (IND, pc_no_fill)
pc_fill_bfmoat = difference {[(BFMOAT not over IND) sized by -DS202], pc_no_fill}
pc_no_fill = {[union (A, B, C, E, F)] sized by G/2} sized by -(I/2 - H)
pc_predicted(T) = density (PC) + [0.256 density (pc_fill_zone)] + [0.20 density (pc_fill_ind)] + [0.20
density (pc_fill_bfmoat)]
Where
A = Mx_ds512 = [union (MxEXCLUD, KERFEXCL, LOGOBND, PROTECT)] sized by +DS512
B = Mx_ds511 = [union (Mx, MxING)] sized by +DS511
C = Mx_ind_x = difference [(IND sized by +DS512), (IND sized by DS512)]
DS542a
D = Mx_502 = (PCFUSE sized by +DS502). G = Mx_limit = (DS516 + I)
DS543PD
H = Mx_slivr = I / 6
1, 2
DS642a
I = Mx_pitch = [(DS516 + DS515)/3]
DS643PD
Mx_fill_zone = difference {[CHIPEDGE sized by (DS512/2)], union (Mx_no_fill, IND)}
Mx_fill_ind = difference (IND, Mx_no_fill)
Mx_no_fill = {[union (A, B, C, D)] sized by G/2} sized by -(I/2 - H)
Mx_predicted(T) = density [union (Mx, MxING)] + [0.40 density (Mx_fill_zone)] + [0.091125 density
(Mx_fill_ind)]
Where
A = My_ds512 = [union (MyEXCLUD, KERFEXCL, LOGOBND, PROTECT)] sized by +DS512
B = My_ds511 = [union (My, MyING)] sized by +DS511
C = My_ind_x = difference [(IND sized by +DS512), (IND sized by DS512)]
G = My_limit = (DS516 + I)
DS642b
H = My_slivr = I / 6
1, 3
DS644PD
I = My_pitch = [(DS516 + DS515)/3]
My_fill_zone = difference {[CHIPEDGE sized by (DS512/2)], union (My_no_fill, IND)}
My_fill_ind = difference (IND, My_no_fill)
My_no_fill = {[union (A, B, C)] sized by G/2} sized by -(I/2 - H)
My_predicted(T) = density [union (My, MyING)] + [0.40 density (My_fill_zone)] + [0.091125 density
(My_fill_ind)]
1. T = tile size in microns for density calculations. All density calculations are tiled..
2. Mx = M1, M2
3. My = M3, M4, M5, M6, M7
4. Bx = B1, B2, B3, B4
5. Lx = L1, L2, L3, L4
6. By = BA, BB, BD, BE, BG
7. Ex = EA, EB
8. Fx = FA, FB
9. Ux = UA, UB

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Table F-5. Predicted Density (Page 2 of 3)


Reference Rule

Notes

Boolean Description

Where
A = Bx_ds522 = [union (BxEXCLUD, KERFEXCL, LOGOBND, PROTECT)] sized by +DS522
B = Bx_ds521 = [union (Bx, BxING)] sized by +DS521
C = Bx_ind_x = difference [(IND sized by +DS530PD), (IND sized by DS529PD)]
G = Bx_limit = (DS526 + I)
DS2x42a
H = Bx_slivr = I / 6
1, 4
DS2x43PD
I = Bx_pitch = [(DS526 + DS525)/3]
Bx_fill_zone = difference [(CHIPEDGE sized by DS522), union (Bx_no_fill, IND)]
Bx_fill_ind = difference (IND, Bx_no_fill)
Bx_no_fill = {[union (A, B, C)] sized by G/2} sized by -(I/2 - H)
Bx_predicted(T) = density [union (Bx, BxING)] + [0.40 density (Bx_fill_zone)] + [0.091125 density
(Bx_fill_ind)]
Where
A = Lx_ds522 = [union (LxEXCLUD, KERFEXCL, LOGOBND, PROTECT)] sized by +DS522
B = Lx_ds521 = [union (Lx, LxING)] sized by +DS521
C = Lx_ind_x = difference [(IND sized by +DS530PD), (IND sized by DS529PD)]
G = Lx_limit = (DS526 + I)
DS2Ax42a
H = Lx_slivr = I / 6
1, 5
DS2Ax43PD
I = Lx_pitch = [(DS526 + DS525)/3]
Lx_fill_zone = difference [(CHIPEDGE sized by DS522), union (Lx_no_fill, IND)]
Lx_fill_ind = difference (IND, Lx_no_fill)
Lx_no_fill = {[union (A, B, C)] sized by G/2} sized by -(I/2 - H)
Lx_predicted(T) = density [union (Lx, LxING)] + [0.40 density (Lx_fill_zone)] + [0.091125 density
(Lx_fill_ind)]
Where
A = By_ds522 = [union (ByEXCLUD, KERFEXCL, LOGOBND, PROTECT)] sized by +DS522
B = By_ds521 = [union (By, ByING)] sized by +DS521
C = By_ind_x = difference [(IND sized by +DS530PD), (IND sized by DS529PD)]
G = By_limit = (DS526 + I)
DS2Bx42a
H = By_slivr = I / 6
1, 6
DS2Bx43PD
I = By_pitch = [(DS526 + DS525)/3]
By_fill_zone = difference [(CHIPEDGE sized by DS522), union (By_no_fill, IND)]
By_fill_ind = difference (IND, By_no_fill)
By_no_fill = {[union (A, B, C)] sized by G/2} sized by -(I/2 - H)
By_predicted(T) = density [union (By, ByING)] + [0.40 density (By_fill_zone)] + [0.091125 density
(By_fill_ind)]
Where
A = Ex_ds542 = [union (ExEXCLUD, KERFEXCL, LOGOBND, PROTECT)] sized by +DS542
B = Ex_ds541 = Ex sized by +DS541
C = Ex_ind_x = difference [(IND sized by +DS550PD), (IND sized by DS549PD)]
G = Ex_limit = (DS546 + I)
DS4x42a
1, 7
H = Ex_slivr = I / 6
DS4x43PD
I = Ex_pitch = [(DS546 + DS545)/3]
Ex_fill_zone = difference [(CHIPEDGE sized by DS542), union (Ex_no_fill, IND)]
Ex_fill_ind = difference (IND, Ex_no_fill)
Ex_no_fill = {[union (A, B, C)] sized by G/2} sized by -(I/2 - H)
Ex_predicted(T) = density (Ex) + [0.40 density (Ex_fill_zone)] + [0.091125 density (Ex_fill_ind)]
Where
A = Fx_ds562 = [union (FxEXCLUD, KERFEXCL, LOGOBND, PROTECT)] sized by +DS562
B = Fx_ds561 = Fx sized by +DS561
C = Fx_ind_x = difference [(IND sized by +DS562), (IND sized by DS562)]
G = Fx_limit = (DS566 + I)
DS6x42a
1, 8
H = Fx_slivr = I / 6
DS6x43PD
I = Fx_pitch = [(DS566 + DS565)/3]
Fx_fill_zone = difference {[CHIPEDGE sized by (DS562/2)], union (Fx_no_fill, IND)}
Fx_fill_ind = difference (IND, Fx_no_fill)
Fx_no_fill = {[union (A, B, C)] sized by G/2} sized by -(I/2 - H)
Fx_predicted(T) = density (Fx) + [0.40 density (Fx_fill_zone)] + [0.091125 density (Fx_fill_ind)]
1. T = tile size in microns for density calculations. All density calculations are tiled..
2. Mx = M1, M2
3. My = M3, M4, M5, M6, M7
4. Bx = B1, B2, B3, B4
5. Lx = L1, L2, L3, L4
6. By = BA, BB, BD, BE, BG
7. Ex = EA, EB
8. Fx = FA, FB
9. Ux = UA, UB

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Table F-5. Predicted Density (Page 3 of 3)
Reference Rule

Notes

Boolean Description

Where
A = Ux_ds582 = [union (FxEXCLUD, KERFEXCL, LOGOBND, PROTECT)] sized by +DS582
B = Ux_ds581 = Ux sized by +DS581
C = Ux_ind_x = difference [(IND sized by +DS582), (IND sized by DS582)]
G = Ux_limit = (DS586 + I)
DS10Bx42a
1, 9
H = Ux_slivr = I / 6
DS10Bx43PD
I = Ux_pitch = [(DS586 + DS585)/3]
Ux_fill_zone = difference {[CHIPEDGE sized by (DS582/2)], union (Ux_no_fill, IND)}
Ux_fill_ind = difference (IND, Ux_no_fill)
Ux_no_fill = {[union (A, B, C)] sized by G/2} sized by -(I/2 - H)
Ux_predicted(T) = density (Ux) + [0.40 density (Ux_fill_zone)] + [0.091125 density (Ux_fill_ind)]
Where
A = LB_ds592 = [union (FxEXCLUD, KERFEXCL, LOGOBND, PROTECT)] sized by +DS592
B = LB_ds591 = LB sized by +DS591
C = LB_ds593 = IND sized by +DS593
G = LB_limit = (DS596 + I)
DSLB43PD
1
H = LB_slivr = I / 6
I = LB_pitch = [(DS596 + DS595)/3]
LB_fill_zone = difference {[CHIPEDGE sized by (DS592/2)], LB_no_fill}
LB_no_fill = {[union (A, B, C)] sized by G/2} sized by -(I/2 - H)
LB_predicted(T) = density (LB) + [0.40 density (LB_fill_zone)]
1. T = tile size in microns for density calculations. All density calculations are tiled..
2. Mx = M1, M2
3. My = M3, M4, M5, M6, M7
4. Bx = B1, B2, B3, B4
5. Lx = L1, L2, L3, L4
6. By = BA, BB, BD, BE, BG
7. Ex = EA, EB
8. Fx = FA, FB
9. Ux = UA, UB

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Revision Log
This document is published by the GLOBALFOUNDRIES Semiconductor Manufacturing Ltd and is the property of
GLOBALFOUNDRIES Document distribution is restricted to authorized GLOBALFOUNDRIES employees and
GLOBALFOUNDRIES customers with current nondisclosure agreements. Use of this document is authorized only
for the design of GLOBALFOUNDRIES manufactured products.
Revision of Rev 14 as relevant to Rev 13 (December 2012)
Document
Revision
14

Paragraph(s) of Changed

Description of Change(s)

Table 2-3. Design Levels, Utility Levels,


and GDS Stream Layers

Add metal blockage layers which are used by IP

Table 2-9. Design Truth Table

Update design truth table


Add RXFILL and PCFILL columns

Table 3-6. PC Design Rules

Add note 9 for 119a

Table 3-18. JZ Design Rules

JZ382 change "PC" to "(PC over (OP or SBLK))"

Table 3-35. ESD Design Rules

Update ESD17a, ESD17b

Table 3-41. Mx and Vx Design Rules

Rule 642: Add Mx OR MxFILL into description

Figure 3-45. Explanation of exact


configurations applied to 613

Update the figure.

Table 3-42. 2x Metal Design Rules in


Low-K Dielectric

2Ax42a: Add Lx OR LxFILL into description

Table 3-44. 2x Metal Design Rules in


FTEOS Dielectric

2Bx42a: Add Bx OR BxFILL into description

Table 3-48. 6x Metal and Via Design


Rules

6x42: Add Fx OR FxFILL into description

Table 3-73. RXFILL, PCFILL Design


Rules

Update PCFILL205 value from 0.26 to 0.22

Table 3-74. MxFILL Design Rules

MXFILL511 update value from 0.48 to 0.458


MXFILL516 update value from 0.44 to 0.258

5. Device Electrical Parameters

Add statement

Table 5-2. Other Available Devices

Update Capacitors part with model name and Unique Design Levels

Table 5-3. Operating Voltages

Typo correct of VDD Tolerance (%)


From -10%/+20% to +/-10%

Table 5-29. Resistance of Minimum


Width, Minimum Space Wires at 25C

Add sheet resistance data

Table C-1. RXFILL and PCFILL Rules

Table C-2. Metal Fill Rules

DS100 add RXFILL into description


DS200 add PCFILL into description
DS500 add MxFILL into description
DS511 update value from 0.48 to 0.414
DS516 allow 2 dummy size, update value from 0.4 to 0.4 or 0.234

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