A HIGH DATA TRANSFER RATE FREQUENCY SHIFT KEYING

DEMODULATOR CHIP FOR THE WIRELESS BIOMEDICAL IMPLANTS
Mavsam Ghovanloo and Khalil Najafi
Center for Wireless Integrated Microsystems

University of Michigan, 1301 Beal Ave., Ann Arbor, Michigan 48109-2122, USA
Tel: (734) 763-6650, Fax: (734) 763-9324, maysamgh@,engin.umich.edu
ABSTRACT

So far, the amplitude shifl keying (ASK) data modulation
technique has been commonly used in the biomedical implants
because of its fairly simple modulation .and demodulation
circuitry However this method faces major limitations for high
bandwidth data transfer. Therefore, a novel high-rate data
transfer protocol and demodulator circuit has been proposed
based on the frequency shift keying (FSK) data modulation
technique for wirelessly operating the University of Michigan
micromachined 3D stimulating microprobes [I], shown in Fig. I ,
which are targeted at a 1024-site wireless stimulating
microsystem for visual and auditory prosthesis.

This paper describes a high-rate frequency shift keying
(FSK) data transfer protocol and demodulator circuit for
wirelessly operating biomedical implants in need of data transfer
rates above IMbitiSec. The demodulator circuit receives the
serial data bit stream from an FSK carrier signal in 2-2OMHz
range, which is used to power the implant through inductive
coupling. The circuitry has been desimed and fabricated in the
University of Michigan’s single metal, dual-poly 3-LIm CMOS
process and has been tested fully functional.

1. INTRODUCTION
Wireless operation is required for must of the biomedical
implantable circuits and many other emerging MEMS
applications to improve safety and enable stand-alone operation
for an unlimited time period. Many of these devices are powered
by inductive coupling in the centimeter range distance over the
skin barrier. Tne most convenient way to transfer data to these
devices is to combine it with the electromagnetic power carrier
signal. Some of the biomedical implants, particularly those who
are interfacing with the central nervous system like cochlear
implants, need to transfer large amount of data for real-time
signal processing and high quality sound perception. The visual
implant is another example, which needs even higher data rates
for transferring images with minimum reasonable resolution.
Therefore, a high data transfer rate interface circuitry that can
establish an efficient wireless link between the implant and the
external units is highly needed.

The FSK is one of the most useful modulation techniques
for digital communication, which simply means sending binary
data with two frequencies& andf,, representing digital “0” and
“1” respectively. The resultant modulated signal can he regarded
as the sum oftwo amplitude modulated (AM) signals of different
carrier frequencies as shown in Fig. 2a:

/ ( 1 ) = ~ ~ ( t ) s i n ( 2 ~ ~ ~ + 8 ) + ~ ~ ( t ) s i n ((1)2 ~ ~ ~ + ~ )
!n the frequency domain, the signal power is centered at two
carrier frequencies,fo andf,, as shown in Fig. 2b. Since/o(tj and
f,(r) can have the same amplitude, an excellent characteristic of
the FSK modulation for wireless biomedical implants, which
should be powered as well as communicated with the same
electromagnetic field is that the transmitted power is always
constant at its maximum level irrespective of& andfi or the data
contents:

0

I

I

0

0

1

0

DigitalSigna

(b) Frequency Domain

Fig. 1 A 3D probe array of256 stimulating sites.

0-7803-7523-8/02/$I7.00 02002 lEEE

Fig. 1 Frequency shifl keying in time and frequency domains.

111-433

This (b) R D m K Fig. Another difference between the FSK and ASK is that in the ASK data transmission. and the digital bit “ 0 is transmitted by two cycles of the carrier fo as shown in Fig.Referenced differential FSK demodulator (RDFSK): Generating a reference voltage and comparing it with a charging capacitor voltage as shown in Fig.5]. which is the main focus of this paper and implemented in the UofM 3pm CMOS process as shown in Fig. 2. 3. Therefore.Fully differential FSK demodulator (FDFSK): Charging two unequal capacitors with different currents and compare their voltages with a hysteresis comparator as shown in Fig. The FDFSK method is more robust against process To variations in expense of more power consumption. which is directlyrecovered from the FSK carrier by the clock recovery block. the receiver tank circuit frequency response should have a very high quality factor (Q). the current sources lLand IH linearly charge CLand CH up to VL and VH respectively.3b. Fig. THE FSK DATA TRANSFER PROTOCOL The data rate in digital communication.. any odd number of consecutive fa cycles in this protocol is an indication of data transfer error. is low. which is directly connected to the receiver coil and turns the sinusoidal FSK carrier signal into a similar square waveform. If the period is higher than a certain value.. A simple method for time measurement is charging a capacitor with a constant current source and monitoring its voltage. the pass band should be centered between fa and fi with a low Q to pass enough power of both carrier frequencies. 3 The FSK data detection techniques: (a) Fully Differential FSK (b) Referenced Differential FSK. DIFERRENTIAL FSK DEMODULATOR The data detection technique used here for the FSK demodulation is based on measuring the period of each received carrier cycle. When CK. This leads to a consistent data transfer rate of fi bits/Sec.centered at the carrier frequency to get enough amplitude variation for data detection. 2a. we desigmd a circuit based on the RDFSK method in the AMI 1Spm CMOS process through the M O S S foundry. During a digital “ I ” long cycle. h f. 4. In this method. so called FSK rate. Fig. a digital “ I ” bit is detected and otherwise a digital “ 0 is received. For this kind of applications. is hundreds oftimes slower thanf.. Because the receiver internal clock signal can be directly derived by stepping down the constant transmitter carrier frequency [4. every dozen of carrier cycles should transfer at least one or even more bits of data. or/. If the capacitor voltage is higher than a certain value. This cannot he the case if we want to surpass IMbiVSec baud rate in the wireless biomedical implants where the carrier frequency is limited to tens of MHz because of the incremental tissue loss and risk of tissue damage at higher frequencies. Therefore a new method was devised for the FSK data transfer with the FSK rate as high as fiwith j o twice as f. 5 shows a simplified schematic diagram of the FDFSK demodulator. The transminer frequency switches at a small fraction of a cycle and only at zero crossings. Another prototEe chip was designed based on the FDFSK method. This comparison can be done in two ways: I. SL and SH switches are open and SLC and SHCare closed.t This is a major advantage over the amplitude shift keyed (ASK) signals where data bits can alter power transfer efficiency parricularly when the modulation index is high as in suspended carrier modulation [2]. vn 2. Obviously. However. However. Both current sources and switches are controlled by the input clock signal (CK. This is an advantage for the FSK technique because in the biomedical implants application. the quality factor of the receiver coil is generally low particularly when the implant receiver coil is integrated and its high resistivity is unavoidable [3]. the internal clock with constant frequency should be derived from a combination of the two carrier frequencies and 6)based on the data transfer protocol or synchronization patterns. in the FSK data transfer. The clock recovery circuit is a cross-coupled differential pair. 3a. (a) PDFSK t Synchronization of the receiver with the transmitter is easier though in the ASK systems. the digital bit “I” is transmitted by a single cycle of the carrier/. experiment and compare both methods. is like comparing two capacitive timers with different time constants. a digital “1” hit is detected and otherwise a digital “ 0 is received. Charging and discharging of this capacitor should be synchronized with the FSK carrier signal. 4 The FDFSK prototype chip and its floor plan In-434 . in the FSK data transmission.).

The data detector.. whilefi andfo are set equal to lMHz and 2MHz respectively. The lower trace in all sections is the regenerated clock input (CK. All of these circuits were functioning as expected from the simulations up to IOOKbitisec.. 7a shows the resulting simulation waveforms. SL and SH switches discharge the capacitors in a fraction of the FSK 2& half cycle. Any odd number of short cycles is an indication of error according to the FSK protocol’and activates the error output signal. Fig. 4. Fig. trace-I shows the FSK detector output pulses. and digital blocks were tested both individually and together as an FSK data demodulator chip. 8 shows some of the measured waveforms. also resets the hysteresis comparator to prepare it for dktecting the type of the next cycle.. a T flip-flop indicates the number of successive zeros and another T flip-flop toggles an every long CKj.. clock regenerator. 7b shows CH and CL capacitor voltages in a scaled portion of the simulation waveforms. A hesteresis comparator compares capacitor voltages.. so it cannot be directly regarded as the received data bit stream. meanwhile SU. which discriminates between long and short FSK carrier cycles. the comparator output switches to highduring a digital “1” long cycle but not during a distal “0” shoti cycle. which was the highest FSK modulation rate of our signal generator. 8c shows the FSK data detector output pulses which discriminates between IMHz and 2MHz carrier cycles. SIMULATION AND MEASUREMENT RESULTS To check the performance of the FDFSK demodulator. postlayout simulation was performed with choosing& andjo to be 2. a 2-bit shift register shifts in the data-detector block output. 6 The FDFSK digital block schematic diagram. 2. CK. These pulses are fed into a digital block along with CK.nsUx 1 (b) Fig. TI is twice as To. and SHCswitches open to reduce power consumption.6 shows the schematic diagram of the digital block. The upper traces in Fig. The hysteresis window width.andVHO-VLO.-VL. when CK..). VLI and VHIare twice as V. cycles. Every 2 successive short cycles should be regarded as a “0” bit on DOUT and every single long cycle indicates a “1” bit.5MHz and 5MHz respectively. ‘Ile constant frequency clock (CL. 7 The FDFSK data detector simulated waveforms..a Fig. which shows the original bit stream of “0010011lO101” without any errors. To generate a constant frequency clock.) and data (VOUT) outputs are shown on the 4Ih and 5h traces respectively. The final demodulated data bit III-435 . cycle or two successive short CK. Both rising and falling edges of the CG. 8 n. On every rising edge of the CK. From top to bottom. which indicate long period pulses (2. The output of the FDFSK data detector circuit is only a pulse.O and VHOwhen a digital “0” short cycle is being received because in our FSK protocol in Fig. CK. “001001 110101” changes to “000010000111001001” when it is encoded to the FSK data transfer protocol. Why. 8a and 8b are CL and CH capacitor voltages respectively. Fig. 5 The FDFSK data detector simplified schematic diagram. Therefore.5MHz) of the bottom trace. input. to generate the serial data output (VOUT) and a constant frequency output clock ( C L J . is high. The data hit stream of -error vout ckout Fig. Fig. Fig.is set somewhere between VH.2ks and t=5ps and shown on the 3rd trace. indicate received data bits on VOUT. The inserted error bits have been detected at t=3.. To test the error detection circuitry two single zeros are added before the 121h and I S h bits and finally a bit stream of“0000100001 IQlOOlO0Ql” is fed into the FDFSK demodulator CK.

voltage.999-1002. REFERENCES M.2000. pp 277-282. voltage. P. “On-chip coils with integrated cores for remote inductive powering of integrated microsystems. “A BiCMOS wirelcss interface chip for micromachined stimulating microprobes. K. Edington. MadisonWisconsin. pp. Troyk and M. F. CH. M . (c) The FSK data detector output. Najafi. Madison-Wisconsin. Najafi. pp. (d) The FSK demodulated data output 111-436 .” The 11“ International Conference on Solid-State Sensors and Actuators (Transducers ‘Ol). J. 60-62. Volume 1. “Fully integrated power supply design for wireless biomedical implants. Najafi. Wise. and K. 8d. Supply voltage I 2OuA and 33uA I 5v 7. (a) Larger capacitor.stream at IOOKbitkec is shown in Fig. G. and I.” IEEE-EMBS Special Topic ConJerence on Microtechnologies in Medicine and Biology proceedings. “A 256-site 3 0 CMOS microelectrode anay for multipoint stimulation and recording in the central nervous system. May 2002 M.” Transducers 97. Table 1 summarizes some of the specifications of the FDFSK demodulator chip. Gingench. CONCLUSION TABLE 1 SPECIFICATIONS OF THE FDFSK DEMODULATOR CHIP Process technology Die size 1 Uofh4 CMOS 3 ~ m I2mmx2mm We have developed a high-rate FSK data transfer protocol and demodulator circuit for wirelessly operating the University I. pp. D. Ghovanloo. Von A r x and K.” IEEEEMBS Special Topic Conference on Microtechnologier in Medicine and Biology proceedings. K. 0. J. D.” A n t e n n a arid Propagarion Symposium. 5. CL. Hetke. 416419 June 2001. May 2002 Fig. pp 414419. 8 The prototype FDFSK measured waveforms withfi and fo equal 10 lMHz and 2MHz respectively. “Inductive links and drivers for remotely-powered telemetry systems. Ghovanloo and K. Wise. (b) Smaller capacitor. Beach. lune 1997. and K. Anderson. R. A. 1.