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Scaling Silicon Devices Towards the Atomic Scale
John Alcock (00517801) Sridhar Bulusu (00508188) Atharva Inamdar (00512270) Vishanth Narayan (00515089) Shashwat Sapre (00512655) Ali Shad (00507167) Krishna White (00512908) Supervisor: Dr Z. Durrani
As higher performance is demanded from smaller and smaller devices, research into nanoscale components is of obvious interest. As a result, many devices are in the process of being scaled to atomic sizes with the use of silicon nanowires (SiNWs). These include FETs, sensors and complete logic circuits. Larger scale devices, such as solar panels and lithium ion batteries, may also benefit from a several-fold increase in efficiency and capacity when constructed with nanowires, though this technology is currently at the experimental stage.
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Introduction Silicon Nanowire Synthesis 2.1 Chemical Vapour Deposition 2.2 Plasma-Enhanced Chemical Vapour Deposition 2.3 Vapour-Liquid-Solid Process 2.4 Chemical Etching 2.5 Laser Assisted Catalytic Growth Method
3 4 4 5 5 6 7 8 9 9 10 10 12 13 14 16 16 17 19 19 22 22 23 23 24 24 25 27 28
Field Effect Transistors 3.1 Silicon Nanowire FET Characteristics 3.1.1 3.1.2 3.1.3 Multiple-Level FETs by AFM Nanolithography 4nm Channel Width FETs by AFM Nanolithography Integratable Nanowire Transistors
Non-Volatile Memory using Molecule-Gated Nanowires 4.1 4.2 Nanowire Based Non-Volatile Device Crossed Nanowire Non-Volatile Device Device Fabrication Sensing Mechanism Silicon Nanowires as Anode Materials Operation 7.1.1 7.2 7.3 7.4 7.5 Difference Between Nanorod Array and Planar Photoelectrodes
Nanosensors – Detection of DNA & DNA Sequence Variations 5.1 5.2
Lithium Batteries with Silicon Nanowire Anodes 6.1 7.1 Solar Cells using Silicon Nanowires
Absorption in Silicon Nanowire Arrays Silicon Nanowire Devices for Photovoltaics Slantingly-Aligned Silicon Nanowire Arrays Single Axial p-i-n Nanowires for Solar Energy Harvesting
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The demand for compact, multifunctional devices has been growing at an immense rate, putting pressure on manufacturers to fit more powerful electronic circuits into ever smaller packages. However, while Moore‟s Law has so far been a reliable measure of this progress, we are rapidly approaching the limits of current manufacturing methods. Solutions involving nanotechnology – specifically, nanotubes and nanowires – is an area of enormous interest as the boundaries of manufacturing are pushed even further. As the name suggests, nanowires are wires with dimensions of the order of nanometres. Although much research has already been conducted on carbon-based nanotubes (CNTs) and nanowires (CNWs), recently the direction of study has shifted towards investigation of silicon nanowires (SiNWs). SiNWs present a unique opportunity to fabricate basic electronic components such as Field Effect Transistors (FETs) with nanoscale dimensions. The implications of this research are significant: future processing units could potentially have several hundred times the current transistor density, while micro- and nanoscale devices could be fabricated with ease. Over the past three decades, advanced experiments with programmable logic circuits and bio-sensors made from nanoscaled FETs have already been carried out. Devices such as bio-sensors for applications in DNA, virus, and bacterial detection have been made successfully and are being tested extensively. The use of SiNWs is not restricted to nanometre-scale electronics. Larger devices, such as those designed for energy harvesting and storage, may also benefit from the technology. The latest SiNWbased solar cells are considerably more cost effective than solar cells built solely with conventional methods. Lithium ion cells, used widely in electronics as a result of their high capacity, may have their storage capacity at least tenfold – SiNWs have an extremely large charge capacity at lengths of up to just a few hundred nanometres. This paves the way for batteries that last longer, need less frequent charging and yet are even smaller than existing units. It is important to note that the method of manufacture significantly affects the electrical characteristics of the nanowires. The most common method used at present is Chemical Vapour Deposition (CVD); slight variations of this technique include Plasma-Enhanced Chemical Vapour Deposition (PECVD), which is also widely used. Processes that use CVD generally use the Vapour-Liquid-Solid (VLS) technique for fabrication. Other methods, such as Atomic Force Microscope (AFM) lithography are used in manufacturing. SiNWs do not have to be made from pure silicon. Doped silicon can also be used. This report describes the various manufacturing processes of SiNWs and their applications, discussing five nanowire devices in detail: FETs, programmable logic circuits, bio-sensors, lithium ion batteries and solar cells.
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2. Silicon Nanowire Synthesis
Nanotechnology follows a bottom-up paradigm which involves the controlled growth of nanoscale structures to form nanoscale 'building blocks' which fit together and allow the creation of new devices. Nanowires form these building blocks and can be grown or synthesised in many different ways. In this section of the report we will consider a number of techniques.
2.1. Chemical Vapour Deposition (CVD)
Chemical vapour deposition is a process used for the deposition of thin dielectric films – for example, silicon oxide or nitride – from their gaseous state into a solid state upon a substrate. In this process, a silicon wafer is first cleaned to remove the native oxide before a thin layer of gold film is deposited by electron-beam evaporation. This gold-coated wafer is then left to grow in the CVD reactor for 30 minutes, where it is annealed with hydrogen and then doped using a SiH 4/B2H6 (silane/diborane) ratio of 4000:1. This is performed at a pressure of 10 Torr and a temperature of 680C to produce a dense array of p-doped SiNWs. Finally, selected nanowires are suspended for sonication.
The disadvantage of this manufacturing method is that it involves moving the wires after they are grown. This presents an obstacle to large-scale integration.
Figure 1: (a) General concept diagram of Nanowire synthesis. (b) Picture of a CVD reactor. (c) Centre part of the CVD set-up, growth wafer inside quartz tube circled. SEM image of the grown SiNWs (inset). (d) Ethanol before and after sonication separation of SiNW observed in colour change. (Raza et al, 2006)
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2.2. Plasma-Enhanced Chemical Vapour Deposition (PECVD)
Plasma-enhanced chemical vapour deposition is similar in principle to conventional CVD: it consists of the deposition of a solid material, such as a thin film, onto a substrate. It can also be used for SiC layers or poly-silicon deposition.
A plasma of reacting gases is generally created by generation of 100Hz to 13MHz radio frequency (RF) electromagnetic waves in a reaction chamber. The necessary energy for the reaction is produced by heating the gas or plasma to form the reactive ions and radicals. The growth on the substrate begins because of the high activation energy provided by the intense bombardment by ions from the plasma. The silicon films obtained from this process are generally Figure 2: The AKT 1600, shown above, is an advanced between 20nm to 100nm thick with good adhesion plasma reactor that produces high quality SiN, SiO and and high growth rates. deposited film –
Many properties of the http://www.hitech-projects.com/dts/docs/pecvd.htm, structure, density,
doped Si layers. (Royal Philips Electronics
conductance and uniformity of the deposit, as well its maximum thickness – are dependent on PECVD process variables such as plasma power, chamber pressure and the RF parameter. These are adjusted as required during the process.
2.3. Vapour-Liquid-Solid (VLS) Process
SiNWs can also be synthesised by CVD via the vapour-liquid-solid process. For this technique, a catalyst is chosen which reacts and forms a liquid alloy solution with the chosen nanowire material. (Gold is a suitable catalyst for the growth of SiNWs, but any monodispersed metal nanoparticle can be used). The catalyst and silicon are heated to form a eutectic mixture to which SiCl4 or SiH4 gas is introduced. In the presence of the gas, the nanoscale „seed‟ droplet becomes supersaturated with silicon (due to deposition of silicon from the vapour to the liquid alloy) and the silicon freezes into a nanoscale crystal. This displaces the droplet from its original position, moving it along the nanowire. The nanodroplet is acting as a nucleus, from which a solid crystalline nanowire is grown. This growth occurs in the <111> direction (axial growth) and process. (a) Initial condition with nanoscale alloy continues until the catalyst is exhausted. By controlling droplet on substrate. (b) Growing nanowire with the size of the nanodroplet, it is possible to finely
alloy droplet on tip. (Wagner & Ellis, 1964) Figure 3: Illustration of nanowire growth by VLS
control the diameter of the SiNW. Studies have shown that it is possible to grow controllable SiNWs with sub-10 nm diameters; however, when their diameter is less than 20 nm, the nanowires tend to grow in the <110> direction.
Page 6 of 30 It is also possible to grow axial and radial heterostructures using the above process. To synthesise axial heterostructures, the VLS process is carried out as before but the gas reactant is changed so that
saturation of a different material occurs, thus growing a new
nanowire joined to the initial one. This forms a junction, as shown in Figure 4b. Radial
Figure 4: Illustrations depicting growth and representative structures of (a) Uniform Single Crystal Semiconductor Nanowire (b) Axial Nanowire Heterostructures (c) Radial Nanowire Heterostructures. (Lieber, 2003)
Figure 4c, are made by changing the growth mode from axial to radial. This is achieved by ensuring homogeneous deposition of material on the nanowire and can be implemented by changing the gas reactant or the growth temperature.
2.4. Chemical Etching
Chemical etching is another method for the synthesis of SiNWs, and differs slightly from VLS in that it is used to produce arrays of nanowires rather than a single nanowire. Chemical etching comprises two steps. Firstly, before any etching can take place on the wafers, they must first be thoroughly cleaned to eliminate any impurities. To remove organic grease the wafers are ultrasonically vibrated in acetone and ethanol at room temperature, and then to remove further organic residues or heavy metals, they are placed in a boiling solution of sulphuric acid and hydrogen peroxide. After each cleaning step, the wafers are rinsed in de-ionised water.
n-Silicon Planar silicon p-n junction p-Silicon
Selective etching in aqueous HF solution containing silver nitrate
SiNW p-n junction array on
Once the wafers are suitably clean, a thin silver film (10-50nm) is laid out on the wafer via thermal
evaporation and the wafers are submerged in an Figure 5: Illustration of preparation of SiNW p-n junction etchant solution of hydrofluoric acid and diode arrays using Etching. (Peng et al, 2004) hydrogen peroxide. The etchant dissolves the silicon; however the areas of the wafer covered in film are protected. Thus SiNWs are etched from the silicon wafer. The longer the time spent in the etchant solution, the more silicon will be dissolved and the longer the resultant nanowires.
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2.5. Laser Assisted Catalytic Growth (LCG) Method
The laser assisted catalytic growth method is another technique used to create SiNWs.
Laser ablation –
target to pump tube furnace
irradiation with a laser beam – of a composite target which contains both the catalyst and the nanowire material, in this case SiFe, is carried out at temperatures
equal to or above 1200°C in a heated flow tube using Figure 6: Apparatus for the catalytic growth of 11 the apparatus shown in Figure 6. This produces a SiNWs assisted by laser ablation. (Wang, 2003) vapour of silicon and iron which condense into Fe-Si nanoclusters. With increasing exposure, the nanoclusters eventually contain an excess of silicon and become supersaturated. The SiNW starts to form when the silicon crystallises into a solid.
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3. Field Effect Transistors
The shrinking of transistors is of obvious interest if the current trend of miniaturisation in electronics is to continue. We are concerned here with field effect transistors (FETs), which form the basis for most current integrated circuits. Aside from the difference in physical size, the advantages of constructing FETs from silicon nanowires are twofold: the nanowire FETs exhibit significantly higher electron mobility than standard planar MOSFETs, and also a relative increase in channel size.
properties allow their electrical characteristics to more closely approach those of an ideal transistor. The applications of such devices are numerous. Nanowire transistors could be used to create even smaller integrated circuits. These low-power circuits might be employed, for example, in biological implants. It is even possible to fabricate transparent transistors using SiNWs. It is worth mentioning that the devices in question can be fabricated on virtually any substrate. This has the potential for impact upon a huge spectrum of applications, for example one could create devices capable of functioning under flexion. Indeed tests were conducted upon a SiNW device which had been fabricated on a plastic substrate. They showed negligible alterations in device current for large amounts of stress upon the device, something which proves promising for the future of flexible electronics.
Although FETs using nanotechnology were first constructed from carbon nanotubes in 1998, it was not until 2003 that functioning SiNW devices were fabricated by Charles Lieber and his team at Harvard.
Nanowires have several advantages
over nanotubes in this application: they are constructed purely of semiconductor material
Figure 7: SiNW FET. (Lieber et al, 2003)
rather than the metal-carbon hybrid nanotubes; the dopant concentration can be precisely controlled during synthesis; and they are more compatible with existing Si-based infrastructure.
The team used the CVD process to fabricate SiNWs, which were deposited from an ethanol suspension onto a layer of silicon oxide to give the structure shown in Figure 7. Most subsequent transistors are variations on this basic structure, which functions in much the same way as a standard planar MOSFET: the application of a voltage at the gate causes inversion in the nanowire, creating a channel between source and drain. Some more recent devices have used “top-down” fabrication methods, which start with an existing multi-layered substrate. This substrate typically comprises a layer of oxide (SiO2) sandwiched between two layers of silicon, which is known as a Silicon On-Insulator (SOI) wafer. Parts of the top layer are then etched away to give the desired structure. Many different techniques can be used to shape the wafer: chemical etching , reactive ion etching
16 17 18
and electron beam lithography
are just a
Page 9 of 30 few examples. In a recent paper, Martinez et al. (2008) used atomic-force microscope (AFM) nanolithography to fabricate transistors with a 4nm channel width.
AFM nanolithography is a variation on the methods described earlier. It involves moving the tip of an atomic-force microscope over an SOI wafer and using it to apply a pulse of voltage to the surface, which creates an oxide layer. Chemical etching can then be used to remove the surface silicon. This leaves a nanowire coated with oxide, which when removed gives a complete SiNW. The transistors created with this method can be quite intricate – for example, the „four-armed‟ model shown in Figure 9. However, the technique can be more expensive than “bottom-up” growth methods due to the fine lithography equipment required. Quitoriano and Kamins have demonstrated what they believe to be a superior process.
Figure 8: SiNW MOSFET. (Kamins, 2008)
developed a technique to control the location and growth direction of the SiNW structure which is compatible with conventional planar processes. holds several advantages: the nanowires can be more robust, as well more amenable to large-scale integration. They used this to fabricate a MOSFET on an n /BOX/p SOI wafer, a diagram of which is shown in Figure 8.
3.1. SiNW FET Characteristics
Current SiNW FETs demonstrate transconductances in the region of 3.3mSµm and on-currents in the region of 2.1mAµm , performing three to four times better than standard planar silicon CMOS devices. Hole mobilities are typically ten times higher than that of planar enhancement mode MOSFETs, in the region of 730cm V s . Furthermore, improved switching delays with reference to planar FETs make SiNW FETs suitable for use in logic circuits operating at speeds outside the limits of CMOS technology.
13 2 -1 -1 -1 -1
I-V data recorded on individual p- and n-type SiNWs show a linear relationship consistent with Ohm‟s law, which indicates that metal-SiNW contacts will not contribute to nonlinear I-V behaviour of junctions. It has been possible to create NOR gates out of nanoscale
Figure 9: A four-arm transistor with drain and source connections. The base beneath the nanowires acts as a gate. (Martinez et al, 2003)
FETs, which routinely exhibit gains in excess of five – something which allows them to be interconnected without the need for signal restoration at each stage.
therefore seems certain that other nanoscale logic gates are possible, either by construction from FETs and diodes or at the the very least by NOR implementation.
Page 10 of 30 3.1.1. Multiple-Level FETs by AFM Nanolithography
It has been shown by Martinez et al. that a greater density of FETs can be achieved by the arrangement of SiNWs in a multiple-level construction – for example, the four-arm transistor in Figure 9,
constructed from two perpendicular SiNWs across a silicon wafer. With the silicon wafer acting as a gate terminal, the device can be considered to have four sets of drain-source connections, each of which has its own characteristics determined by the channel widths and lengths in each case. The output characteristics are
Figure 10: Output characteristics for the four-arm transistor using different pairs of Drain-Source terminals. (Martinez et al, 2008)
shown in Figure 10.
4nm Channel Width FETs by AFM Nanolithography
As described earlier, SiNW FETs have been fabricated by Martinez et al. with channel widths as small as 4nm using AFM nanolithography. The output characteristic for this FET, shown in Figure 11, is very similar in terms of current to that of the multi-level, four-arm FET whose channel lengths are three orders of magnitude larger – both achieve a drain-source current of approximately 40nA for a drain-source voltage of 2V and a gatesource voltage of 3V. However the device does not appear to saturate as early as the four-arm FET, with a clear gradient still visible at a drainsource voltage of 1.5V regardless of gateFigure 11: IDS-VDS characteristic for the 4nm channel-width transistor. (Martinez et al, 2008)
source voltage. In contrast, the four-arm FET showed saturation as early as 1V. The 4nm
channel width FET also exhibits a very shallow gradient in the triode region, which limits its use to switching applications such as digital logic gates.
Page 11 of 30 3.1.3. The Integratable Nanowire Transistors planar-compatible technique developed by
Quitoriano and Kamins was described earlier. In addition to the advantages already discussed, the electrical characteristics of FETs produced using this method show promise, especially when the infancy of the manufacturing technique is taken into account. The output characteristics in Figure 12 show reasonable saturation, and with an Ion/Ioff ratio of approximately 10 , the device can be used in such a way that temperature changes (which affect the threshold voltage and carrier mobility, and hence Ion and Ioff) do not interfere with circuit performance.
The high Ion/Ioff ratio also means
low power consumption while in the „off‟ state. The device exhibits an inverse sub-threshold slope of approximately 155mV per decade which is at the low end of the spectrum in comparison to similar devices (which exhibit slopes of between 120 and 609mV
SiNW FET. (Quitoriano & Kamins, 2008)
This means that the device has a low interface-state Figure 12: Output characteristics of an 'integratable' density and so good coupling between the gate and channel – an important feature for amplification and sensing applications.
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4. Nonvolatile Memory using Molecule-Gated Nanowires
Moore‟s Law, formulated by Gordon Moore in 1965, speculates that the number of transistors that can be placed on an integrated circuit will double approximately every two years 24. Since 1965, silicon technology has advanced at exponential rates and this prediction has held true with an excess of 1 billion transistors25 currently placeable on an integrated circuit. This is mainly done through shrinking the size of the transistor so that more fit on to the same integrated circuit. However, this ultimately leads to tradeoffs between performance, energy efficiency26 and cost as space becomes more restricted. It is thought that the limits of planar silicon transistor dimensions will be reached at some point in the next decade. This creates a need for new technical developments. The use of hybrid structures is something that is likely to be used within the silicon industry in the aid of making transistors ever smaller. There are currently two technologies being heavily researched into which can meet this requirement: SiNWs and CNTs. In short, SiNWs are chosen over CNTs for the reasons described earlier: they remain as semiconductors regardless of diameter and their doping can be controlled during synthesis which is crucial for devices applications , thus allowing them to be more readily integrated within the industry. The previously discussed high performance SiNW FETs created by Lieber molecule-gated nanowires with retention times in excess of 20 minutes
led to his research into which can be used for
nonvolatile memory purposes. These can be manufactured using any of the processes previously discussed for use with FETs. This application shall be discussed in further detail. A p-type SiNW FET (p-SiNW FET) is created by adding acceptor impurities with diborane (B 2H6) commonly used. N-type SiNW FETs (n-SiNW FET) are created by adding phosphine (PH3) as the donor dopant . Table 1 shows the comparison of the key device parameters of a p-SiNW FET and a regular planar Si FET device. p-SiNW FET Gate length (nm) Gate oxide thickness (nm) ION (µA/µm) [Vsd = 1V] IOFF (nA/µm) Subthreshold slope (mV/dec) Transconductance (µS/µm) 80-2000 (50) 600 (1.5) 50-200 (2000-5600) 2-50 (4-45) 174-609 (60) 17-100 (2700-7500) Planar Si FET 50 1.5 650 9 70 650
Table 1: Comparison of key device parameters between SiNW FETs and planar Si FETs, both with a comparable doping ratio of 4000:1 (Kumar, 2008). The SiNW FET results have been scaled in brackets using a gate length of 50nm and gate oxide thickness of 1.5nm. (Lieber et al, 2003)
It can be seen from Table 1 that some key SiNW FET device parameters can even exceed those of planar Si FETs when both have similar doping levels, ultimately leading to benefits for high-speed devices.
Page 13 of 30 This method has since been enhanced with the use of different redox active molecules to create similar devices but with different properties.
4.1. Nanowire-Based Nonvolatile Devices
N-type indium phosphide (n-InP), n-type gallium nitride (n-GaN) and p-Si nanowires can all be used with redox active molecules including ferrocene, zinc tetrabenzoporphine and cobalt phthalocyanine (CoPc) to create these nanowire FETs. All the above provide similar results – however, the measurements taken for this device were using n-InPNW FETs functionalised with CoPc redox molecules as shown in Figure 13. Chlorobenzene solutions of CoPc are spin coated which produces a uniform layer of the redox molecules on the nanowire surfaces with layer thickness greater than one monolayer.
Conductance (G = I/Vsd) against gate voltage (Vg) data for an n-InPNW FET is shown in Figure 14, before and after the addition of a CoPc layer. Before the
layer is added, the response is like that of an n-type FET. After the addition of a CoPc layer a large
Figure 13: Nanowire based nonvolatile device. The middle picture shows an SEM image of a device with the lower circular picture showing a TEM image of an nInPNW. (Lieber et al, 2002)
before (green) and after (red) surface
apparent. As the gate Figure 14: G against Vg for an n-InPNW FET voltage is increased modification with CoPc and V = 0.1V. sd from negative to (Lieber et al, 2002)
positive the channel conductance starts to increase before the green curve, and also increases with a steeper gradient. As the gate voltage is then decreased from positive to negative the channel conductance decreases before the green curve and again with a steeper gradient, thus producing the hysteresis curve. The direction is shown with arrows in Figure 14. This is used to show the two states of a bistable system and thus can be used as a three terminal switch or a memory device. The low conductance state can be said to be off, and the high conductance state on. Figure 15 shows the switching of the device using a Vg pulse of ±10V. The CoPc modified FET shows reversible switching which can be maintained for at least 100 cycles before any degradation of the ratio is observed and a change in Figure 15: Reversible on/off switching of the conductance from around 0.1nS to 600nS.
n-InPNW FET after surface modification with
This would seem 1s gate pulses. (Lieber et al, 2002)
to confirm that a molecule-gated nanowire FET could be used as a bistable on/off switch.
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4.2. Crossed Nanowire Nonvolatile Devices
A crossed nanowire (cNW) FET uses crossed nanowires as the FET channels and the gate. This structure, as shown in Figure 16, has its channel length defined by the gate nanowire diameter; its ability to be integrated is defined by assembly and not lithography.
Results for conductance against gate voltage are taken, as with the n-InPNW FET but this time even larger hysteresis can be seen in Figure 17, confirming that cNW FETs can be used as bistable switches. More significantly these FETs can undergo reversible switching
Figure 16: Crossed nanowire based nonvolatile device with a nanowire being used as the gate. Top right picture shows an SEM image of a device. (Lieber et al, 2002)
without any significant change in the conductance ratio for hundreds of cycles. Figure 18 shows the retention times for the device which show whether these bistable switches are able to
be used for nonvolatile memory purposes. The initial on/off ratio exceeds 10 as the conductance when on is greater than 1000nS and when off is less than 0.1nS. Both curves slowly decay towards a steady state difference of around 700nS. This difference is maintained for at least 20 minutes with other tested devices able to hold their state for several hours. This huge difference in retention times is something which requires further research; however, it is thought that it is due to “variations in the barrier separating an active nanowire core and the redox active molecules”.
Figure 17: G against Vg for a cNW FET after surface modification with CoPc. (Lieber et al, 2002)
To restate, bistable switches can be constructed on a nano scale using both nanowire FETs and cNW FETs modified with redox active molecules. These two devices give on/off ratios exceeding 10 and retention times of at least 20 minutes due to the unique nature of the redox molecules. This enables them to be used for nonvolatile memory purposes. There are several issues which first need to be faced before any future technology can be modified to use these devices. The retention time needs to be of a consistent level and also must be much higher than the 20 minutes recorded as nonvolatile memory is such that the data must remain when the
Figure 18: Retention times for a cNW FET device after modification with CoPC. The upper curve shows conductance against time after the device was switched on and the lower curve after the device was switched off. (Lieber et al, 2002)
power is switched off. It is therefore suited to use in volatile memory applications.
Page 15 of 30 Another major problem is how to repeat the same experimental procedure but on a manufacturing level. The results need to be repeated again and again to ensure consistency and the experimental procedure needs to be simplified so that mass production of these devices can be undertaken. Moore‟s law is sure to hold true in the future as the technology exists for nanowires to replace standard planar devices. However, more research needs to be conducted into this technology and methods of fabrication if we are to see it come into mass production.
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5. Nanosensors – Detection of DNA & DNA Sequence Variations
The first experiment to incorporate the idea of integrating nanotechnology with sensors was in 1990, with the deposition of individual xenon atoms on a nickel substrate to spell the logo of the computer company IBM . Since then, there has been an increasing interest shown in nanosensors, with a large increase in funding and research output. An obvious advantage of the use of nanotechnology for this application is a great decrease in size, which makes it possible to integrate nanosensors into many modern day devices. Further reasons for the increased popularity were largely due to the promise that was seen in the various applications sensors. In the past, both carbon nanotubes and silicon nanowires have Figure 19: SiNW with Nickel contacts. been used in the detection of DNA and DNA sequence PennState 1855 variations. However, SiNWs are preferred today as their electrical http://www.mrsec.psu.edu/research/seeds.asp,
34,35 33 32
(Center for Nanoscale Science,
properties and sensitivity of detection can be altered according to needs by adjusting the dopant concentration and the NW diameter . Also, silicon oxide layer surfaces can be modified in order to tailor it to either biological or chemical receptors. This section of the report will focus on the application of the SiNW nanosensor in the detection of DNA and DNA sequence variations.
5.1. Device Fabrication
The main nanowire for the DNA sensor is fabricated using gold-catalysed CVD. Electrical contacts are then etched onto the ends with electron-beam lithography. It is the conductance between these contacts that will be
investigated and used to draw conclusions. After the attachment of the leads, the devices are chemically functionalised with probe molecules for DNA sensing experiments. Usually, one of the methods of covalent binding is used to add PNA probes onto the surface of the nanowire.
Figure 20: (A) Schematic diagram of a sensor device consisting of the SiNW (yellow) with the arrow indicating direction of sample flow placed on an oxidised Silicon substrate. (B) PNA probes on nanowire (C) PNA-DNA interaction. (Lieber et al, 2004)
Before attaching the probes,
the surfaces of the SiNWs are treated with water vapour plasma. Finally, the SiNW surfaces are exposed to a 5m A rough device
PNA solution in water for 12 hours. schematic is shown in Figure 20.
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5.2. Sensing Mechanism
Linear current versus voltage behavior is present for all devices, and they have conductance values between 200 and 1700nS.
PNA is chosen for the probes because it shows high binding affinity to its complementary DNA or RNA sequence and shows single-base specificity.
Furthermore, it has high chemical
stability against both temperature and pH, as well as high biological stability to nuclease and protease. The PNA probes
on the SiNW bind with their complementary DNA samples and this alters the property of the SiNW. The graphs below show some results of the variations in conductances that were observed upon addition of small quantities of DNA. In Figure 21, conductance is seen to remain relatively constant before addition of any substance (point 1). However, a very rapid increase is observed upon addition of the DNA sample (point 2) and a much more gradual increase takes place after that (point 3) over hundreds of seconds. This increase in
Figure 21: Real time conductance response from a SiNW device with PNA receptor. The arrow marks the time when a 60fM WT DNA sample was added. (Lieber et al, 2004)
conductance can be explained by an increase in negative surface density due to the binding of negatively charged Figure 23: Conductance versus time for oligonucleotides at the surface. SiNW with linked PNA receptor in the Conduction remained roughly
presence of 100fM MU DNA samples. (Lieber et al, 2004)
Figure 22: Time dependent conductance in DNA-free solution. (Lieber et al, 2004)
constant when a solution without DNA in it was added, which can be seen in Figure 22. Also, the change in conduction, shown in Figure 23, was insubstantial when a solution containing DNA was added to the surface of a SiNW that had already been hybridised with complementary DNA sequence. Figure 24 shows a combination of all the results discussed above. When a DNA free solution is added, as proved before, the conductance remains consistent. However, there are two new
Figure 24: Conductance versus time for PNA probed NW device during flow of (1) DNA-free solution, (2) 100fM MU DNA (3) DNA-free solution and (4) 100fM WT DNA. (Lieber et al, 2004)
results to note here. Firstly, the addition of a DNA free solution to a SiNW which has already been hybridised with DNA sharply
Page 18 of 30 decreases the conductance to approximately its original value (3). Secondly, the addition of a different type of DNA, WT combination sequence (4) causes a sharp increase but over a longer time scale than when the original MU DNA sample was added. This shows that the PNA-probed SiNW can differentiate between different sequences of DNA and hence detect sequence variations in addition to the simple presence of DNA. In summary, SiNWs that are functionalised with peptide nucleic acid (PNA) probes can be used to detect DNA and DNA sequence variations by monitoring variations in conductance across the ends of the SiNW in real time with very high sensitivity and selectivity. More generally, this approach has been extended to the detection of other rare genetic mutation DNA or diseases, such as cystic fibrosis
and hence by exploiting recent advances in large-scale assembly , the integration of ultrasensitive nanowire nanosensors into many applications has revolutionised DNA detection for genetic screening and studies in biology.
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6. Lithium Batteries with Silicon Nanowire Anodes
Batteries are used in a broad range of
applications to power devices of many sizes with a variety of power ratings. Although alkaline batteries are the most common type, lithium ion models are gaining popularity due to their high capacity and resultant long life. Research is now being carried out using cutting edge technology to improve this capacity even further: silicon nanowires are being trialled as anodes in the batteries. This new technology promises to increase their capacity by several times.
Figure 25: Fully Lithiated SiNWs. Inset: Unlithiated nanowire with Au-Si alloy on top. (Peng et al, 2008)
The SiNWs used for the anode are roughly 100nm
in diameter and are generally fabricated using
the VLS CVD technique. Typically, the process occurs at temperatures of 500°C and above to yield higher capacities, since it has been shown that the temperature is a major factor in determining the available storage capacity. Increased manufacturing temperature correlates with increased capacity.
These nanowires inherit the electrical characteristics of silicon and thus do not need doping to control conductivity.
6.1. Silicon Nanowires as Anode Materials
The nanowire technology has been shown to increase the capacity of a lithium battery by ten times; however, this is not the only advantage. In addition to enhanced electrical characteristics, the structural properties are also improved. Anodes made from thin-film silicon – the current technology – have weaker structures that are prone to fracturing after several charge/discharge cycles. SiNWs are grown directly on the anode material which provides one of the biggest advantages – a direct 1D electrical pathway allowing for very high efficiency of charge transport.
Since each nanowire is connected to the
anode electrically, they all contribute to the overall
Figure 26: TEM image of a single SiNW partially coated with Nickel before (c) and after (d) cycling (charge and discharge). (Cui et al, 2008)
nanowires change in volume by up to 400% as the lithium ions react and combine with silicon. SiNWs are also affected by cycling – however, the effect is only significant
after at least 10 cycles.
Page 20 of 30 One of the key characteristics of SiNWs is the very high surface area-to-volume ratio. This allows a large number of lithium ions to react with silicon, resulting in a higher capacity - up to 4200mAhg
has been recorded in the first charge cycle. A drawback of the nanowires is an irreversible drop in capacity after the first charge cycle. It should be noted that the amount of charge stored in the SiNWs during charging is greater than the charge released during the discharge cycle. This is due to the change in volume of the SiNWs as lithiation is Figure 27: SiNW charge/discharge capacities compared not completely reversible. For the end application with other technologies over 10 cycles. (Cui et al, 2008) this means that the available capacity of the battery is reduced. The capacity loss during cycling is known as fading. Studies conducted at Stanford University have shown to achieve at least 75% of the maximum theoretical capacity (4200mAhg ) on second cycle and higher capacity up to 90% on the third cycle . During experimentation, it was also found that higher charging currents resulted in higher capacities. The charging cycle involves lithium ions reacting with silicon; this results in an increase of the nanowire volume. Due to the large surface area, a large number of lithium ions react and thus the volume increases to around 400% of its original value.
43 43 -1
The experiments conducted have shown that
the diameter increases from 89nm to 141nm. This is shown in Figure 26 on the previous page. The TEM image also shows that the expanded SiNW winds itself around the nickel coating. The nickel coating is present to show the change in volume. A study conducted to examine possible applications for micro-batteries provides some relevant electrochemical data. A typical
SiNW, of diameter in the range of 200-300nm grown at 550°C has an initial capacity of 1750mC. After 20 cycles of charging and discharging the fading effect reduces the
Figure 28: Voltage profiles of SiNWs cycled at varying rates. NB. C/20 profile is from second cycle. (Cui et al, 2008)
capacity to around 750mC
- a loss of
approximately 57%. However, if the growth
temperature is increased to 575°C, then this capacity is increased to 3200mC. This is equivalent to 3000µAhcm .
Another study shows evidence of higher capacities close to the theoretical maximum
capacity (4200mAhg ). A first charge capacity of 4277mAhg capacity of 3124mAhg earlier.
43 -1 -1
was achieved and a first discharge
was recorded. This indicates a Coulombic efficiency of 73% as stated
A second charge capacity was reduced by 17% to 3541mAhg and the discharge capacity
of 3193mAh , indicating 90% efficiency. In order to place these figures in perspective, it should be
Page 21 of 30 noted that the graphite used in current lithium battery anodes has a capacity of 372mAhg . This can be seen in Figure 27. Figure 28 shows charge/discharge cycles at different rates and also the capacity. When charging the SiNWs at a current equal to their measured capacity, referred to as C, the overall capacity achieved was >2100mAhg . In another device a charge rate of C/5 achieved stable capacities of ~3500mAhg
-1 -1 -1
over 20 cycles. This data clearly shows a higher capacity of six to nine times than that of conventional graphite anodes. The C/20 rate achieves the highest capacity; however, this graph shows the second cycle onwards.
Thus the initial first cycle rate of 4277mAhg is not shown. The positively inclined
curves show charging while the rest show discharging. It is evident that anodes using SiNWs have very high capacity compared with the traditional graphite anodes. The capacity can potentially be increased by 10 times over a large number of cycles. However, some obstacles, such as fading, need to be overcome to achieve high efficiency and large capacity over a reasonable number of cycles. SiNWs not only present better electrochemical properties but also structural advantages. During charging and discharging, the volume can change significantly, but importantly the SiNWs do not fracture during this process. These properties allow for the manufacture of extremely high capacity batteries in the future for all electronic devices providing a longer life.
Page 22 of 30
7. Silicon Nanowire Solar Cells
Environmental concerns are a bigger part of our lives today than ever before and there is increasing pressure to find and exploit renewable energy.
The Sun is an attractive source of energy.
provides 100000TW of energy, but today‟s population only needs 13TW. Solar cells are a great way to harness this incredible power and it is estimated that by covering just 0.1% of the Earth‟s surface with solar cells of 10% efficiency the world‟s energy demands could be met.
The first solar cells
were invented in the 1940s and since then the two types of cells most commonly used are photovoltaic (PV) cells and photoelectrochemical (PEC) cells. However, efficiency limitations and
high electricity production costs have prevented solar energy from becoming more popular. The current challenge is to effectively achieve miniaturisation of these cells while addressing issues of cost and boosting efficiency. Focus has recently been directed towards nanotechnology and the use of nanostructures as a solution to the problem. Silicon is a popular choice due to its abundance, availability and proven photovoltaic properties in silicon-based solar cells available in the market. Research is therefore underway on technologies using silicon nanowires.
The concept by which light is converted into electricity is the same for silicon solar cells and is explained below. Figure 29 shows the band diagram of a pn diode for solar energy harvesting. When light shines onto the cell, electrons in the valence band can absorb the energy of the photon. If the energy is greater or equal to the band-gap then the electron can be promoted to the conduction band leaving behind a hole and hence generating an electron hole pair. If the energy of the photon is greater than the required energy to promote the electron to the conduction band then the excess energy will be radiated as heat. Electrons are attracted by low potentials and holes by high potentials. In a pn junction the low potential is on the n-type side and the high potential on the p-type side, this is a result of the difference in Fermi levels between the n- and p-type regions. Thus there are two cases: If the electron is excited in the p-type region then it will be attracted by the low potential on the n-type region and will “roll down the hill” resulting in current. Conversely if it is excited on the n-type side then it “sees” a potential barrier; in this case, the hole generated will be attracted by the high potential on the p-type side and “climb up the hill” again resulting in current.
Figure 29: Energy band diagram for a pn-diode for solar cells: Photons can excite electrons and promote them from the Valence Band to the Conduction band. This creates an electron hole pair and current can flow. (Grätzel, 2007)
Page 23 of 30 Since the holes and electrons flow in opposite directions but have opposite sign, the current will sum up in one direction – from the n-type region to the p-type region. 7.1.1. Difference Between Nanorod Array and Planar Photoelectrodes Figure 30 shows the geometry for nanorod (nanowire) arrays.
In these the pn diode is formed radially, such that the current can flow from the inside out. This enables engineers to fabricate nanorods which are axially long enough to absorb enough light. But at the same time the radius of the nanowires can be shorter than the diffusion length, which improves the
Figure 30: Nanowires can be fabricated such that the radius is thinner than the diffusion length. This improves I-V characteristics, because recombination hardly takes place. (Hu & Chen, 2007)
7.2. Absorption in Silicon Nanowire Arrays
For effective solar to electrical energy conversion, it is important that the material used can absorb the energy of photons efficiently over a broad range of frequencies, i.e. a high “absorptance” is needed.
The absorption spectrum was simulated for SiNW arrays as shown in Figure 31. The photon energy varied from and 1.1eV to 4eV. Equation 1 relates 𝐴 𝜔 , the absorptance, 𝑅 𝜔 , the reflectance, and 𝑇(𝜔), the
Figure 31: Absorption spectrum of a SiNW array and a film over a photon wavelengths range from 1239nm (infrared) to 309nm (ultraviolet). (Hu & Chen, 2007)
transmittance are desirable properties. 𝐴
𝜔 = 1 − 𝑅 𝜔 − 𝑇(𝜔)
Equation 1: Relation between cell parameters (Hu & Chen, 2007)
Figure 31 shows the absorptance of the array as a function of photon energy and, for comparison, that of a conventional film with thickness 2.33µm. There are three traces for the SiNWs, which correspond to lengths of 1.16µm, 2.33µm and 4.66µm. The data clearly depicts that the SiNW array has high absorptance properties above photon energies of 3eV, but very low absorptance for low
Figure 32: Reflectance and transmittance of SiNW and film. (Hu & Chen, 2007)
frequencies as compared to the film. Moreover, by increasing the length of the SiNWs (from 1.16µm to
Page 24 of 30 4.66µm) the frequency range of absorptance can be extended into the low frequency area by a small amount. Figure 32 shows the reflectance 𝑅 𝜔 (dashed lines) and transmittance 𝑇(𝜔) (full lines) of a film and SiNW array each with a thickness of 2.33µm.
Clearly the SiNW array has a low reflectance for the
full spectrum, but the high transmittance at low frequencies is the cause for low absorption at low frequencies. Calculations have shown that the absorption efficiency are 5.8%, 9.5%, 12.5% and 15.5% for the 50nm, 60nm and 80nm long SiNW and the film respectively.
All in all, the analysis shows that arrays of SiNWs have significantly low absorptance in the low frequency regime as compared to the conventional films that have been used. Hence the overall absorption efficiency of the SiNWs was lower than that of conventional films, but can be improved by manufacturing longer SiNWs.
7.3. Silicon Nanowire Devices for Photovoltaics
Currently, there is a lot of research going into different types of devices using SiNWs for photovoltaics. As shown in the operations section, in general a pn diode is required. The main variable for fabricating different SiNWs is the geometry of the pn diode. There are currently two geometries: axial and radial (coaxial). The difference between these two is that in the former the nanowire consists of a segment which is p-type and n-type to form the pn junction axially, whereas in the latter the SiNW core is made out of p-type and the shell out of ntype to form a pn diode radially. In general coaxial rods are used for the Figure 33: Geometry of 53 nanorods in arrays for solar cells as illustrated in Figure 33. The next two a coaxial p-i-n diode. sections will discuss the characteristics of two devices which can be used for solar energy harvesting. The first is about “Slantingly-Aligned SiNW Arrays” and the second about “Single and Tandem Axial p-i-n SiNWs”.
The inclusion of intrinsic Silicon between the n- and ptype regions improves diode characteristics. (Lieber et al, 2007)
7.4. Slantingly-Aligned Silicon Nanowire Arrays
In this device the SiNW are slanted (SA–SiNW) as compared to vertically-aligned (VA–SiNW) and the pn diode is formed radially as shown in Figure 33.
It is fabricated by chemical etching
of a cleaned p-Si <111> wafer followed by dry metal deposition, as discussed in Section 2.4. The I-V characteristic of the SA-SiNW device is shown in Figure 34.
Regarding the absorption
properties, it was found that the new SA-SiNWs reflect slightly more than the VA-SiNWs. The fact that the SiNWs are slanted probably
Figure 34: IV characteristics of SA-SiNW, which had ann efficiency of 11.37%, an open circuit voltage 580.25mV and a short circuit current 26mA. (Fang et al, 2008)
amounts to a higher reflectance. Although the
Page 25 of 30 VA-SiNWs had better absorptance, the SA-SiNWs performed better. The reason for this could be that in the latter, the “electrode film on the surface of the arrays could probably improve the contact and decrease the resistance loss”.
Table 2 shows the improvement in efficiency and the decrease in
series resistance (RS) which result in an efficiency improvement.
VA-SiNW array cells η (%) Rs (Ω) Rsh (Ω) 9.31 2.49 4775 8.66 2.88 1543 8.91 2.64 4720
SA-SiNW array cells 10.78 1.36 1158 11.37 1.22 3555 10.66 1.38 631
Table 2: Efficiency, series and shunt resistance of VA- and SA-aligned SiNWs. (Fang et al, 2008)
One disadvantage of SA-SiNWs is the low minority carrier lifetime. In bulk silicon wafer the lifetime is about 10.6µs but in the array it is only 1.7µs.
This means that recombination takes place at a higher
rate and limits current. Hence this is an area where effort is required to find ways of increasing the carrier lifetime and thus improving the efficiency.
7.5. Single Axial p-i-n Nanowires for Solar Energy Harvesting
As the name suggests, this analysis will concentrate on the photovoltaic characteristic of a single axial p-i-n nanowire shown in Figure 35.
In contrast to the SA-SiNW
model, the pn diode of this device is formed axially, which means
Figure 35: A single axial p-i-n SiNW. (Kempa, 2008)
that the current will flow along the axis of the nanorod. This axial SiNW is fabricated using the gold nanoparticle-catalysed VLS
growth method. The axial variation in doping is achieved by changing the gas reactant, as discussed in section 2.3. The I-V characteristics were established under dark conditions with i-region widths of 0µm (red trace), 2µm (green trace) and 4µm (black trace) and is shown in Figure 36. The figure clearly suggests that the nanowire has similar characteristics to that of a planar pn-diode: The onset value is typically close to 0.7V and the current rises steeply from this point onwards.
Moreover, it is
noticeable that increasing the i-region width results in a smaller reverse bias current which is desirable. Photovoltaic properties were obtained under an illumination intensity single axial p-i-n SiNW for different -2 54 of 100mWcm . It turned out that the devices with different i-region widths of the i-region. (Kempa, widths showed improved characteristics with an increase in this width, as shown in Table 3. However, the maximum efficiency of this device is only 0.5%, which is very low compared to alternative SiNW devices (such as the SA-SiNW) which exhibit efficiencies of around 10%.
2008) Figure 36: I-V characteristic of
Page 26 of 30
i-region width (µm) 0 2 4
Voc (V) 0.12 0.24 0.29
Isc (pA) 3.5 14 31.1
Efficiency (%) N/A N/A 0.5
Table 3: Photovoltaic Characteristics of single p-i-n SiNWs for different widths of the i-region. (Kempa, 2008)
In conclusion, this section has briefly discussed how solar cells work in general, pointing out the main advantage of using nanorods over planar solar cells and the importance of good absorptance characteristics in solar energy harvesting. Moreover, there are mainly two types of SiNWs for solar energy: radial and axial. Clearly the SA– SiNWs, which use coaxial pn diodes are currently the most efficient solar cells using nanorods, whereas single axial nanowires have a very low efficiency. Hence the future of SiNWs in the area of solar energy lies in coaxial SiNWs.
Page 27 of 30
Silicon nanowires are a promising solution to the future challenge of device miniaturisation. They can be synthesised by different methods, depending on the application for which they are used. They are multifunctional and can be used in a wide range of situations. However, research is still ongoing to determine to what extent they can be useful. Initial results have proved positive and it has been shown that SiNWs can play an effective role in the fabrication of electronic components such as FETs and nonvolatile memory. The SiNW FETs are advantageous because their electrical properties closely resemble that of ideal transistors yielding better results while allowing for increased transistor densities because of their reduced size. Similarly, studies have shown that SiNWs are capable of storing data on a nano-scale, something previously unattainable. Challenges for SiNWs in nonvolatile memory include increasing the retention time of the memory from the current 20 minutes and obtaining a fabrication process that would allow for mass production. Research is also currently ongoing to investigate the role of SiNW as nanosensors while other groups are focused on developing high capacity batteries. Using SiNWs in nanosensors shows the true potential of nanowires, bridging the gap between biology and electronics. Detection of DNA and other biological molecules, such as proteins and viruses is possible due to an active site which changes the conduction of the nanowires in the presence of the active material. The use of SiNWs in lithium batteries has proved to be advantageous with increased battery capacity and greater resistance to charge cycles. However, experts agree that there is still room for improvements in efficiency and capacity losses. Additionally, SiNWs have shown promising results in the field of photonics despite research being in the preliminary stage. Research conducted to determine which method of fabrication produces the most effective nanowires for solar applications, have shown that coaxial nanowires offer the most benefits over axial nanowires and conventional solar cells. SiNWs have shown enormous potential in meeting the demand for smaller, more powerful devices. However, it is clear that further research must still be done to fully understand and control the properties of SiNWs. One thing is certain: we have all but glimpsed the usefulness of SiNWs.
Page 28 of 30
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