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Asst.Prof(E.C.E. Dept.)



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This is to certify that Mr. Shekhar Kumar Sharma of Electronics & Communication Branch of
Siddhi Vinayak College Of Science & Hr. Education, ALWAR has completed his seminar
work entitled “ASYNCRONOUS CHIP “ under my Supervision as a partial, fulfillment of his
Degree of Bachelor of Technology of Rajasthan Technical University, Kota. I am fully
satisfied with the work carried out by him which has been reported in this seminar and all
the work done is bonafide to the above name student. I strongly recommend for the award of the


Mr. Vikas Tiwari
Asst. Prof(E.C.E. Dept.)


First and foremost, I would like to thank my respected parents, who always encouraged me and taught
me to think and work out innovatively what so ever would be the field of my life.
My sincere thanks go to Mr. Vikas Tiwari (H.O.D., ECE Dept.) for his prodigious guidance,
persuasion, reformative and prudential suggestion throughout my seminar work. It is just her guidance
because of which I was able to know every aspects of the seminar used here.
Finally it is indeed a great pleasure & privilege to express my thanks to colleagues, my friends and my
family members for their all types of help and suggestions.

Date :- -----------

Shekhar Kumar Sharma


Breaking the bounds of the clock on a processor may seem a daunting task to those
brought up through a typical engineering program. Without the clock, how do you organize the
chip and know when you have the correct data or instruction? We may have to take this task on
very soon.

Clock speeds are now on the gigahertz range and there is not much room for speedup
before physical realities start to complicate things. With a gigahertz powering a chip, signals
barely have enough time to make it across the chip before the next clock tick. At this point,
speedup the clock frequency could become disastrous. This is when a chip that is not
constricted by clock speed could become very valuable.

Interestingly, the idea of designing a computer processor without a central controlling clock is
not a new one. In fact, this idea was suggested as early as 1946, but engineers felt that this
asynchronous design would be too difficult to design with their current, and by today’s
standards, clumsy technology.
Today, we have the advanced manufacturing devices to make chips extremely accurate.
Because of this, it is possible to create prototype processors without a clock. But will these
chips catch on? A major hindrance to the development of clock less chips is the
competitiveness of the computer industry. Presently, it is nearly impossible for companies to
develop and manufacture a clock less chip while keeping the cost reasonable. Until this is
possible, clock less chips will not be a major player in the market.




1. It overcomes all the disadvantages of a clocked circuit such as slow speed. The clock orchestrates the synchronous dance of electrons that course through the hundreds of millions of wires and transistors of a modern computer. which uses a technique known as asynchronous logic. Such crystals which tick up to 2 billion times each second in the fastest of today's desktop personal computers. For these reasons the clockless technology is considered as the technology which is going to drive majority of electronic chips in the coming years. high electromagnetic noise etc. dictate the timing of every circuit in every one of the chips that add. One advantage of a clock is that. complex calculations may take many steps. subtract.2 CLOCK CONCEPT The clock is a tiny crystal oscillator that resides in the heart of every microprocessor chip. 1. Wouldn't it be nice to have an alternative? Clockless approach. All operations. A simple transfer of data may take only one step. Computer chips of today are synchronous: they contain a main clock which controls the timing of the entire chips. distributing the timing signals has become more and more difficult. which samples data in the registers at precisely timed intervals. multiply and move the ones and zeros that are the basic stuff of the information age. Present-day transistors can process data so quickly that they can accomplish several steps in the time that it takes a wire to carry a signal from one side of the chip to the other. high power consumption. The use of a central clock also creates problems. divide. each a billionth of a second long. must begin and end according to the clock's timing signals. the clock signals to the devices of the chip when to input or output. Conventional chips (synchronous) operate under the control of a central clock. however. The clock is what which sets the basic rhythm used throughout the machine. Keeping the rhythm identical in all parts of a large chip requires careful design and a great deal of electrical power. The circuit which uses global clock can allow data to flow in the circuit . differs from conventional computer circuit design in that the switching on and off of digital circuits is controlled individually by specific pieces of data rather than by a tyrannical clock that forces all of the millions of the circuits on a chip to march in unison.1 DEFINITION Every action of the computer takes place in tiny steps. As speeds have increased.

in any manner of sequence and order does not matter. fig1. The diagram above shows the global clock is governing all components in the system that need timing signals. All components operate exactly once per clock tick and their outputs need to be ready and next clock tick.1: Power Dissipation in Synchronous (Left) & Asynchronous (Right) Chapter-2 CLOCKLESS APPROACH .

These logic circuits are supposed to respond to every tick of the clock and yet when they can compile to match the speed then logic circuits will be not optimum according to the speed of clock and hence the input and output can go incorrect. however. Clock speeds are now in the gigahertz range and there is not much room for speedup before physical realities start to complicate things. speedup up the clock frequency could become disastrous. Clock (Frequency One can create a clock that is so fast and it sends its timing signals to the logic circuits which are governed by the clock timing signals. enabling a huge savings in battery-driven devices. The faster the clock.1 CLOCK LIMITATIONS There are problems that go along with the clock. 2.2. Like a team of horses that can only run as fast as its slowest member. At both Intel and Sun. By contrast. The result? Instead of the entire chip running at the speed of its slowest components. This will result hardware problem since one has to assemble chips to achieve the speed of clock and hence much more complicated situation arise. At this point. the answer isn't guaranteed until every part completes its work. without needing to wait for everything else. this approach has led to prototype chips that run two to three times faster than comparable products using conventional circuitry. This is when a chip that is not constricted by clock speeds could become very valuable. Clockless chips draw power only when there is useful work to do. chip makers will be able to escape from huge power dissipation. it can run at the average speed of all components. With a gigahertz clock powering a chip. signals barely have enough time to make it across the chip before the next clock tick. the more difficult it is to prevent a device from . Another advantage of clockless chips is that they give off very low levels of electromagnetic noise.2 ASYNCRONOUS VIEW By throwing out the clock. the transistors on an asynchronous chip can swap information independently. a clocked chip can run no faster than its most slothful piece of logic.

so does the power used by the clock. the other parts of the chip are forced to sit idle. One problem is speed. As the number of transistors on a chi increases. involved with these clocked designs that are common today. which controls the timing of the entire chips. One possible solution is a second clock. A clock does not perform operations on information. Therefore. dispensing with the clock all but eliminates this problem. They contain a main clock. There are problems. if one part of the chip is especially slow. however. This wasted computed time is obviously detrimental to the speed of the chip. it simply orchestrates the computational parts of the computer. It is also important to note that doubling the frequency of the clock does not double the chip speed. so this is a poor solution. but this will incur overhead and power consumption. Computer chips of today are synchronous. When we get to the point where the clock cannot drive the entire chip. The clock consumes more power that any other component of the chip. New problems with power consumption are arising. Therefore. . The most disturbing thing about this is that the clock serves no direct computational use.interfering with other devices. The combination of low noise and low power consumption makes asynchronous chips a natural choice for mobile devices. New problems with speeding up a clocked chip are just around the corner. we’ll be forced to come up with a solution. as we design more complicated chips. therefore blindly trying to increase chip speed by increasing frequency without considering other options is foolish. A chip can only work as fast as its slowest component. The other major problem with c clocked design is power consumption. Clock frequencies are getting so fast that signals can barely cross the chip in one clock cycle.

The natural solution to the above problems. Fig 2. Mobile electronics are the target for many chips. as you may have guessed. These chips need to be even more conservative with power consumption in order to have a reasonable battery lifetime.power consumption becomes an even more crucial topic.1: ASYNCRONOUS VIEW . is to eliminate the source of these headaches: the clock.

When an asynchronous CPU completes an operation more quickly than anticipated. multiplication can be very fast when multiplying by 0 or 1. every change in the logical levels of its storage components is simultaneous. An operation might finish faster than normal because of attributes of the data being processed (e. Although there are faster circuits which have sophisticated performance but since they are depending of some other slow components for input and output of data then they can no long run faster than the slowest components.2 LOW SPEED A traditional CPU cannot "go faster" than the expected worst-case performance of the slowest stage/instruction/component. These transitions follow the level change of a special signal called the clock signal. the next stage can immediately begin processing the results. some delay is required for each logical operation. even when running code produced by a brain-dead compiler). Hence the performance of the synchronous system is limited to its worst case performance. so the behavior of the whole circuit can be predicted exactly.g.. Practically. The speed of execution will not be faster than that of the slowest circuit in the system and this will determine the final working performance of the system. resulting in a maximum speed at which each synchronous system can run.Chapter-3 PROBLEMS WITH SYNCRONOUS CIRCUITS Sy nchronous circuits are digital circuits in which parts are synchronized by clock signals. rather than waiting for synchronization with a central clock. Ideally. the input to each storage element has reached its final value before the next clock occurs. In an ideal synchronous circuit. or because .1 LOW PERFOMANCE In a synchronous system. 3. However there are several problems that are associated with synchronous circuits: 3. all the components are tied up together and the system is working on its worst case execution.

Data can be received and transmitted in any form of order regardless of there sequential order they arrive at the fist stage of execution. or a lower ambient temperature. 3. This is not a good sign for design of mobile devices too. this lead into high power dissipation by the synchronous circuit since they use central clock in their timings. This makes synchronous system more power consumer and hence not suitable for use in design of mobile devices and battery driven devices. The clock itself consumes about 30 percent of the total power supplied to the circuit and sometimes can even reach high value such as 70 percent.4 HIGH ELECTROMAGNETIC NOISE Since clock itself is crystal oscillator it is then associated with electromagnetic waves. 3. than 'normal' or expected. The designing of clock frequency should be so sophisticated since the frequency of the clock is fixed and poor march of design can result problem in the reusability of resources and interfacing with mixed-time environment devices.3 HIGH POWER DISSIPATION As we know that clock is a tiny crystal oscillator that keeps vibrating during all time as long as the system is power on. the clock is synchronous circuit and globally distributed over the components which are obviously in running in different speed and hence the order of arrive of the timing signal is not important.of the presence of a higher voltage or bus speed setting. The higher the speed of clock is the higher number of oscillations per second and this leak high value of electromagnetic noise and spectra emission. Even if the synchronous system is not active at the moment still its clock will be oscillating and consumes power that is dissipated as heat energy. These waves produce electromagnetic noise due to oscillations. Apart from the problems above. Noise will also be accompanied by emission spectra. .

.1 CLOCKLESS CHIPS IMPLEMENTATION In order to achieve asynchronous as final goal one must implement the electronic circuits without using central clock and hence make the system free from tied components obeying clock. Since the clock is installed only to enable the synchronization of components. One tricky technique is to use clockless chips in the circuit design. In this case the circuits are not tied up together and forced to follow the global clock timing signals but each and every component is loosely and they run at average speed. Asynchronous is can be achieved by implementing three vital techniques and these are: 4. by throwing away the global clock it is possible now for components to be completely not synchronized and the communication between them is only by handshaking mechanism. 4. Since these chips are not working with central clock and guarantee to free different components from being tied up together. Now as components can run on their own different performance and speed hence asynchronous is established.2 THROWING AWAY GLOBAL CLOCK There is no way one can success to implement asynchronous in circuits if there is global clock that is managing the whole system timing signals.Chapter-4 ASYNCRONOUS CIRCUITS Asynchronous circuits are the electronic digital circuits that are not govern by the central clock in their timing instead they are standardized in their installation and they use handshakes signals for communication to each other components.

"dual-rail" circuits. Synchronous ness can be split up if these components are not bound together and hence standardizing these components is one of the alternatives. All of these ideas and approaches are different enough that executing them could confound the mind of an engineer trained to design to the beat of a clock. 4. Fair additionally proposes replacing the conventional system of digital logic with what known as "null convention logic. not only to send bits. It's no surprise that the . But that means being far more meticulous about the physical design than synchronous designers have been trained to be. Such talent is scarce. Clocked chips represent ones and zeroes using low and high voltages on a single wire. thereby assuring that signals travel to the register in the proper logical sequence. giving the chip communications pathways. successful development of clockless chips requires the understanding of asynchronous design. One way to achieve this goal is to pay close attention to such details as the lengths of the wires and the number of logic gates connected to a given register. the values that arrive in registers must be correct the first time. but in a clockless chip. but also to send "handshake" signals to indicate when work has been completed." but also "no answer yet"-a convenient way for clockless chips to recognize when an operation has not yet been completed.3 STANDADISE OF COMPONENTS In synchronous system all the components are closed up together as to be managed by central clock." a scheme that identifies not only "yes" and "no. use two wires. on the other hand. Here all the components are going to be standard in a given range of working performance and speed. as asynchronous principles fly in the face of the way almost every university teaches its engineering students. Conventional chips can have values arrive at a register incorrectly and out of sequence. There is average speed in which the design of system is dedicated to compile and the worst case execution will be avoided.4 HOW CLOCKLESS CHIPS WORKS Beyond a new generation of design-and-testing equipment. An alternative is to open up a separate communication channel on the chip.4.

For a chip to be successful. all three elements-design tools. This technique has offered low power consumption and low electromagnetic noise and also there will of course be smooth data streaming. manufacturing efficiency and experienced designersneed to come together. data do not have to move at random and out of order as in synchronous in which the movement of data is no so essential. . The asynchronous cadre has very promising ideas. Asynchronous Digital Devices and Self-Timed Solutions. One component which needs to communicate with the other uses the handshake signals to achieve the establishment of connection and then with set up the time at which is going to send data and at the other side another component will also use the same kind of handshakes to harden the connection and wait for that time to receive data. And hence handshakes were the solution to overcome synchronization. In circuits implemented by clockless chips. In asynchronous circuits data are treated as very important aspect and hence do not move at any time they only and only move when are required to move in case such as transmission between several components. are populating now. There is now way one can obtain pure asynchronous circuits to be used in the complete design of the system and this is one of major barrier of clockless implementation but the circuits were successfully standardized and hence they do not have to be in synchronous mode.two newest asynchronous startups. and clockless-chip research has been going on the longest.

however.Chapter-5 COMPUTERS WITHOUT CLOCKS Asynchronous chips improve computer performance by letting each circuit run as fast as it can. As speeds have increased. In a computer with a speed of one Gigahertz. a clock distribution system delivers the timing signals from the crystal oscillator to the various circuits. the crystal “ticks” a billion times a second. Keeping the rhythm identical in all parts of a large chip requires careful design and a great deal of electrical power. Present day transistors can process data so quickly that they can accomplish several steps in the time that it takes a wire to carry a signal from one side of the chip to the other. must begin and end according to the clock’s timing signals. The synchronization provided by the clock helps chip designers plan sequences of actions for the computer. Since most modern computers use a single rhythm. Inside the computer’s microprocessor chip. a crystal oscillator that sets the basic rhythm used throughout the machine. complex calculations may take many steps. distributing the timing signals has become more and more difficult. 5. we call them synchronous. All operations. Each part of an asynchronous system may extend or shorten the timing of its steps when necessary.1 How fast is your personal computer? When people ask this question. Because all parts of the chip share the same rhythm. the output of any circuit from one step can serve as the input to any other circuit for the next step. much as a hiker takes long or short steps when walking across . The use of a central clock also creates problems. they are typically referring to the frequency of a minuscule clock inside the computer. just as sound in air delivers the beat of a drum to soldiers to set their marching space. Every action of the computer takes place in tiny step. for example.

rough terrain. but commercial success is still to come. The University of Tokyo and The California Institute of Technology had demonstrated asynchronous microprocessors. tried using asynchronous designs to build machines in the early 1950’s. We believe that asynchronous systems will become ever more popular as researchers learn how to exploit their benefits and develop methods for simplifying their design. In contrast each part of an asynchronous system takes as much or as little time for each action as it needs. Even though many other circuits on that chip may be able to complete their operations in less time. Some of the pioneers of the computer age. In the late 1990’s Sharp. such as mathematician Allen M Turing. We remain a long way from fulfilling the full promise of asynchrony. the Japanese electronics company used asynchronous design to build a data driven media processor – a chip for editing graphics. asynchrony may speed up computers. Some asynchronous chips are already in commercial mass production. 5. these circuits must wait until the clock ticks again before proceeding to the next logical step. .2 BEAT THE CLOCK What are the potential benefits of asynchronous systems? First. the chip cannot run faster than one gigahertz. the clock’s rhythm must be slow enough to accommodate the slowest action in the chip’s circuits. video and audio – and Philips Electronics produced an asynchronous microcontroller for two of its pagers. In a synchronous chip. the Ultra SPARC IIIi processor recently introduced by SUN includes some asynchronous circuits developed by our group. Asynchronous chipmakers have achieved a good measure of technical success. If it takes a billionth of a second for one circuit to complete its operation. Asynchronous parts of otherwise synchronous systems are also beginning to appear. Researchers at the University of Manchester in England. Engineers soon abandoned this approach in favour of synchronous computers because common timing made the design process so much easier. Now asynchronous computing is experiencing a renaissance.

. If the efforts required for local coordination are small. Systems with parts that act only occasionally benefit more than systems that act continuously. be faster than a clocked system. Asynchronous systems lack a fixed rhythm. on average. Most computers have components. Moreover. Asynchronous design may also reduce a chip’s power consumption. In asynchronous systems. but it can also cut the cost of larger systems by reducing the need for cooling fans and air-conditioning to prevent them from overheating. televisions and aircraft navigation systems that operates t the same frequencies. without waiting for the next tick of the clock. that often remain idle for long periods. emitting less at any one frequency. because the clock is always running. Asynchrony offers the most help to irregular chip designs in which slow actions occur infrequently. an asynchronous system may. idle parts of the chip consume negligible power. however. it generates heat whether or not the chip is doing anything useful. Coordinating as actions. The amount of power saved depends on the machine’s pattern of activity. it broadcasts a strong radio signal at its operating frequency and at the harmonics of that frequency. the circuits that deliver the timing signals take up a good chunk of the chip’s area. and simple ones can take les. In the current generation of large. This feature is particularly valuable for battery-powered equipment. such as the floating-point arithmetic unit. also takes time and chip area. as much as 30% of the electrical power used by the chip. Actions can start as soon as the prerequisite actions are done. Because of a clocked system uses a fixed rhythm. fast synchronous chips. must be devoted to the clock and its distribution system. as systems produce less ratio interference than synchronous machines do. so they spread their radiated energy broadly across the radio spectrum. In addition.Complex operations can take more time than average. Thus the systems speed depends on the average action time rather than the slowest action time. Furthermore. Such signals can interfere with cellular phones.

lower power consumption and less radio interference. link fast PCs with slower machines. Because of the circuits of an asynchronous system need not share a common rhythm. because data may be “out of sync” with the receiving clock. Moving data controlled by one clock to the control of another clock requires asynchronous bridges. although asynchronous design can be challenging.3 OVERVIEW/ CLOCKLESS SYSTEM  Most modern computers are synchronous: all their operations are coordinated by the timing signals of tiny crystal oscillators within the machines. Such a system is inherently asynchronous: different parts march to different beats.  Asynchronous systems rely on local coordination circuits to ensure an orderly flow of data. chip designers will need to learn asynchronous techniques. 5. These clusters can tackle complex problems by dividing the computational tasks among the PCs. for instance. Now researchers are designing asynchronous systems that can process data without the need for a governing clock. The two most important coordination circuits are called the Rendezvous and the Arbiter.  The potential benefits of asynchronous systems include faster speeds.5. replacing any part with a faster version will improve the speed of the entire system. it can also be wonderfully flexible. Finally. As integrated circuit become more complex. Moreover.4 LOCAL OPERATION . designers have more freedom in choosing the systems’ parts and determining how they interact.  Yet another benefit of asynchronous design is that it can be used to build bridges between clocked computers running at different speeds. Many computing clusters.

everyone can rest between buckets. Before each action.To describe how asynchronous systems work. each of which acts as a person in a bucket brigade. we often use the metaphor of the bucket brigade. Each person who holds a bucket can pass it to the next person down the line as soon as the next person’s hands are free. Bucket brigade Bucket brigades in computers are called pipelines. each person grasps the bucket pushed forward by the preceding person. but replacing the slowpoke will return the system to its best speed. The rhythm of this brigade cannot go faster than the time it takes the slowest person to move the heaviest bucket. A slow person will still hinder the performance of the entire brigade. Even if most of the buckets are light. When most of the buckets are light. when there’s no water to move. A clocked system is like a bucket brigade in which each person must pass and receive buckets according to the tick tock rhythm of the clock. they can move down the line very quickly. each person pushes a bucket forward to the next person down the line. When the clock tocks. When the clock ticks. Local cooperation rather than the common clock governs an asynchronous bucket brigade. . however. one person may have to wait until the other is ready. Moreover. Such a pipeline has half a dozen or so stages. A common pipeline executes the computer’s instructions. everyone in the line must wait for the clock to tick before passing the next bucket.

get the numbers from addresses A and B in memory.For example. a processor executing the instruction “ADD A B Chip” must fetch the instruction from memory. do the addition and store the sum in memory address C. . decode the instruction.

Processing logic Req Ack Req Ack Delay .

its output becomes TRUE. When both inputs of a Muller C-element are TRUE.Pipeline diagram Here a “bundled data” self-timing scheme is used. Without a clock to govern its actions. An acknowledge signal (ack) provides flow control. though. the duration of each action may depend on the operation performed the size of the numbers and the location of the data in memory (just as in bucket brigade the amount of water in a bucket may determine how long it takes to pass it on). These circuits exchange completion signals to ensure that the actions at each stage begin only when the circuits have the data they need. now retired from a professorship at the University of Illinois. In an asynchronous pipeline. an asynchronous system must rely on local coordination circuits instead. Delay . A clocked pipeline executes these actions in a rhythm independent of the operations performed or the size of the numbers. A Muller C-element is a logic circuit with two inputs and on output. One form of Rendezvous circuit is called the Muller C-element. so the receiving register can tell the transmitting register when to begin sending the next data. Asynchronous systems use these elements to wait until all the concurrent actions finish before starting the next action. The two most important coordination circuits are called the Rendezvous and the Arbiter circuits. A Rendezvous element indicates when the last of two or more signals has arrived at a particular stage. Requests may be delayed by at least the logic delay to insure that they still indicate data validity at the receiving register. named after David Muller. where conventional data processing logic is used along with a separate request (Req) line to indicate data validity.

For therefore. its inputs must not change again until its output responds.” . Muller C-element to act as a Rendezvous circuit. its output becomes FALSE. 5. Shown here is an electronic pipeline control by a chain of Muller C-elements. A chain of Muller C-elements can control the flow of data down an electronic bucket brigade.Processing logic When both inputs are FALSE. allowing data to flow in an orderly fashion without the need for a central clock.5 RENDEZVOUS CIRCUITS Rendezvous circuit It can coordinate the action of an asynchronous system. each of which allows data to pass down the line only when the preceding stage is “full” – indicating that data are ready to move – and the following stage is “empty. Otherwise the output remains unchanged.

An arbiter is like a traffic officer at an intersection who decides which car may pass through next. The inverter makes the initial inputs to the Muller C-element differ. it must decide which request to grant first. When an Arbiter gets two requests at once. Molnar. setting all stages empty at the start. its output changes to FALSE. Let’s assume that the left input is initially TRUE and the right input FALSE (1). A change in signal at the left input from TRUE to FALSE (2) indicates that the stage to the left is full that is.Each Muller C-element has two input wires and one output wire. Research groups recently introduced a new kind of Rendezvous circuit called GasP. This change in signals does three things: it moves data down the pipeline by briefly making the data latch transparent. TRUE signals are shown in blue and FALSE signals are in red. fit better with ordinary data latches and offer much greater versatility in complex designs. “G” is added to the name because GasP is what you are supposed to do when you see how fat our new circuits go. Because the inputs to the Muller C-element are now the same. and it sends a FALSE signal ahead to the next Muller Celement to make the right stage full (3). 5. at SUN Microsystems. .6 ARBITER CIRCUIT An arbiter circuit performs another task essential for asynchronous computers. which stands for asynchronous symmetric pulse protocol (the asterisk indicates the double “P”). Given only one request. some data have arrived. GasP evolved from an earlier family of circuits designed by Charles E. Molnar dubbed his creation asP*. The output changes to FALSE when both inputs are FALSE and back to TRUE when both inputs are TRUE (in the diagram. it sends a FALSE signal back to the preceding Celement to make the left stage empty.). an Arbiter promptly permits the corresponding action. It is found that GasP modules are as fast as and as energy-efficient as Muller C-elements. delaying any request until the first action is completed.

Each request to an Arbiter pushes the circuit toward one stable state or the other. usually within about a few hundred picoseconds. Although Arbiter circuits never grant more than one request at a time. The fundamental difficulty in making these decisions causes minor dilemmas. and in very rare cases the time needed to make a decision may be 10 times as long as normal. . the Arbiter puts the request into a sequence. granting access to only one processor at a time. there is no way to build an Arbiter that will always reach a decision within a fixed time limit. All that needed is a way to break the tie. which is equivalent to the Continental Divide. Similarly. For example. the circuits may occasionally take twice as long. two people approaching a doorway at the same time may pause before deciding who will go through first. Between the two stable states. which are familiar in everyday life. an Arbiter has two stable states corresponding to the two choices. When faced with close calls. however. there must be a meta-stable line. They can go through in either order. An Arbiter breaks ties. however. just as a hailstone that falls in the Rocky Mountains can roll downhill toward The Pacific or the Gulf. the circuit may pause in its meta-stable state before reaching one of its stable states to break the tie. The Arbiter guarantees that there are never two actions under way at once. If a hailstone falls precisely on the Divide. Like a flip-flop circuit. just as the traffic officer prevents accidents by ensuring that there are never two cars passing through the intersection on a collision course. it may balance momentarily on that sharp mountain ridge before tipping toward The Pacific or the Gulf. when two processors request access to a shared memory at approximately the same time.For example. One can think of these states as the Pacific Ocean and The Gulf of Mexico. Present-day Arbiters reach decisions very quickly on average. if two requests arrive at an Arbiter within a few picoseconds of each other.

Our initial goal was to build a counter flow pipeline with two opposing data flows – like two parallel bucket brigades moving in opposite directions. an Arbiter circuit permitted only one element at a time to pass. Arbitration turned out to be essential. The experiments at Manchester.7 THE NEED FOR SPEED Research group at Sun Microsystems concentrates on designing fast asynchronous systems. Caltech and Philips demonstrate that asynchronous microprocessors can be compatible with their clocked counterparts. This project proved very useful as a research target. We wanted the data from both flows to interact at each of these stages. The asynchronous processors can connect to peripheral machines without special programs or interface circuitry. the hard challenge was to ensure that every “northbound” data element would interact with every “southbound” data element. we learned a great deal about coordination and arbitration and built test chips to prove the reliability of our Arbiter circuits. We have found that speed often comes from simplicity. . At each joints between successive stages.5.

Important features include: * They * Parasitic have smaller capacitances are areas than smaller so conventional that higher CMOS operating logic. There are about four factors regarding pipeline and these are: 1. Dual rail Domino logic is a CMOS-based evolution of the dynamic logic techniques which were based on either PMOS or NMOS transistors. The structure is hence called Domino CMOS Logic.Chapter-6 SIMPLICITY IN DESIGN There in no complexity of a simple design for clockless chips. It allows a rail-to-rail logic swing. Delay insensitive 3. Integrated pipeline mode plays an important role in total system design. It was developed to speed up circuits.Domino logic 2. similar to a domino falling one after the other. speeds are . In a cascade structure consisting of several stages. The one fundamental achievement is to throw the central clock away and standardization of components can be used intensively. the evaluation of each stage ripples the next stage evaluation. Bundle data 4.

The main advantage of such circuits is their ability to optimize processing of activities that can take arbitrary periods of time depending on the data or requested function. This forces some input states or sequences to become illegal. * Charge distribution may be a problem Delay insensitive circuit is a type of asynchronous circuit which performs a logic operation often within a computing processor chip. * Only non-inverting structures are possible because of the presence of inverting buffer. as the entry and exit from this state will not be seen on the output of the gate. In a delay insensitive circuit. Similarly there may be output handshake signals indicating the readiness of the result and the safe delivery of the result to the next stage in a computational chain or pipeline. The Delay-Insensitive (DI) class is the most robust of all asynchronous circuit delay models. Typically handshake signals are used to indicate the readiness of such a circuit to accept new data (the previous computation is complete) and the delivery of such data by the requesting function. Instead the Quasi-Delay-Insensitive model is the smallest compromise model yet capable of generating useful computing circuits. no practical circuits are possible due to the heavy restrictions. An example of a process with a variable time for completion would be mathematical division or recovery of data where such data might be in a cache.possible. the arrival of data to the input of a sub-circuit triggers the computation to start. Instead. the sequencing of computation in delay insensitive circuit is determined by the data flow. For example OR gates must never go into the state where both inputs are one. the next computation can be initiated immediately when the result of the first computation is completed. * Operation is free of glitches as each gate can make only one transition. It makes no assumptions on the delay of wires or gates. there is therefore no need to provide a clock signal to determine a starting time for a computation. This condition stops unseen transitions from occurring. In this model all transitions on gates or wires must be acknowledged before transitioning again. Instead of using clock signals or other global control signals. Although this model is very robust. In DI circuits any transition on an input to a gate must be seen on the output of the gate before a subsequent transition on that input is allowed to happen. For this . Consequently.

* Data-dependent *All carry bits need delays. 6.reason circuits are often incorrectly referred to as Delay-Insensitive when they are Quasi-DelayInsensitive. Hence asynchronization of power is completely inevitable to achieve a low level of power dissipated. . Rest of the time the circuit returns to a non-dissipating state.2 ASYNCHRONOUS FOR LOW POWER Power consumption is very important aspect in designing any mobile and to increase the battery capacity and life for battery driven devices. to be computed. The figure shows how power is less confused by first taking down the frequency by dividing the give frequency to two and the next one show as many circuits are cascaded the more the frequency is divided. The circuit should consume power only when and where active. the following are basics to be implements. 6. The figure show first circuit being not asynchronous and then the second shows dual rail with every bit taken into computation. until next activation. This provides a crucial reduction on power consumption.1 ASYNCRONOUS OF HIGHER PERFOMANCE In order to increase the performance of the circuit.

At both Intel and Sun.which usually need low power sources . runs almost twice as long as competitors' products.6. this approach has led to prototype chips that run two to three times faster than comparable products using conventional circuitry. it can run at the average speed of all components.3 ASYNCRONOUS FOR LOW NOISE Any system with clock will be having oscillations in it and will create electromagnetic noise and this is the source of the actual noise one hears from convectional computers. enabling a huge savings in battery-driven devices. without needing to wait for everything else. for example. That makes them ideal for mobile communications applications . By contrast. The result? Instead of the entire chip running at the speed of its slowest components. an asynchronous-chip-based pager marketed by Philips Electronics. Chapter-7 ADVANTAGE OF ASYNCRONOUS CHIP A clocked chip can run no faster than its most slothful piece of logic. the answer isn't guaranteed until every part completes its work. the transistors on an asynchronous chip can swap information independently. For every clock cycle there will be spike emitted and emission of random spectra is accompanied together with noise. in which the clocks are constantly drawing power. Asynchronous chips use 10 percent to 50 percent less energy than synchronous chips. which use conventional clocked chips.and the chips' quiet . Clockless chips draw power only when there is useful work to do. This problem is greatly reduced to significant considerable range by discarding the central clock as explain above and the spectra radiation are much smoother in asynchronous circuits.

Such an attack would be far more difficult on a smartcard based on asynchronous logic. There's no clear signal to watch." says Fant. look now. This allows details of the chip’s inner workings to be deduced. believes that such chips will have twice the power of conventional designs. the more difficult it is to prevent a device from interfering with other devices. dispensing with the clock all but eliminates this problem. which will make them ideal . Potential hackers don't know where to begin. who is regarded as the guru of the field." Analyzing the power consumption for each clock tick can crack the encryption on existing smart cards. Asynchronous is more like a milling crowd. Okay. They can perform encryption in a way that is harder to identify and to crack. The combination of low noise and low power consumption makes asynchronous chips a natural choice for mobile devices.nature also makes them more secure. "The low-hanging fruit for clockless chips will be in communications devices. electronic funds exchange and personal identification. as typical hacking techniques involve listening to clock ticks." starting with cell phones Asynchronous logic would offer better security than conventional chips: "The clock is like a big signal that says. Ivan Sutherland of Sun Microsystems. Another advantage of clockless chips is that they give off very low levels of electromagnetic noise. The faster the clock. "It's like looking for someone in a marching band. Improved encryption makes asynchronous circuits an obvious choice for smart cards—the chip-endowed plastic cards beginning to be used for such security-sensitive applications as storage of medical records.

for use in high-performance computers. Replacing the conventional system of digital logic with what he calls "null convention logic. but also to send "handshake" signals to indicate when work has been completed. But Dr Furber suggests that the most promising application for asynchronous chips may be in mobile wireless devices and smart cards. Different styles There are several styles of asynchronous design. Another approach is called “bundled data”. Low and high voltages on 32 wires are used to represent 32 bits. and a change in voltage on a 33rd wire indicates when the values on the other 32 wires are to be used. and on the other wire a one. Sudden voltage changes on one of the wires represent a zero. not only to send bits. Conventional chips represent the zeroes and ones of binary digits (“bits”) using low and high voltages on a particular wire." but also "no answer yet"—a convenient way for clockless chips to recognize when an operation has not yet been completed. "Dual-rail" circuits use two wires giving the chip communications pathways. called “dual rail”. ." a scheme that identifies not only "yes" and "no. uses two wires for each bit. One clockless approach.

Low power dissipation. High performance. 4.Chapter-8 APPLICATION OF ASYNCRONOUS CHIP 1. A good match with heterogeneous system timing. 2. . Low noise and low electro-magnetic emission. 3.


However. potentially. part of this advantage is canceled by the overhead required to detect the completion of a step. it may be difficult to translate local timing variability into a global system performance advantage. Data-dependent delays The delay of the combinational logic circuit show in Figure-1 depends on the current state and the value of the primary inputs.8. an advantage that increases with the variability in delays associated with these computation steps. to a fundamental performance advantage for asynchronous circuits. the actual delay is always less (and sometimes much less) than the clock period.1 ASYNCHRONOUS FOR HIGH PERFORMANCE In an asynchronous circuit the next computation step can start immediately after the previous step has completed: there is no need to wait for a transition of the clock signal. is then a lower bound for the clock period of a synchronous circuit. Thus. The worst-case delay. plus some margin for flip-flop delays and clock skew. . This leads. Furthermore.

when each pair (cf i. . 0) to (0.2 ASYNCHRONOUS FOR LOW POWER Dissipating when and where active the classic example of a low-power asynchronous circuit is a frequency divider. 8. but the clock period must be 6 times longer! On the other hand.A simple example is an N-bit ripple-carry adder (Figure 2). Then the carry ripples from FA1 to FAN. In an asynchronous circuit this variation in delays can be exploited by detecting the actual completion of the addition. Most practical solutions use dualrail encoding of the carry signal (Figure 2(b)). which we consider next. the addition has completed when all internal carry-signals have been computed. A cascade of N such divide-by-two elements (Figure 4(b)) divide the incoming frequency by 2N. cti) has made a monotonous transition from (0. The worst-case delay occurs when 1 is added to 2N . when adding 1 to 0. The controller communicates exclusively with the controllers of the immediately preceding and succeeding stages by means of handshake signaling. the average length determines the average case delay of an asynchronous ripple-carry adder. 0) (carry = true). Assuming random inputs. That is. the completion can be observed from the outputs of the adder. and controls the state of the data latches (transparent or opaque). For a 32-bit wide ripple-carry adder the average length is therefore 5. Between the request and the next acknowledge phase the corresponding data wires must be kept stable.1. 1) (carry = false) or to (1. When inputs and outputs are dual-rail encoded as well. A D-flip-flop with its inverted output fed back to its input divides an incoming (clock) frequency by two (Figure 4(a)). the average length of the longest carry-propagation chain is bounded by log 2 N. as. In the best case there is no carry ripple at all. Dual-rail encoding of the carry signal has also been applied to a carry bypass adder. for example.

and so on. sometimes by several orders of magnitude 2. The potential of asynchronous for low power depends on the application. a similar synchronous divider would dissipate in proportion to N. independent of N. in many digital-signal processing functions the clock rate exceeds the data (signal) rate by a large factor. A cascade of 15 such divide-by-two elements is used in watches to convert a 32 kHz crystal clock down to a 1 Hz clock.The second element runs at only half the rate of the first one and hence dissipates only half the power. in a digital filter where the clock rate equals the data rate. That is. all flip-flops and all combinational circuits are active during each clock cycle. Then little or nothing can be gained by implementing the filter as an asynchronous circuit. For example. In contrast. The clock frequency is chosen that high to accommodate sequential algorithms that share resources over . this fraction may be highly data dependent. However. Hence. slightly less than twice the power of its head element. Furthermore. the entire asynchronous cascade consumes. only a small fraction of registers change state during a clock cycle. over a given period of time. fixed power dissipation is obtained. In such circuits. the third one dissipates only a quarter.

The single rail was clearly superior and consumed five times less power than the synchronous version. This noise may affect the performance of an analog-to-digital converter connected so as to draw power from the same source or that is integrated on the same substrate. 8. The filter bank for a digital hearing aid was the subject of another successful demonstration. One application for which asynchronous circuits can save power is Reed-Solomon error correctors operating at audio rates. Another example is that of a digital sub circuit that emits electromagnetic radiation at its clock frequency (and the higher harmonic frequencies). The result is a factor five less power consumption. Two different asynchronous realizations of this decoder (single-rail and dual-rail) are compared with a synchronous (product) version. and a radio receiver sub-circuit that mistakes this radiation for a radio signal. a digital sub circuit generates voltage noise on the power-supply lines or induces currents in the silicon substrate. They re-implemented an existing filter bank as a fully asynchronous circuit. A fourth application is a pager in which several power-hungry sub circuits were redesigned as asynchronous circuits. A second example is the infrared communications receiver IC designed at HewlettPackard/Stanford. most modules operate well below the maximum frequency of operation.3 ASYNCHRONOUS FOR LOW NOISE AND LOW EMISSION Sub circuits of a system may interact in unintended and often subtle ways. as shown later in this issue. For example. .subsequent computation steps. Also. as demonstrated at Philips Research Laboratories. which leads directly to prolonged battery life. this time by the Technical University of Denmark in cooperation with Oticon Inc. but can start up as soon as a signal arrives so that it loses no data. The receiver IC draws only leakage current while waiting for incoming data. One is vastly improved electrical efficiency.

Due to the absence of a clock. routers. Once asynchronous on-chip interconnect structures are accepted. gate delays rapidly decrease with each technology generation. Due to parasitic resistance and inductance in the on-chip and off-chip supply wiring this causes noise on the on-chip power and ground lines. Their combined effect results in an increasingly heterogeneous organization of system-on-a-chip timing. and multi-port memories. The introduction of additional interconnects layers and new materials (copper and low dielectric constant insulators) may slow down this trend somewhat. new circuits and architectures are required to circumvent these parasitic limitations. 8. across-chip communication may no longer fit within a single clock period of a processor core. asynchronous circuits may have better noise and EMC (Electro-Magnetic Compatibility) properties than synchronous circuits. This advantage can be appreciated by analyzing the supply current of a clocked circuit in both the time and frequency domains. According to Figure 7. and clock skew. Nevertheless. For example. By contrast. new opportunities will arise for asynchronous interconnect structures and protocols. the threshold to introduce asynchronous clients to these interconnects is lowered as well. Circuit activity of a clocked circuit is usually maximal shortly after the productive clock edge. Viewed differently. the delay of a piece of interconnect of fixed modest length increases. soon leading to a dominance of interconnect delay over gate delay. . including buses. Asynchrony makes it easier to deal with interconnecting a variety of different clock frequencies. It gradually fades away and the circuit must become totally quiescent before the next productive clock edge. Hence. Also. the clock signal modulates the supply current as depicted schematically in Figure 5(a). switch matrices. Heterogeneous system timing will offer considerable design challenge for system-level interconnect. mixed synchronous-asynchronous circuits hold promise. differences in clock phases and frequencies. without worrying about synchronization problems. FIFOs.4 HETEROGENEOUS TIMING There are two on-going trends that affect the timing of a system-on-a-chip: the relative increase of interconnects delays versus gate delays and the rapid growth of design reuse.

we are confident that the relentless advances in the speed and complexity of integrated circuits will force designers to learn asynchronous techniques. Because each part sets its own pace. Can chip designers create order out of the potential chaos of concurrent actions? Fortunately. accepted testing methods and widespread education in asynchronous design. asynchronous design will become prevalent. . Enumerating all the possible sequences of actions in a complex asynchronous chip is as difficult as predicting the sequences of actions in a school yard full of children. that pace may vary from time to time in any one system and may vary from system to system.Chapter-9 A CHALLENGING TIME Although the architectural freedom of asynchronous systems is a great benefit. A growing research community is making good progress. researchers are developing theories for tracking this problem. however. is inevitable: in he coming decades. We do not know yet whether asynchronous systems will flourish first within large computer and electronics companies or within start-up companies eager to develop new ideas. it also poses a difficult challenge. To continue the schoolyard metaphor. This dilemma is called the state explosion problem. Nevertheless. Designers need not worry about all the possible sequences of actions if they can set certain limitations on the communication behavior of each circuit. Another difficulty is that we lack mature design tools. The technological trend. but the present total investment in clock-free computing parlances in comparison with the investment in clocked design. they may finish in a large number of possible sequences. a teacher can promote safe play by teaching each child how to avoid danger. If several actions are concurrent.

and have already seen. A manufacturing cost increase of a couple of cents per chip can cause an entire line of computers to fail because of the large cost increase passed onto the customer. Therefore. The third place is in personal computers (PCs). This is an ideal place to implement a clock less chip because of the minimal power consumption. as is the case with mobile electronics. . Many prototypes will be necessary to create reliable designs. Also. clock less designs are in the lab. the manufacturing process must be improved to create a reasonably priced chip. The second place we’ll see these chips are in mobile electronics.Chapter-10 FUTURE SCOPE The first place we’ll see. It is essential in that market to create an efficient design that is reasonably priced. less interference is critical in designs with many components packed very tightly. low levels of electromagnetic noise creates less interference. Clock less designs will occur here last because of the competitive PC market. Manufacturing techniques must also be improved so the chips can be mass-produced.

but there are insignificant difficulties looming for clocked design in future. Self-timed design offers an alternative paradigm that addresses these problem areas. Inc. the examples available. .CONCLUSION Clocks have served the electronics design industry very well for a long time. but until now VLSI designers have largely ignored it. and there are significant rewards on offer to those brave enough to take the lead in its exploitation. power and design costs threaten to render the potential of future process technologies inaccessible to clocked design. where electrical noise. Things are beginning to change. and Cogency Technology. Although full-scale commercial demonstrations of the value of self-timed design are still few in number.. are beginning to be addressed. and a few companies (including a couple of start-ups. however. which are the lack of design tools and designers capable of handling self-timed design. The drawbacks.) have made significant commitments to the technology. demonstrates that there are no “show stoppers” to threaten the ultimate viability for this strategy. self-timed design is poised to emerge as a viable alternative to clocked design. Theseus Logic Inc. These difficulties are most obvious in complex SOC development. Self-timed technology is poised to make an impact.

and Steven M. Mark B. It's Time for Clockless Chips Å“ Claire Tristram from MIT Technology October 2001 6. 3. H. 2. August 2002.REFERENCES 1. Is it time for Clockless chips? Å“ David Geer published by IEEE Computer Society. 5. March 2005. Guest Editors˜ Introduction: Clockless VLSI Systems Å“ Soha Hassoun. Yong-Bin Kim and Fabrizio Lombardi copublished by IEEE CS and IEEE November Å“ December 2005. 4. (Kees) van Berkel. Computers without clocks Å“ Ivan E Sutherland and Jo Ebergen Scientific American. Nowick proceedings of IEEE. December 1998. Old tricks for new chips Apr 19th 2001 From The Economist print edition . Josephs. Scanning the Technology: Applications of Asynchronous Circuits Å“ C.