In linear algebra, Householder transformation is a linear transformation that is widely used in QR decomposition and finds application in communication systems, image and signal processing like adaptive beam forming, MIMO systems, channel equalization, echo cancellation etc. This paper describes the realization of available hardware architectures for the computation of Householder transformation based QR decomposition. Simulink supplied by Mathworks and System Generator developed by Xilinx ISE Design suite 14.4 is used for the realization of hardware architectures.

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In linear algebra, Householder transformation is a linear transformation that is widely used in QR decomposition and finds application in communication systems, image and signal processing like adaptive beam forming, MIMO systems, channel equalization, echo cancellation etc. This paper describes the realization of available hardware architectures for the computation of Householder transformation based QR decomposition. Simulink supplied by Mathworks and System Generator developed by Xilinx ISE Design suite 14.4 is used for the realization of hardware architectures.

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Householder Transformation based QR

Decomposition using Xilinx System Generator

Block Sets

Anju Rose Tom

PG Student

Department of Electronics & Communication Engineering

Toc-H Institute of Science & Technology Arakkunam, Kochi,

India

Prof. M. Mathurakani

Associate Professor

Department of Electronics & Communication Engineering

Toc-H Institute of Science & Technology Arakkunam, Kochi,

India

Abstract

In linear algebra, Householder transformation is a linear transformation that is widely used in QR decomposition and finds

application in communication systems, image and signal processing like adaptive beam forming, MIMO systems, channel

equalization, echo cancellation etc. This paper describes the realization of available hardware architectures for the computation

of Householder transformation based QR decomposition. Simulink supplied by Mathworks and System Generator developed by

Xilinx ISE Design suite 14.4 is used for the realization of hardware architectures.

Keywords: Hardware Architectures, Householder Transformation, Matrix Inversion, System Generator, QR

Decomposition

________________________________________________________________________________________________________

I.

INTRODUCTION

Matrix inversion and triangularization problems are common to wide variety of communication systems, signal and image

processing applications such as channel equalization, spatial filtering, adaptive beamforming, MIMO systems etc. All these

applications involve finding solution to a set of linear equations by computing matrix inversion. Using direct method, matrix

inversion takes O (n3) computational complexity and also increases the complexity in hardware implementation. Therefore, most

commonly used technique to carry out computationally intensive matrix inversion process is to decompose the matrix into

simpler factors. Decomposition methods provide analytic simplicity and computational convenience necessary for

computationally intensive matrix inversion. Matrix factorization involves analysis of data. QRD is widely employed in many

engineering areas intended to solve linear least square problems, linear system equations etc. Main focus is towards the

computation of QR decomposition using Householder transformation. In linear algebra, Householder (HH) transformation is a

linear transformation that describes the reflection about a plane containing origin. It is also known as Householder reflection or

elementary reflector. It is used to perform QR decomposition, also called QR factorization. This method allows us to change a

symmetric matrix into tridiagonal matrix with same set of Eigen values.

II. PROBLEM DEFINITION

The MGS algorithm computes Q and R matrices column by column by using vector projections, norm and other computations.

However, for fixed precision arithmetic, it offers reduced accuracy and numerical stability due to round off errors and loss of

orthogonality introduced during vector projections. Also, straightforward implementation of this algorithm requires

multiplication, division and square root operations which lead to high implementation complexity and high computational

latency. Givens rotations for matrices with large dimensions (eg 4*4) performing QRD using conventional sequence of Givens

rotations might lead to high computational complexity due to large number of vectoring/rotation operations.

Alternative method for better QR decomposition compared to other schemes is Householder Transformation. By using a

unified hardware architecture based on Householder transformation can achieve fast and area efficient QR factorization. As a

result, area and power requirements for the procedure are reduced without decreasing the overall speed. However, it is not

straightforward to carry out multiple reflections in parallel which could have helped to speed up the QR decomposition process.

To resolve this issue, novel Householder CORDIC algorithms is utilized by using sequences of simple Householder reflections

which can be easily implemented using shift, carry- save - addition (CSA) and simple addition operations.

202

Realization of Hardware Architectures for Householder Transformation based QR Decomposition using Xilinx System Generator Block Sets

(IJSTE/ Volume 2 / Issue 08 / 037)

The Householder transformation (HH) was introduced in 1958 by Alston Scott Householder. In solving the linear simultaneous

equations A*x = b by Gaussian elimination, we apply elementary row transformations to the matrix A which is equivalent to

pre-multiplying A by a non-singular matrix P which is not necessary to be orthogonal. Then we solve the triangular system of

equations P*Ax = P*b by back substitution. The numerical instability to may increase i.e || Pv|| may be greater than ||v||. To

resolve this issue, orthogonal transformation can be applied since norm of a vector remains invariant under orthogonal

transformation i.e. ||v|| = ||Rv||. To improve numerical stability, orthogonal transformations are therefore recommended.

Householder transformation which is orthogonal in nature will be used for performing QR decomposition. The proposed

methodology can also be used for triangularization of an arbitrary matrix and tridiagonalization of a symmetric matrix.

Consider a unit vector w with unit length, the matrix P of the form:P = I 2wwT, where w * wT= 1

(1)

is called Householder transformation. If w is real, then P is orthogonal and symmetric. Given a non- zero vector x =

[x1,..,xk]T there exists a HH transformation, PK = I 2wwT of order K such that

Pkx = e1

(2)

Where is a real number, e1 = [1 0 .. 0]T is an elementary vector in RK and I is an identity matrix of order K. If w is real,

then matrix P is orthogonal and symmetric. Under transformation P, a n-vector x can be reduced to a vector whose elements

except for the first row are equal to zero. Let m be a positive number defined by:m = ||x||2 = (x21 + x22 + + x2k)1/2

(3)

T

Since, Pk Pk = I, it now follows from (2) that

m2 = ||x||22 = xTPTkPkx = 2e1Te1 = 2

(4)

Hence, = m = ||x||2

(5)

Using the expression given on right hand side of (1) for Pk where w = [w1,.,wk]T in Rk and equating components of both

sides of (2), we have

x1 2w1(wTx) = = m

(6)

xi 2wi (wTx) = 0

where i = 2,,k (7)

In order to determine the unknown vector w, set wTx = q. We have,

2w1q= x1 m,

2wiq = xi, i = 2,,k

(8)

Observing that wTw = w21 + .+ w2k = 1, by squaring and adding the equations (8) we get

4q2 = (x1 m)2 + x22 +..+ x2k

= 2(m2 x1m)

(9)

Hence,

2q2=m (mx1)

(10)

is known. Therefore, from (9) it follows that

w = (2q)-1u where u = [x1 m, x2,,xk]T

(11)

and from (2) implies

Pk = I (2q2)-1uuT

(12)

The above Householder transformation algorithm can be realized by following hardware architectures under Simulink

environment using System Generator block sets from Xilinx ISE Design Suite.

Fixed Point Architecture

In fixed precision environment, Gram-Schmidt orthogonalization and its variants are susceptible to round off errors and loss of

orthogonality due to vector projections. Householder reflections are useful in introducing zeros on large scale. Also, it is

commonly used technique due to its stability, accuracy and ease of implementation on parallel and pipelined systolic array

structure. Here, the fixed point architecture is realized using block sets under Simulink environment for one iteration. Input

vector [4 2] is given to the model from workspace.

203

Realization of Hardware Architectures for Householder Transformation based QR Decomposition using Xilinx System Generator Block Sets

(IJSTE/ Volume 2 / Issue 08 / 037)

Fig. 1: Realization of Fixed Point Achitecture using System Generator block sets

Iterative Architecture:

An area efficient low power implementation of QR algorithm using Householder method can be performed using iterative

architecture. The proposed design realized for an iteration using system generator block sets uses same hardware blocks to

calculate each step in the algorithm to reduce the area of the overall design. The main focus is to implement unified division,

square root and inverse square root block into QR algorithm by focusing on fixed iteration division, square root and inverse

square root analysis. The iterative architecture is realized under Simulink environment by using System Generator block sets

from Xilinx ISE Design Suite 14.4.

Vectorized Architecture:

Matrix computations are often expressed in terms of plane rotations which may be implemented using CORDIC arithmetic. As

matrix size increases, microprocessor systems employing traditional CORDIC arithmetic which operates on 2D vectors become

unable to achieve sufficient speed. Speed may be increased by expressing the matrix computations in terms of higher

dimensional rotations and implementing these rotations using novel CORDIC algorithms called Householder CORDIC that

extend CORDIC arithmetic to arbitrary dimensions. Householder CORDIC algorithms consist of sequences of simple

Householder reflections.

204

Realization of Hardware Architectures for Householder Transformation based QR Decomposition using Xilinx System Generator Block Sets

(IJSTE/ Volume 2 / Issue 08 / 037)

The complex vector x0 + jy0 = 11 + j1 is given as input to the unit. The results are found after one iteration and yields x 1 + jy1

= 11.5 j4.5. In this design, quantization scheme of (16,8) is used with 8 bits for precision, 7 bits for dynamic range and 1 bit for

sign. The rotated vector is scaled by a cosine term which becomes constant and is equal to 0.6057. Design uses shift and add

units for scale correction instead of conventional multipliers in order to save area and power. The control input to each CORDIC

unit is designed to configure the unit in either vector or rotation mode.

Algebraic / Approximation Methods:

Algebraic method/approximation method is based on floating point unit for optimized matrix factorization based on Householder

transformation. A LAC (Linear Algebra Core) achieves orders of magnitude better efficiency in power and area consumption

compared to conventional general purpose architectures. It is specifically optimized to perform rank-1 updates that form the

inner kernels of parallel matrix multiplication. Fig 4 shows the realization of architecture for one iteration with input vector [5 6]

and obtained the results for one iteration at MATLAB workspace.

Fig. 4: Realization of Algebraic/ Approximation methods using System Generator block sets

205

(IJSTE/ Volume 2 / Issue 08 / 037)

IV. CONCLUSION

QR decomposition involves factorization of a matrix into simpler factors for the easiness of computationally intensive matrix

inversion process. Householder method (HHM) can be made time efficient by employing an intelligent hardware/software codesign model. In this paper, it describes the available four hardware architectures for the computation of Householder based QR

decomposition. The hardware architectures were realized using Xilinx System Generator design tool 14.4 under Simulink

environment. Simulink is a block diagram environment for multi-domain simulation and model based design. It supports system

level design, simulation, automatic code generation and continuous test and verification of embedded systems. Simulink

provides graphical editor, customizable block libraries and solvers for modelling and simulating dynamic systems. It is

integrated with MATLAB which enables to in cooperate MATLAB algorithms into models and export simulation results to

MATLAB for further analysis.

REFERENCES

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Milos D. Ercegovac and Tomas Lang, Reciprocation, Square Root, Inverse Square Root and some Elementary functions using Small Multipliers, IEEE

Transactions On Computers, Vol. 49, No. 7, July 2000.

Jose-Alejandro Pineiro, Stuart F. Oberman, High-Speed Function Approximation Using a Minimax Quadratic Interpolator, IEEE Transactions On

Computers, Vol. 54, No. 3, March 2005.

Zahid Khan, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan, Area & Power Efficient VLSI Architecture for Computing Pseudo Inverse of Channel

Matrix in a MIMO Wireless System, Proceedings of the 19th International Conference on VLSI Design (VLSID06) Vol. 49, No. 7, July 2006.

Semih Aslan, Erdal Oruklu and Jafar Saniie, Realization of Area Efficient QR Factorization using unified Division, Square Root and Inverse Square Root

Hardware, IEEE Transactions On Computers, Vol. 57, No. 5, June 2009.

A. S. Dhar, FPGA Implementation of a High Speed VLSI Architecture for CORDIC, 9781424445479/09/$26.00 c 2009 IEEE TENCON,Vol. 58,No.

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