You are on page 1of 8

DIFFERENTIAL AMPLIFIER

PRACTICE PROBLEMS
Masum Hossain

Problem 1 For an NMOS differential pair with a common-mode voltage VCM applied,
as shown in Fig. 8.2, let VDD = VSS = 1.0V, kn = 0.4 mA/V2, (W/L)1,2 = 12.5, Vtn = 0.5 V, I =
0.2 mA,
RD = 10k, and neglect channel-length modulation.
(a) Find VOV and VGS for each transistor.
(b) For VCM=0, find VS, ID1, ID2, VD1, and VD2.
(c) Repeat (b) for VCM = +0.3 V.
(d) Repeat (b) for VCM = -0.1 V.
(e) What is the highest value if VCM for which Q1 and Q2 remain in saturation?
(f) If current source I requires a minimum voltage of 0.2 V to operate properly,
what is the lowest value allowed for VS and hence for VCM?

Figure 8.2 The MOS differential pair with a commonmode input voltage VCM.

Problem 2
For the differential amplifier specified in Assignment 1., let vG2 = 0 and
vG1 = vid . Find the value of vid that corresponds to each of the following situations:
a. iD1 = iD2 = 0.1mA
b. iD1 = 0.15 mA and iD2 = 0.05mA
c. iD1 = 0.2mA and iD2 = 0 (Q2 just cuts off)
d. iD1 = 0.05mA and iD2 = 0.15mA
e. iD1 = 0.mA (Q1 just cuts off) and iD2 = 0.2mA
For each case, find vS , vD1 , vD2 and (vD2 vD1)

Figure 8.2 The MOS differential pair with a commonmode input voltage VCM.

Problem 3
Consider the differential amplifier specified in Assignment 1 with G2 grounded
and vG1 = vid . Let vid be adjusted to the value that causes iD1 =0.11mA and
iD2 =0.09mA. Find the corresponding values of vGS2,vS , vGS1 , and hence vid.
What is the difference output voltage vD2 vD1 ? What is the voltage gain
(vD2 vD1 )/vid ? What value of vid result in iD1 = 0.09mA and iD2 = 0.11mA?

Figure 8.2 The MOS differential pair with a commonmode input voltage VCM.

Problem 4
a.

For the MOS differential amplifier of Fig. 8.1 with vG!=VCM + vid/2 and vG2=VCM - vid/2, use Eqns.
(8.23) and (8.24) to derive expression for the output differential voltage vod =vD2 vD1 in terms of
the input differential voltage vid.
b. Sketch and clearly label the voltage transfer characteristic (VTC), that is, vod versus vid , over the
range -2VOV vid 2VOV , where VOV is the overdrive voltage at which each transistor is operating
in the equilibrium state. What is the slope of nearly linear portion of the VTC near the origin? The is
the differential voltage gain.
c. Show on the same coordinates how the VTC change if the bias current I is doubled? What is the
change in the differential voltage gain ?
d. Prepare another sketch for case (b) . Show on the same coordinates what happens to the VTC if
the W/L ratio of each transistor is doubled. What is the change in the differential voltage gain?

Problem 5
An NMOS differential amplifier is operated at a bias current I of 0.4mA
and has a W/L ratio of 32,n Cox = 200A/V2 , Vd= 10 V, and RD = 5k.
Find VOV , gm , ro, and Ad.

Problem 6
Figure P8.24 shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form
the differential pair, while the current source transistors Q3 and Q4 form the active loads for Q1
and Q2 , respectively. The dc bias current that establishes an appropriate dc voltage at the
drains of Q1 and Q2 is not shown. It is required to design the circuit to meet the following
specifications:
a. Differential gain, Ad = 80V/V
b. IREF = I = 100A
c. The dc voltage at the gates of Q6 and Q3 is +1.5V
d. The dc voltage at the gates of Q7 , Q4 and Q5 is +1.5V
The technology available is specified as follows : n Cox = 3p Cox = 90A/V2 , Vtn = |VAP| = 20V.
Specify the required value of R and the W/L ratios for all transistors. Also specify ID and |VGS| at
which each transistor is operating. For dc bias calculations you may neglect channel-length
modulation.

Problem 7

For the cascode differential amplifier of Fig. 8.12(a) show


that if all transistors have the same channel length and
are operated at the same |VOV| and assuming that
VAn=|VAp|= |VA|, the differential gain Ad is given by
Ad = 2(|VA|/|VOV|)2
Now design the amplifier to obtain a differential gain of
100V/V. Use |VOV|= 0.2V. If |VA| = 10V/m, specify the
required channel length L. If gm is to be as high as
possible but the power dissipation in the amplifier (in
equilibium) is to be limited to 1mW, what bias current I
would you use? Let VDD = -VSS = 0.9V