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IEEE Asian Solid-State Circuits Conference

8-2

November 12-14, 2007 / Jeju, Korea

A 8-bit 500-KS/s Low Power SAR ADC for BioMedical Applications


You-Kuang Chang, Chao-Shiun Wang and Chorng-Kuang Wang
Graduate Institute of Electronics Engineering and Department of Electrical Engineering,
National Taiwan University, Taipei, Taiwan.
AbstractThis paper presents a successive approximation
register analog-to-digital converter (SAR ADC) design for
bio-medical applications. An energy-saving switching
sequence technique is proposed to achieve low power
consumption. The average switching energy of the capacitor
array can be reduced by 56% compared to a conventional
switching method. The measured signal-to-noise-anddistortion ratios of the ADC is 46.92 dB at 500KS/s sampling
rate with an ultra-low power consumption of only 7.75-W
from a 1-V supply voltage. The ADC is fabricated in a 0.18m CMOS technology.
Index TermsSuccessive approximation register analog-todigital converter (SAR ADC), low power, bio-medical
application.

I.

INTRODUCTION

Over the past years, many researches on successiveapproximation-register analog-to-digital converters (SAR
ADC) have been published [1]-[3] for applications which
require low-power dissipation. The SAR ADC
architecture is well suitable for large-scale wireless sensor
networks and bio-medical applications due to its
moderate speed, moderate resolution and very low-power
consumption characteristics. The primary sources of
power consumption in a SAR ADC are the comparator
and charge/discharge of the capacitor array. The energy
dissipation required to charge/discharge the capacitor
array is dominated by the switching sequence. The
conventional switching sequence is an inefficient
procedure and much of energy is wasted on charging and
discharging the capacitor array.
This paper proposes an energy-saving switching
sequence technique to minimize the power consumption
of the capacitor array and the details about circuit design
are organized as followings: the ADC architecture and
energy-saving switching sequence technique is discussed
in Section 2 and the building block circuit designs are
presented in Section 3. The measurement results are
summarized in Section 4. Finally, summary of this design
is offer in Section 5.
II.

ADC ARCHITECTURES

Figure 1 shows the SAR ADC architecture which


consists of a binary-weighted capacitor array, a
comparator, a SAR control unit and switches. Combining
with the capacitor splitting technique proposed by [4], the
MSB/2 capacitor is split into parallel binary-weighted sub

1-4244-1360-5/07/$25.00

2007 IEEE

capacitor array to save the energy required during a


down transition. The operation of the ADC is based on
the binary search algorithm which is accomplished by the
capacitor array, the SAR control unit, and the comparator.

2n-3C

2C C

2n-1C

2n-3C

2C C

2n-1C

2n-3C

2C C

Gnd
Vdd
Vin

Vdd
Vdd

SAR
Control Unit

D1
D2
Dn

Vip
Vdd
Gnd
2n-3C

2C C

Fig. 1. Successive-approximation-register ADC architecture.

It is instructive to calculate the total energy drawn


from Vref when switching the capacitor array. For
alleviating the computation, a 3-bit capacitor array is taken
as an example. Fig. 2(a) shows all possible paths to
convert an analog signal to digital signal in conventional
SAR ADC and the energy consumption of each switching
phase is calculated. If each path is equiprobable, it can be
shown that the first switching phase consumes the most
energy in a conversion period. Furthermore, even though
the conventional switching sequence can charge the
capacitor array efficiently during the down paths of each
switching phase in Fig. 2(a), it is highly inefficient in the
up paths. The average switching energy for an n-bit SAR
ADC to convert an analog signal to digital signal can be
derived as:
n

Etotal ,nbit = 2n+12i (2i 1)CVref2

(1)

i =1

In order to reduce the energy consumption, the


proposed energy-saving switching sequence modifies the
switching sequence as shown in Fig. 2(b). Compared to
the conventional architecture consuming 4CVref2 Joules,

228

Switching Phase 3
Switching Phase 2

Vref

Vin Vin Vin Vin


4C 2C C C

4CVref2

Vref
4C 2C

5CVref2

Switching Phase 1

Vref

Vref
4C 2C

C
Vip-Vin > 0 ?

4C 2C C C
Vip Vip Vip Vip

4C 2C C C
Vref Vref Vref

Vref Vref
4C 2C

2
ref

CV

4C 2C C C
Vref Vref

C
Vip-Vin > 3Vref/4 ?

Vip-Vin > Vref/2 ?


4C 2C C C
Vref
Vref Vref

Vref
4C 2C C

9
CVref2
4

5
CVref2
4

4C 2C C C
Vref Vref
Vref
Vref Vref
4C 2C C C
Vip-Vin > Vref/4 ?
4C 2C C C
Vref
Vref
Vref
Vref
4C 2C C C

13
CVref2
4

Vip-Vin > -Vref/4 ?

4C 2C C C
Vref
Vref
Vip-Vin > -Vref/2 ?
Vref Vref Vref
4C 2C C C

1
CVref2
4

Vip-Vin > -3Vref/4 ?


4C 2C

Vref

(a)
C

Vref
C

4C

4C

Switching Phase 3

Vref Vref
C C

Switching Phase 2

1
CV ref2
4

Vip-Vin > 3Vref/4 ?


Vref

4C

C
C
Vref
Vref Vref
C
C

Vip-Vin > Vref/2 ?

Vin Vin
C
C
Vin
4C

Vin Vin
C C

Vref

Switching Phase 1

5
CV ref2
4

4C

Vref
C

4C

Vip-Vin > Vref/4 ?


Vref

4C

C
C

Vref

Vip-Vin > 0 ?
4C

C C
Vip Vip
C

C C
Vref Vref
C

Vref
4C
Vip

4C
Vref

3CVref2

Vref Vref

C
C
C

Vip Vip

3CV ref2

Vref
4C

Vref
4C

5
CVref2
4

Vip-Vin > -Vref/4 ?


4C

Vref Vref
C C

Vref Vref

1
CV ref2
4

(b)

Vref

C
C
Vref Vref
Vref
C
C

Vip-Vin > -Vref/2 ?


4C

Vref
C
C

Vref
4C

Vref Vref
C
C
Vip-Vin > -3Vref/4 ?

4C

C
Vref

Fig. 2. (a) Conventional Switching Sequence. (b) Proposed energy-saving switching sequence.

the energy-saving switching sequence consumes no power


in the first switching phase. Moreover, the energy-saving
switching sequence combines capacitor splitting technique
which splits MSB/2 capacitor into parallel binaryweighted sub capacitor array to efficiently reduce the
energy required during the up paths of each switching
phase in Fig. 2(a). The difference of two switching
methodologies can be observed in detail in Fig. 2. The
average switching energy for an n-bit SAR ADC using
proposed energy-saving switching sequence can be
derived as:

applicable to any bit of SAR ADC. For an 8-bit SAR ADC,


it consumes 339CVref2 Joules using conventional switching
sequence while the proposed energy-saving switching
sequence only consumes 148CVref2 Joules which achieves
56% energy saving in switching the capacitor array
compared to the conventional one. Fig. 4 shows the energy
comparison of two switching sequences for every output
code in a conversion period. The larger the output code,
the more switching energy required for conventional
sequence while the switching energy for each output code
almost remains the same for energy-saving sequence.

Etotal ,nbit = 3 2 n3 + 2 n+12i (2i 1 1)CVref2

(2)

i =3

The average switching energy, Etotal,n-bit, of two


switching sequences for an n-bit capacitor array is shown
in Fig. 3. The energy-saving switching sequence is

III.

CIRCUIT DESIGN

A. Capacitor Array
The linearity of the SAR ADC is dependent upon the

229

Average Switchgin Energy, (CV 2)

10

10

10

10

Conventional
Energy-Saving

5
10
n-bit Capacitor Array

15

Fig. 3. The average switching energy of two sequences for an n-bit SAR
ADC.

B. Comparator
The comparator circuit is shown in Fig. 6.The operation
principle is described below. When Vclk is low, the
comparator is in precharge phase. Nodes Vout+ and Voutare precharged to Vdd by transistors M5 and M6. Because
M9 is off at this time, no dc current flows from Vdd to
ground. When Vclk is high, the comparator is in
comparison phase. At this time, Vout+ and Vout slew
towards ground at unequal rates according to the
differential input voltage Vin+ and Vin-. Once the voltages
of Vout+ and Vout- are low enough, the PMOS positive
feedback load formed by M7 and M8 latches the
comparator. When the comparator is in steady-state, there
is also no dc current flowing from Vdd to ground.
Therefore, it is suitable for low power application due to
no static current consumption.

Switching Energy (CV2)

500

Vdd

Conventional
Energy-Saving

400

Vclk

M5

300

M7

M8

Vout-

200

Vout+
M3

100
0

50

100
150
Output Code

200

M4

Vclk

Vin+

M1

250

Vclk

M6

M2

Vclk

Vin-

M9

Fig. 4. The energy versus output code required for the switching of the
capacitor array.
Fig. 6. Comparator circuit.

capacitor matching in the capacitor array. Each capacitor


in the capacitor array consists of numbers of unit
capacitors. A unit capacitance of 20fF metal-insulatormetal capacitor (MIMCAP of 4m 4m) is chosen to
guarantee the 8-bit linearity requirement. A layout
floorplan of the capacitor array is depicted in Fig. 5. In
order to improve linearity and tolerate process gradients,
common-centroid layout technique is utilized. A dummy
capacitor ring is also used on the edges of the capacitor
array to ensure that all unit capacitors in the capacitor
array have the same structure around them.

C. Successive Approximation Register


Figure 7 shows the SAR which provides control signals
to the capacitor array to implement the energy-saving
switching sequence.

Set
Q

QB

32

32

128
16
4
4

8
8

Reset

QB
Reset

Reset

Set
Switch
Control

Reset
Set
D

QB
Reset

32

Reset
Set

Logic

Switch
Control

Q
QB

Reset
Set

Logic

QB

S2

Logic

Q
QB

Reset

Reset
S1

Set
Switch
Control

Q
QB

QB

16
128

32

QB

QB

DUMMY

DUMMY

16

16

Set

32

128
2 1 1 2
2 1 1 2
128

S7
Set

Comp

128

4
4

S6
Set

CLK

32

8
8

S1
Set

QB

Reset

DUMMY
128

Bit cycling

Sample
Set

Reset
S7

128
32

32
128
DUMMY

Fig. 7. SAR schematic.

Fig. 5. The layout floorplan of the capacitor array.

230

IV.

MEASUREMENT RESULTS

The ADC is fabricated in a standard 0.18-m CMOS


process. A chip photograph is shown in Fig. 8. The total
chip size occupies 1 1 mm2 and the core size measures
250 320 m2.

power dissipation makes it well-suited for bio-medical


applications.
FFT

Amplitude [dB]

-20
-40

Fin @ 231KHz
SNDR = 46.92 dB
ENOB = 7.5 bits
SFDR = 62.69 dB

-60
-80
-100
0

The static performance is characterized through


differential nonlinearity (DNL) and integral nonlinearity
(INL) measurement. The measured DNL and INL are
+0.17/-0.24 LSB and +0.31/-0.28 LSB, respectively.

6
5
ENOB

DNL (LSB)

250

4
3
2

100
150
200
250
DIGITAL OUTPUT CODE
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
1
INL(LSB)

200

ENOB vs Input Frequency

DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE


1

50

1
0
0

0
-1
0

100
150
Frequency [kHz]

Fig. 10. Measured FFT spectrum at input frequency of 231-KHz.

Fig. 8. Die photograph.

-1
0

50

50

100
150
Input Frequency [KHz]

200

250

Fig. 11. ENOB versus input frequeny.


50

100
150
200
DIGITAL OUTPUT CODE

250

Fig. 9. Measured DNL and INL error..

ACKNOWLEDGMENT

The measured FFT spectrum at input frequency close to


Nyquist rate is shown in Fig. 10. The measured SNDR is
46.92 dB which equals to ENOB of 7.5 bits and the SFDR
is 62.69 dB. Fig. 11 plots the ENOB of the ADC as a
function of input frequency. The total power dissipation of
the ADC is 7.75-W at 500-KS/s sampling rate and supply
voltage of 1-V. The typical figure of merit (FOM)
definition of the ADCs is defined as:

FOM =

Power
2 ENOB f s

(3)

The FOM of this work corresponds to 86fJ/conversionstep and is better than previous publications [2][3].

The authors would like to thank National Science


Council (NSC 95-2220-E-002-012), Chip Implementation
Center (CIC) for supporting this work and chip
implementation.

REFERENCES
[1]

[2]

[3]

[4]

V.

CONCLUSIONS

A 1-V 8-bit 500-KS/s SAR ADC using proposed


energy-saving switching sequence is realized in a
standard 0.18-m CMOS technology. The feature of low

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Wireless Micro-Sensor Applications, ISSCC Dig. Tech. Papers,
pp. 222-223, Feb. 2006.
B. P. Ginsburg and A. P. Chandrakasan, An energy-efficient
charge recycling approach for a SAR converter with capacitive
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pp. 184-187.

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