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Objectives

There are two basic ways to design clocked sequential circuits. These are

using:

1. Mealy Machine, which we have seen so far.

2. Moore Machine.

1. Study Mealy and Moore machines

2. Comparison of the two machine types

3. Timing diagram and state machines

Mealy Machine

In a Mealy machine, the outputs are a function of the present state and the

value of the inputs as shown in Figure 1.

change in the inputs.

Mealy Machine

In a Moore machine the outputs depend only on the present state as shown in

Figure 2.

A combinational logic block maps the inputs and the current state into the

necessary flip-flop inputs to store the appropriate next state just like Mealy

machine.

inputs are only the flip-flops state outputs.

1

The outputs change synchronously with the state transition triggered by the

active clock edge.

Consider a finite state machine that checks for a pattern of ‘10’ and asserts

logic high when it is detected.

The state diagram representations for the Mealy and Moore machines are

shown in Figure 3.

The state diagram of the Mealy machine lists the inputs with their associated

outputs on state transitions arcs.

The value stated on the arrows for Mealy machine is of the form Zi/Xi where

Zi represents input value and Xi represents output value.

A Moore machine produces a unique output for every state irrespective of

inputs.

Accordingly the state diagram of the Moore machine associates the output

with the state in the form state-notation/output-value.

The state transition arrows of Moore machine are labeled with the input value

that triggers such transition.

can be generated in fewer states using Mealy machine as compared to Moore

machine. This was illustrated in the previous example.

2

Figure 3: Mealy and Moore State Diagrams for '10' Sequence Detector

Timing Diagrams

To analyze Mealy and Moore machine timings, consider the following

problem. A state-machine outputs ‘1’ if the input is ‘1’ for three consecutive

clocks.

3

Mealy State Machine

Note that there is no reset condition in the state machine that employs two flip-

flops. This means that the state machine can enter its unused state ‘11’ on start

up.

To make sure that machine gets resetted to a valid state, we use a ‘Reset’

signal.

The logic diagram for this state machine is shown in Figure 5. Note that

negative edge triggered flip-flops are used.

Since the output in Mealy model is a combination of present state and input

values, an unsynchronized input with triggering clock may result in invalid

output, as in the present case.

Consider the present case where input ‘x’ remains high for sometime after

state ‘AB = 10’ is reached. This results in ‘False Output’, also known as

‘Output Glitch’.

4

Figure 6: Timing Diagram for Mealy Model Sequence Detector

The Moore machine state diagram for ‘111’ sequence detector is shown in

Figure 7.

The state diagram is converted into its equivalent state table (See Table 1).

The states are next encoded with binary values and we achieve a state

transition table (See Table 2).

5

Table 1: State Table

Present Next State Output

Present Next State Output

State x=0 x=1 Z

Initial Initial Got-1 0

Got-1 Initial Got-11 0

Got-11 Initial Got-111 0

Got-111 Initial Got-111 1

Present Next State Output

State x=0 x=1 Z

Initial Initial Got-1 0

Got-1 Initial Got-11 0

Got-11 Initial Got-111 0

Got-111 Initial Got-111 1

We will use JK and D flip-flops for the Moore circuit implementation. The

excitation tables for JK and D flip-flops (Table 3 & 4) are referenced to

tabulate excitation table (See Table 5).

Q(t) Q(t+1) J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Q(t) Q(t+1) D

0 0 0

0 1 1

1 0 0

1 1 1

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Table 5: Excitation Table for the Moore Implementation

Inputs of Outputs of

Comb.Circuits Next Comb.Circuit

Output

Present State Flip-flop

Input

State Inputs

A B X A B JA KA DB Z

0 0 0 0 0 0 X 0 0

0 0 1 0 1 0 X 1 0

0 1 0 0 0 0 X 0 0

0 1 1 1 0 1 X 0 0

1 0 0 0 0 X 1 0 0

1 0 1 1 1 X 0 1 0

1 1 0 0 0 X 1 0 1

1 1 1 1 1 X 0 1 1

o JA = X.B

o KA = X’

o DB =X(A + B)

o Z=A.B

Figure 8.

The timing diagram for Moore machine model is also shown in Figure 9.

There is no false output in a Moore model, since the output depends only on

the state of the flop flops, which are synchronized with clock. The outputs

remain valid throughout the logic state in Moore model.

7

Figure 9: Timing Diagram for Moore Model Sequence Detector.

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