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Computer Engineering Dept

Engineering

Term 081

Dr. Ashraf S. Hasan Mahmoud

Rm 22-148-3

Ext. 1724

Email: ashraf@kfupm.edu.sa

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 1

Counter

• Counter: A register (sequential circuit) that goes

through a pre-determined sequence of states upon the

application of input (clock or other source) pulses

• Binary Counter: The sequence of the states follows

the binary number sequence (e.g. 000 Æ 001 Æ 010

Æ 011 Æ etc.)

• n-bit binary counter requires n flip-flops – counts from 0 to 2n-

1

• Two Types of Counters:

1. Ripple counter:

• Flip-flop output transition serves as source for triggering the other

flip-flops

2. Synchronous counter: the clock input of all flip-flops receive

the common clock signal

1

Binary Counter

Counting Sequence for Binary Number

Upward Counting Sequence Downward Counting Sequence

No No

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

0 0 0 0 0 15 1 1 1 1

1 0 0 0 1 14 1 1 1 0

2 0 0 1 0 13 1 1 0 1

3 0 0 1 1 12 1 1 0 0

4 0 1 0 0 11 1 0 1 1

5 0 1 0 1 10 1 0 1 0

6 0 1 1 0 9 1 0 0 1

7 0 1 1 1 8 1 0 0 0

8 1 0 0 0 7 0 1 1 1

9 1 0 0 1 6 0 1 1 0

10 1 0 1 0 5 0 1 0 1

11 1 0 1 1 4 0 1 0 0

12 1 1 0 0 3 0 0 1 1

13 1 1 0 1 2 0 0 1 0

14 1 1 1 0 1 0 0 0 1

15 1 1 1 1 0 0 0 0 0

J Q Q0

clock pulses 0 1 2 3 4 5 6 7 8 9 10 11 …

C 1

K Q’

R clock

0 time

1

J Q Q1 Q0

0 time

C 1

K Q’

R Q1

0 time

1

J Q Q2

Q2

0 time

C

1

K Q’

R

Q3

0 time

J Q Q3

C

How to modify this circuit to count downwards:

Logic 1 K Q’

clear’

R

1. Use Q’ as input to C

2. Use +ve edge triggered f/f

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 4

2

Ripple Counter

• Advantages:

• Simple hardware

• Disadvantages:

• Asynchronous – delay dependent

• Clock pulses are applied to the inputs of all of the flip-

flops.

• Design of binary counters

• Same as we learned in Chapter 4!

3

Example: 4-bit Binary Counter

State Table and Flip-Flops Inputs for Binary Counter

Present State Next State Flip-flips inputs

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 JQ3 KQ3 JQ2 KQ1 JQ1 KQ1 JQ0 KQ0

0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X

0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1

0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X

0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1

0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X

0 1 0 1 0 1 1 0 0 X X 0 1 X X 1

0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X

0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1

1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X

1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1

1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X

1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1

1 1 0 0 1 1 0 1 X 0 X 0 0 X 1 X

1 1 0 1 1 1 1 0 X 0 X 0 1 X X 1

1 1 1 0 1 1 1 1 X 0 X 0 X 0 1 X

1 1 1 1 0 0 0 0 X 1 X 1 x 1 x 1

cont’d

Q1 Q0 00 01 11 10 Q1 Q0 00 01 11 10

Q3 Q2 Q1 Q0 00 01 11 10

Q3 Q2

Q3 Q2

00 0 0 0 0 00 0 0 1 0

00 0 1 x x

01 0 0 1 0 01 x x x x

01 0 1 x x

11 x x x x 11 x x x x

11 0 1 x x

10 x x x x 10 0 0 1 0

10 0 1 x x

JQ3 = Q0Q1Q2 JQ2 = Q0Q1 JQ1 = Q0

Q1 Q0 00 01 11 10 Q1 Q0 00 01 11 10

Q3 Q2 Q1 Q0 00 01 11 10

Q3 Q2

Q3 Q2

00 x x x x 00 x x x x

00 x x 1 0

01 x x x x 01 0 0 1 0

01 x x 1 0

11 0 0 1 0 11 0 0 1 0

11 x x 1 0

10 0 0 0 0 10 x x x x

10 x x 1 0

KQ3 = Q0Q1Q2 KQ2 = Q0Q1 KQ1 = Q0

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 8

4

Example: 4-bit Binary Counter –

Implementation

JQ3 = Q0Q1Q2

Q1 Q0 00 01 11 10

Q3 Q2

KQ3 = Q0Q1Q2

00 1 x x 1

01 1 x x 1

11 1 x x 1

JQ2 = Q0Q1

10 1 x x 1 KQ2 = Q0Q1

JQ0 = 1

JQ1 = Q0

Q1 Q0 00 01 11 10

Q3 Q2 KQ1 = Q0

00 x 1 1 x

01 x 1 1 x

11 x 1 1 x JQ0 = 1

10 x 1 1 x

KQ0 = 1

KQ0 = 1

Implementation - continued

• Sometimes it is desirable to control the counter operation

by added a count enable signal: En

• When En = 1 Î counter counts

• When En = 0 Î counter holds state (stops counting)

• Hence the new input equations are:

JQ3 = Q0Q1Q2En, KQ3 = Q0Q1Q2En

JQ2 = Q0Q1En, KQ2 = Q0Q1En

JQ1 = Q0En, KQ1 = Q0En

JQ0 = En, KQ0 = En

5

Example: 4-bit Binary Counter –

Circuit

J Q Q0

Count enable

En C

K Q’

J Q Q1 CTR 4 Q0

C

Q1

K Q’ En

Q2

J Q Q2 Q3

C

K Q’ CO

J Q Q3

C

K Q’

Carry

clock output CO

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 11

Counter

• When En = 0 Î J = K = 0 Î flip-flop holds state

• For general n-bit binary synchronous counter the input

equation for the ith JK flip-flop is:

JQi = KQi = Q0Q1Q2…Qi-1QiEn

• The CO output can be used to extend the counter to

more stages (How?)

• If we use a –ve edge triggered clock, will this circuit

☞ count downwards?

• Draw the state diagram for this counter?

• Binary synchronous counters are MOST efficiently

constructed with complementing T or JK flip-flops – but

can be designed with D flip-flops

6

Problem: 4-bit Binary Counter with

D flip-flops

Problem: Design a 4-bit binary synchronous counter with counter enable (En)

signal

Solution:

State Table and Flip-Flop inputs for Binary Counter

Present State Next State Flip-flips inputs

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 DQ3 DQ2 DQ1 DQ0

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 0

0 0 1 0 0 0 1 1 0 0 1 1

0 0 1 1 0 1 0 0 0 1 0 0

0 1 0 0 0 1 0 1 0 1 0 1

0 1 0 1 0 1 1 0 0 1 1 0

0 1 1 0 0 1 1 1 0 1 1 1

0 1 1 1 1 0 0 0 1 0 0 0

1 0 0 0 1 0 0 1 1 0 0 1

1 0 0 1 1 0 1 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 1 1

1 0 1 1 1 1 0 0 1 1 0 0

1 1 0 0 1 1 0 1 1 1 0 1

1 1 0 1 1 1 1 0 1 1 1 0

1 1 1 0 1 1 1 1 1 1 1 1

1 1 1 1 0 0 0 0 0 0 0 0

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 13

D flip-flops – cont’d

• The flip-flops input equations are given by:

Q1 Q0 00 01 11 10 Q1 Q0 00 01 11 10

Q3 Q2 Q3 Q2

00 1 0 0 1 00 0 0 1 0

01 1 0 0 1 01 1 1 0 1

11 1 0 0 1 11 1 1 0 1

10 1 0 0 1 10 0 0 1 0

Q1 Q0 00 01 11 10 Q1 Q0 00 01 11 10

Q3 Q2 Q3 Q2

00 0 1 0 1 00 0 0 0 0

01 0 1 0 1 01 0 0 1 0

11 0 1 0 1 11 1 1 0 1

10 0 1 0 1 10 1 1 1 1

= Q3 ⊕ (Q2Q1Q0)

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 14

7

Problem: 4-bit Binary Counter with

D flip-flops – cont’d

• Rewriting the input equations and using the count enable signal En:

DQ0 = Q0’ = Q0 ⊕ 1

DQ1 = Q0Q1’+Q0’Q1 = Q1 ⊕ Q0

DQ3 = Q0Q1Q2Q3’+Q2’Q3+Q1’Q3+Q0’Q3

= Q3 ⊕ (Q2Q1Q0)

DQ0 = Q0 ⊕ En = Q0’ if En = 1

= Q0 if En = 0

DQ1 = Q1 ⊕ (Q0En) = Q0Q1’+Q0’Q1 if En = 1

= Q1 if En = 0

to DQi Î i.e flip-flop holds state

DQ2 = Q2 ⊕ (Q0Q1En) = Q0Q1Q2’+Q1’Q2+Q0’Q2 if En = 1

= Q2 if En = 0

= Q3 if En = 0

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 15

D flip-flops – Circuit Diagram

• Notes:

• For a general n-bit

counter, the ith D flip- D Q Q0

En

given by:

Q’

DQi = Qi ⊕ (Q0Q1…Qi-1En) D Q Q1

C

Q’

D Q Q2

C

Q’

D Q Q3

C

Q’

Carry

output CO

clock

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 16

8

Exercise: 4-bit Binary Counter with

T flip-flops

• Problem: Verify that

☞ the circuit shown in

Figure is a 4-bit Count enable

En T Q Q0

synchronous binary C

counter Q’

diagram) T Q Q1

C

Q’

T Q Q2

C

Q’

T Q Q3

C

Q’

Carry

output CO

clock

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 17

Design of 8-bit Binary Counter

• Using 4-bit counters with carry D Q

Q0

C

Count enable

En

C

Q1

enable signal of the next

D Q

Q2

C

C

Q3

output CO1

En Q4

C

D Q

Q5

C

Q6

C

and CO2 D Q

C

Q7

Carry

clock output CO2

9

Serial and Parallel Counters

• When counter changes

state from 1111 to 0000, D Q Q0

how many AND gate Count enable C

delays there will be En τ Q’

before CO is generated?

D Q Q1

C

Q’

stage 1 requires one AND gate

delay to know the state change

in Q0; stage 2 requires one D Q Q2

τ

know the state change in Q1; SERIAL gating

Q’

AND gate delay to know the D Q Q3

state change in Q2; and to C

Carry

gate delay is required. output CO

clock

CO has to be zeros after +ve

edge border since Q0-3=0

8 9 10 11 12 13 14 15 0 1 2

1

clock

0 time 15 0

1

T

Q0

0 time

1

Q1 τ+ τ+τ+τ

0 time

1

Q2

0 time

1

Q3

0 time

1

gi n

CO min

0 Zoo time

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 20

10

Why Serial Gating is Bad?

• Delay taken when CO signal is generated – if this CO

signal is used to drive another counter (refer to 8-bit

counter construction) Î cumulative delay may exceed

clock pulse (or cumulative delay limits speed of counting

– clock frequency)

• Not good for design of fast counters

• Solution: Use parallel gating!

This problem is similar to the delay problem we faced with

the ripple carry adder. The parallel gating is analogous to the

carry lookahead adder idea where the required signals are

Generated without propagating the f/f status from Q0 to Q1 to

Q2 to Q3

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 21

Parallel Gating

• For the D flip-flop synchronous binary counter, the

equations for parallel gating can be taken directly from

the AND terms in the flip-flop input equations on slide 15

D Q

Q0

Count enable C

En

D Q

Q1

C

serial gating

parallel

D Q

Q2

C

gating

D Q Q3

C

Carry Carry

outputoutput

CO CO

clock

serial counter

parallel counter: ONE AND gate delay (τ) is required to generate CO

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 22

11

Serial-Parallel Counter

• Each stage (4-bit counter) is constructed using parallel

gating

• Stages are connected in series by using the CO output of

one stage as the counter enable input of the next state

CTR 4 Q0

En Q1

Parallel counter

Q2

Q3 Same as in the case for the

CO

carry lookahead adder, there

Serial-parallel counter exist solution to speed up the

CTR 4 Q4

transfer of CO signal from one

En Q5 stage to the next

Parallel counter

clock Q6

Q7

CO

Maximum Frequency

Problem: A 64-bit synchronous parallel counter is to be

designed

(a) Draw the logic diagram of a 64-bit parallel counter using

8-bit parallel counter blocks and two levels of parallel

gating connections between the blocks. In these blocks

CO is not driven by En

12

Problem: Solution

En

1st 32-bit parallel counter

En En CO0

En CTR 8 En CTR 8 CO1

CO0

Clock Q0-Q7 CO0 Q8-Q15 CO1

Parallel Gating

En En CO0-31

CO0 CO0

En CTR 8 CO1 En CTR 8 CO1

CO2

CO2 CO3

Q16-Q23CO2 Q24-Q31CO3

Serial Gating

2nd 32-bit parallel counter

CO0-31

CO0-31 CO0

En CTR 8 En CTR 8 CO1

CO0

Q32-Q39CO0 Q40-Q47CO1

Parallel Gating

CO0-31 CO0-31

CO0 CO0

En CTR 8 CO1 En CTR 8 CO1

CO2

CO2 CO3

Q48-Q55CO2 Q56-Q63CO3

• Notes:

• Each of the CTR 8 blocks is a parallel counter (i.e. it uses parallel

gating)

• The 32-bit counter resulting from connecting the first (or

second) 4 8-bit block counters is a also a parallel counter since it

uses parallel gating to generate the CO signals

• The 2 32-bit counters are serially connected to form the required

64-bit counter

☞ • Would it be possible to use only parallel gating to obtain the 64-

bit counter? What would be the maximum fan in for the used

AND gates in this case?

13

Synchronous Binary Down-Counter

• Problem: Design a 4-bit synchronous T flip-flop down-

counter.

• Solution: (show that the previous circuits work as a down-

counter if we use Q’ instead of Q in the input equations;

i.e the as input to the AND gates – This applies to the JK

flip-flop counter on slide 11, the D flip-flop counter on

slide 16 and the T flip-flop counter on slide 17)

package – same problem but using JK F/Fs

• Problem: Design a synchronous up-down T flip-flop 2-bit

binary counter with a select input line S and a count

enable En input. When S = 0, the counter counts down;

and when S = 1, the counter counts up. When En = 1, the

counter is in normal up- or down- counting; and En = 0

for disabling both counts.

• Solution: Required mode of operation:

Inputs

Operation

En S

0 x Hold status

Functional Table: 1 0 Count Down

1 1 Count Up

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 28

14

State Diagram/Table for 2-bit Up-

Down Binary Counter

10 T flip-flops

00 00 Present State Inputs Next State

01 00 01

01

11 No Q1 Q0 En S No Q1 Q0 TQ1 TQ0

0 0 0 0 0 0 0 0 0 0

10 11 11 10

0 0 0 0 1 0 0 0 0 0

11 0 0 0 1 0 3 1 1 1 1

11 10

00 00 0 0 0 1 1 1 0 1 0 1

01 01

10 1 0 1 0 0 1 0 1 0 0

1 0 1 0 1 1 0 1 0 0

Arc Label: EnS 1 0 1 1 0 0 0 0 0 1

1 0 1 1 1 2 1 0 1 1

2 1 0 0 0 2 1 0 0 0

2 1 0 0 1 2 1 0 0 0

T Flip-Flop 2 1 0 1 0 1 0 1 1 1

Q(t) Q(t+1) T 2 1 0 1 1 3 1 1 0 1

0 0 0 3 1 1 0 0 3 1 1 0 0

0 1 1 3 1 1 0 1 3 1 1 0 0

1 0 1 3 1 1 1 0 2 1 0 0 1

1 1 0 3 1 1 1 1 0 0 0 1 1

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 29

Binary Counter

• The carry out signals:

EnS 00 01 11 10 • COup and COdown

Q1 Q0

00 0 0 0 1

01 0 0 1 0

COup = Q0Q1EnS Î counter reached 11 and it is counting

11 0 0 1 0

up

10 0 0 0 1

EnS 00 01 11 10 counting down

Q1 Q0

00 0 0 1 1

01 0 0 1 1

11 0 0 1 1

10 0 0 1 1

TQ0 = En

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 30

15

Circuit for 2-bit Up-Down Binary

Counter

En Q0

TQ0 Q0

TQ1 = Q0EnS + Q0’EnS’

C Q0’

TQ0 = En

S

COup = Q0Q1EnS Q1

TQ1 Q1

clock

En COup

S

Q0

Q1

En COdown

S’

The F/Fs can be +ve or -ve edge triggered Q0’

Q1’

This would NOT affect the equations or the implementation

It would, however, effect when the F/Fs can change state

– see the timing diagram on next slide

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 31

Counter –Timing Diagrams Assume En = 1

-ve edge trig F/Fs

clock 0

(11)2=3 (10)2=2 (01)2=1 (00)2=0 (11)2=3 (10)2=2 (11)2=3 (00)2=0 (01)2=1 (10)2=2 (11)2=3 (00)2=0 time

1

Q0 0

time

1

Q1 0

time

1

S 0

time

COup 0

time

COdown 0

time

(S=0) counting up (S=1)

Ashraf S. Hasan Mahmoud 32

16

4-bit Up-Down Binary Counter

☞ • You can show that input equations for 4-bit up-down

binary counter are given by (compare to 2-bit case):

TQ0 = En

TQ1 = Q0.S.En + Q0’.S’.En

TQ2 = Q1.Q0.S.En + Q1’.Q0’.S’.En

TQ3 = Q2.Q1.Q0.S.En + Q2’.Q1’.Q0’.S’.En

COup = Q0.Q1.Q2.Q3.S.En

COdown = Q0’.Q1’.Q2’.Q3’.S’.En

• Counter with parallel load: capability for transferring

an initial binary number into the counter prior to the count

operation

17

Binary Counter with Parallel Load -

Circuit

En

Load

Inputs

D0 J Q Q0 Operation

C Load En

K Q’

0 0 Hold status

0 1 Count Up

D1 J Q Q1

C 1 x Transfer of data

K Q’

D2 J Q Q2

C

CTR 4

K Q’ Q0

Load

Q1

En

D3 Q2

J Q Q3

D0 Q3

C

K Q’ D1

VERY useful

CO

D2 (versatile) circuit

Carry

output CO D3

1/11/2009 clock Dr. Ashraf S. Hasan Mahmoud 35

BCD Counter

• BCD Counter:

0000Æ0001Æ0010Æ…Æ1000Æ1001Æ0000Æ0010Æ…

• We can use the use binary counter with load (previous

slide) as follows:

CTR 4

Q0

Load

Q1

1 En

Note: When Q3Q2Q1Q0 = 1001, D0

Q2

Q3

the load signal is equal to 1 and D1

CO

the counter loads 0000 and starts D2

D3

counting again 0

18

Other Counters

• Divide-by-N counter OR Modulo-N counter: A

counter that goes through a repeated sequence of N state

• This is the general definition of the counter

• The 4-bit Binary counter Î divide-by-16 counter or

modulo-16 counter (because we have 16 states)

• Problem: Design a BCD counter (without En) using T flip-

flops with an output signal that can be used to extend the

counter

• Solution:

• Let’s design one state (4-bit BCD which counts 0000Æ0001Æ …

Æ1000Æ1001Æ0000Æ …)

• Use the output 1001 to generate the carry out signal

19

BCD Counter – State Table

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Y TQ8 TQ4 TQ2 TQ1

0 0 0 0 0 0 0 1 0 0 0 0 1

0 0 0 1 0 0 1 0 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 0 1

0 0 1 1 0 1 0 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 0 1

0 1 0 1 0 1 1 0 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 0 1

T Flip-Flop

0 1 1 1 1 0 0 0 0 1 1 1 1

Q(t) Q(t+1) T

0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1

0 1 1 1 0 0 1 0 0 0 0 1 1 0 0 1

1 0 1

1 1 0

x

Q2 Q1 00 01 11 10 Q2 Q1 00 01 11 10

Q8 Q4 Q8 Q4

00 1 1 1 1 00 0 0 1 0

01 1 1 1 1 01 0 0 1 0

11 1 x x x 11 x x x x

10 1 1 x x 10 0 0 x x

Q2 Q1 00 01 11 10 Q2 Q1 00 01 11 10

Q8 Q4 Q8 Q4

00 0 1 1 0 00 0 0 0 0

01 0 1 1 0 01 0 0 1 0

11 x x x x 11 x x x x

10 0 0 x x 10 0 1 x x

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 40

20

BCD Counter – Input Equation

1 T Q Q1

C

TQ1 = 1 Q’

TQ2 = Q1Q8’ Q1

Q8’

T Q Q2

C

TQ4 = Q1Q2

Q’

Q1

T Q Q4

Q2

C CTR 4

Y = Q8Q1 Q0

Q’

Q1

Q1 Q2

Q2

Q4 T Q Q8 Q3

Q1 CO

C

Q8 Q’

Y or CO

clock

• Synchronous BCD counters (same as the one built in

previous slide) can be cascaded to form counters for

decimal numbers of any length

☞

• Exercise 1: Using the logic diagram of previous slide,

design a counter which counts from 0 till 99 and then

☞

repeats

• Exercise 2: Given synchronous BCD counter with parallel

load blocks (on slide 31) and perhaps using other logic

gates design a stop watch that times up to one minute

• What should be the frequency of the driving clock signal?

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 42

21

Arbitrary Count Sequence

• Problem: Design a counter that has a repeated sequence

of 6 states, as listed in table. In this sequence, flip-flops B

and C repeat the binary count 00, 01, 10, while flip-flop A

alternates between 0 and 1 every three counts.

• Solution:

Present Next State

State

A B C A B C

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 0 0 0

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 43

Table

• Assuming JK flip-flops

State

A B C A B C JA KA JB KB JC KC

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 1 0 0 1 X X 1 0 X

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 1 1 0 X 0 1 X X 1

1 1 0 0 0 0 X 1 x 1 0 x

22

Arbitrary Count Sequence – Input

Equations

BC 00 01 11 10 BC 00 01 11 10 BC 00 01 11 10

A A A

0 0 0 x 1 0 0 1 x x 0 1 x x 0

1 x x x x 1 0 1 x x 1 1 x x 0

JA = B JB = C JC = B’

BC 00 01 11 10 BC 00 01 11 10 BC 00 01 11 10

A A A

0 x x x x 0 x x x 1 0 x 1 x x

1 0 0 x 1 1 x x x 1 1 x 1 x x

KA = B KB = 1 KC = 1

and Unused States

JA A

C

000 111

KA A’

001 110

JB B

C

B’ 010 101

KB

JC C

100 011

C

KC C’

Logic 1

clock 111 or state 011? Will the counter be able

to proceed (count) normally afterward?

How?

23

Problem:

• Problem: Using the two binary counters shown in figure

and logic gates, construct a binary counter that counts

from 9 through binary 69. Add an additional input to the

counter that initializes it synchronously to 9 when the INIT

is 1

CTR 4 CTR 4

Q0 Q0

Load Load

Q1 Q1

En En

Q2 Q2

D0 D0 Q3

Q3

D1 D1

CO CO

D2 D2

D3 D3

Problem: Solution

• Solution:

The key word in the problem statement is “BINARY”

Hence the designed counter should count in binary from

binary 9 through binary 69 and then back to binary 9 and

so on

Binary 69 Î 0100 0101

Hence it is obvious that the two counters providing 8 Qs are

enough to represent 69

24

Problem 5-23: Solution-cont’d

No Binary

• Solution: Q7Q6Q5Q4 Q3Q2Q1Q0

9 0000 1001

• The counting sequence is as shown in table

10 0000 1010

• Note that: 11 0000 1011

• The we can assign first bit counter to count 12 0000 1100

Q3Q2Q1Q0 while the second is assigned . .

Q7Q6Q5Q4 15 0000 1111

• Note that second counter increments count 16 0001 0000

only if Q3Q2Q1Q0 is equal to 1111; i.e the 17 0001 0001

CO signal first counter is 1 18 0001 0010

19 0001 0011

• During count – first counter counts

20 0001 0100

normally from 01001 all the way to 1111

21 0001 0101

and back to 0000, 0001, etc except when

. .

binary 69 is reached – 1001 is reloaded

68 0100 0100

again

69 0100 0101

• During count – second counter counts 9 0000 1001

normally from 0000 all the way to 0100 10 0000 1010

and then it restarts from 0000 again. . .

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 49

Problem: Solution-cont’d

clock

INIT Q0 Q4

Load Load

Q1 Q5

1 En En

Q2 Q6

1 D0 0 D0

Q3 Q7

0 D1 0 D1

CO CO

0 D2 0 D2

1 D3 0 D3

25

Exercise: BCD Counter

• Problem: Using the two binary counters shown in figure

and logic gates, construct a BCD counter that counts from

9 through BCD 69. Add an additional input to the counter

that initializes it synchronously to 9 when the INIT is 1

CTR 4 CTR 4

Q0 Q0

Load Load

Q1 Q1

En En

Q2 Q2

D0 D0 Q3

Q3

D1 D1

CO CO

D2 D2

D3 D3

No Binary

Solution: Q7Q6Q5Q4 Q3Q2Q1Q0

• The key word in the problem statement is 9 0000 1001

“BCD”

10 0001 0000

11 0001 0001

• The counting sequence is as shown in 12 0001 0010

table: . .

• Counter 1 (Q3Q2Q1Q0) counts 9, 0, 1,2, …, 15 0001 0101

9, 0 and so on 16 0001 0110

• Counter 1 increments every clock cycle 17 0001 0111

• Counter 2 (Q7Q6Q5Q4) counts 0, 1, 2, 3, 4, 18 0001 1000

5, 6, 0, 1, and so on 19 0001 1001

• Counter 2 increments every time counter 1 20 0010 0000

reaches 1001 21 0010 0001

• Counter 1 loads . .

• 0000 when 9 is reached; OR 68 0110 1000

• 1001 if INIT is 1 or 69 is reached 69 0110 1001

• Counter 2 loads 0000 when 69 is reached 9 0000 1001

or when INIT is 1 10 0001 0000

. .

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 52

26

Exercise: BCD Counter – cont’d

INIT clock

`

CTR 4 (1) CTR 4 (2)

Q0 Q4

Load Load

Q1 Q5

1 En En

Quad Q2 Q6

S0

2-to-1 O D0 0 D0

0 I00 MUX

0

Q3 Q7

0 I01 O1 D1 0 D1

0 I02 CO CO

0 I03 O2 D2 0 D2

1 I10 O3 D3 0 D3

0 I11

0 I12

1 I13

End of 0-6 sequence (CTR 2) line

The circuit can be built without using the MUX as shown in next slide

1/11/2009 Dr. Ashraf S. Hasan Mahmoud 53

INIT clock

`

CTR 4 (1) CTR 4 (2)

Q0 Q4

Load Load

Q1 Q5

1 En En

Q2 Q6

D0 0 D0

Q3 Q7

0 D1 0 D1

CO CO

0 D2 0 D2

D3 0 D3

End of 0-6 sequence (CTR 2) line

27

Problem:

• Problem: Using the binary counter shown in figure and

logic gates, construct a binary counter that counts from 3

through binary 12.

CTR 4

Q0

Load

Q1

En

Q2

D0 Q3

D1

CO

D2

D3

Problem:

• Solution:

28

Problem:

29

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