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Computer Engineering Dept

Engineering

Term 081

Dr. Ashraf S. Hasan Mahmoud

Rm 22-148-3

Ext. 1724

Email: ashraf@kfupm.edu.sa

12/28/2008 Dr. Ashraf S. Hasan Mahmoud 1

Magnitude Comparator

• Definition: A magnitude comparator is a combinational circuit that

compares two numbers A & B to determine whether:

• A > B, or

• A = B, or

• A<B

• Inputs n-bit input n-bit magnitude GT

comparator

A

• First n-bit number A

• Second n-bit number B EQ

• Outputs n-bit input

1. GT = 1 IFF A > B

2. EQ = 1 IFF A = B

3. LT = 1 IFF A < B

• Note: Exactly One of these 3 outputs equals 1, while the other 2

outputs are 0`s

1

Design Example 1: Magnitude

Comparator

• Problem: Design a magnitude comparator that

compares 2 4-bit numbers A and B and determines

whether:

• A > B, or

• A = B, or

• A<B

• Inputs: 8-bits (A ⇒ 4-bits , B ⇒ 4-bits)

• A and B are two 4-bit numbers

• Let A = A3A2A1A0 , and

• Let B = B3B2B1B0

• Inputs have 28 (256) possible combinations (size of

truth table and K-map?)

• Not easy to design using conventional techniques

n-bit input 4-bit magnitude GT

A comparator

EQ

n-bit input

⇒ can be designed algorithmically.

12/28/2008 Dr. Ashraf S. Hasan Mahmoud 4

2

4-bit Magnitude Comparator: Design

of the EQ Output

• When two binary numbers are EQUAL?

• Define Xi = Ai XNOR Bi = Ai Bi + Ai’ Bi’

• Î Xi = 1 IFF Ai = Bi ∀ i =0, 1, 2 and 3

• Î Xi = 0 IFF Ai ≠ Bi

• Therefore the condition for A = B or EQ=1 IFF

1. A3=B3 → (X3 = 1), and

2. A2=B2 → (X2 = 1), and

3. A1=B1 → (X1 = 1), and

4. A0=B0 → (X0 = 1).

• Thus, EQ=1 IFF X3 X2 X1 X0 = 1. In other words,

EQ = X3 X2 X1 X0

of the GT Output

• When can you say that A is GREATER THAN B?

• Irrespective of the relative values of the other bits of A & B.

• Example, A = 1000 and B = 0111 where A > B.

• This can be stated as GT=1 if A3 B3’ =1

significant pair of bits (A2 & B2)

• If A2 > B2 then A > B (GT=1) irrespective of the relative values of

the other bits of A & B.

• Example, A = 0100 and B = 0011 where A > B.

• This can be stated as GT=1 if X3 A2 B2’ =1

12/28/2008 Dr. Ashraf S. Hasan Mahmoud 6

3

4-bit Magnitude Comparator: Design

of the GT Output – cont’d

• Case 3: If A3 = B3 (X3 = 1) and A2 = B2 (X2 =

1), we compare the next significant pair of bits (A1 &

B1).

• If A1 > B1, then A > B (GT=1)

• Irrespective of the relative values of the other bits of A & B.

• Example, A = 0010 and B = 0001 where A > B

• This can be stated as GT=1 if X3 X2 A1 B1’

1) and A1 = B1 (X1 = 1), we compare the next pair

of bits (A0 & B0).

• If A0 > B0 then A > B (GT=1).

• This can be stated as GT=1 if X3 X2 X1 A0 B0’ = 1

12/28/2008 Dr. Ashraf S. Hasan Mahmoud 7

of the GT Output – cont’d

• To summarize, GT =1 (A > B) IFF:

• A3 B3’ = 1, OR

• X3 A2 B2’ = 1, OR

• X3 X2 A1 B1’ = 1, OR

• X3 X2 X1 A0 B0’ = 1, OR

• In other words,

GT = A3 B3’ + X3 A2 B2’ + X3 X2 A1 B1’

+ X3 X2X1 A0 B0’

4

4-bit Magnitude Comparator: Design

of the LE Output – cont’d

• In the same manner as for the GT output, we can

derive the expression of the LT (A < B) output

+ X3 X2 X1 B0 A0’

• Three functions:

EQ = X3 X2 X1 X0

GT = A3 B3’ + X3 A2 B2’ + X3 X2

A1 B1’ + X3 X2X1 A0 B0’

LT = B3 A3’ + X3 B2 A2’ + X3 X2

B1 A1’ + X3 X2 X1 B0 A0’

5

4-bit Magnitude Comparator:

Modification

• Do you need all three outputs?

• Example: when A is NOT GREATER THAN B, and A is NOT

LESS THAN B THEN A is EQUAL TO B

4-bit input 4-bit magnitude GT

A comparator

EQ

EQ

4-bit input

B LE

Design Example 2:

• Problem: Given two 4-bit unsigned numbers A and B, design a

circuit which outputs the larger of the 2 numbers.

Hint: use a quad 2-1 Mux.

• Solution:

• We need

• 4-bit magnitude comparator to determine which number is greater

• Quad 2-to-1 mux to select between A and B

• The selection signal for the mux must be generated by the comparator

• See circuit

signal and order of inputs 0 and 1 for the mux

6

Design Example 3: Excess-3 Code

Converter

• Problem: Designing an Excess-3 code converter using a Decoder and an

Encoder

• Solution:

• Truth Table is as shown

• The outputs 0000, 0001, 0010, 1101, 1110, and 1111 are never generated

(Why?)

BCD input Excess 3 code

BCD digit W X Y Z A B C D

4-to-16 line Decoder 16-to-4 line Encoder 0 0 0 0 0 0 0 1 1

O0 I0

O1 I1 1 0 0 0 1 0 1 0 0

O2 I2

O3 I3 2 0 0 1 0 0 1 0 1

O4 I4

D0 O5 I5 3 0 0 1 1 0 1 1 0

I6 D0

D1 O6

D2 O7 I7 D1 4 0 1 0 0 0 1 1 1

I8 D2

D3 O8

O9 I9 D3 5 0 1 0 1 1 0 0 0

O10 I10

O11 I11 6 0 1 1 0 1 0 0 1

O12 I12

O13 I13 7 0 1 1 1 1 0 1 0

O14 I14

O15 I15 8 1 0 0 0 1 0 1 1

9 1 0 0 1 1 1 0 0

Example 3: cont’d

• Solution:

• What do you think the output of the encoder will be?

4-to-16 line Decoder 16-to-4 line Encoder

O0 I0

O1 I1

O2 I2

O3 I3

O4 I4

Z O5 I5

D0 D0 ?

I6

Y D1 O6

D1 ?

O7 I7

X D2

I8 D2 ?

W D3 O8

I9 D3 ?

O9

O10 I10

O11 I11

O12 I12

O13 I13

O14 I14

O15 I15

Output: D0 = Z, D1 = Y, D2 = X, D3 = W

So we get exact same code out!!

12/28/2008 Dr. Ashraf S. Hasan Mahmoud 14

7

Example 3: cont’d

• Solution:

• We need to shift

minterm 3 of the decoder. This output is connected to input 6 of

encoder. Thus the encoder will generate the corresponding bit

combination, which is 0110.

16-to-4 line Encoder

I0

I1

4-to-16 line Decoder I2

I3

O0

I4

O1

I5

O2 D

I6 D0

O3

I7 D1 C

O4

I8 D2 B

Z D0 O5

I9 D3 A

Y D1 O6

I10

X D2 O7

I11

W D3 O8

I12

O9

I13

O10

I14

O11

I15

O12

O13

O14

O15

Design Example 4:

• Problem: Design a circuit that adds three 4-bit

numbers – utilize 4-bit adder blocks and half/full

adder blocks

• Solution: refer to the last example in the adder

slides

8

Design Example 5:

• Problem: Design a 4-to-16 Decoder using five 2-to-

4 Decoders with enable inputs. No extra logic is to be

used.

• Solution:

• Solution:

• How does a 2-to-4 decoder with Enable looklike?

• How does a 4-to-16 decoder looklike?

E A1 A0 D0 D1 D2 D3

4-to-16 Decoder

2-to-4 Decoder 1 0 0 1 0 0 0

A0 A0

1 0 1 0 1 0 0 O0

A1 D0 A1 O1

D1 1 1 0 0 0 1 0

O2

D2 A2

1 1 1 0 0 0 1 O3

E D3 A3

0 X X 0 0 0 0 O4

O5

Truth Table O6

O7

O8

O9

It is required to connect 4 boxes of 2-to-4 decoders O10

to obtain the functionality of 4-to-16 decoder O11

O12

O13

E O14

O15

9

Design Example 5: cont’d

• Solution: A3 A2 A1 A0 Output

0 0 0 1 O1

enable the require ONE of FOUR A3A2 = 00 0 0 1 0 O2

2-to-4 decoders 0 0 1 1 O3

• A1A0 always decoded into 4 0 1 0 0 O4

outputs 0 1 0 1 O5

A3A2 = 01

0 1 1 0 O6

0 1 1 1 O7

1 0 0 0 O8

1 0 0 1 O9

A3A2 = 10

1 0 1 0 O10

1 0 1 1 O11

1 1 0 0 O12

1 1 0 1 O13

A3A2 = 11

1 1 1 0 O14

1 1 1 1 O15

A3 A2 A1 A0 Output

• Solution: 0

0

0

0

0

0

0

1

O0

O1

A3A2 = 00 0 0 1 0 O2

0 0 1 1 O3

0 1 0 0 O4

0 1 0 1 O5

A3A2 = 01

0 1 1 0 O6

0 1 1 1 O7

1 0 0 0 O8

1 0 0 1 O9

A3A2 = 10

1 0 1 0 O10

1 0 1 1 O11

1 1 0 0 O12

1 1 0 1 O13

A3A2 = 11

D0 1 1 1 0 O14

D1 1 1 1 1 O15

A0 A0 A0 A0

A1 D0 O0 A1 D0 O4 A1 D0 O8 A1 D0 O12

D1 O1 D1 O5 D1 O9 D1 O13

D2 O2 D2 O6 D2 O10 D2 O14

D3 O3 D3 O7 D3 O11 D3 O15

E E E E

D2 2-to-4 Decoder

A0

A1 D0

D3 D1

D2

1 D3

E

10

Design Example 6:

• Problem: Designing a 16-bit adder using four 4-bit

adders

• Solution:

Textbook Problems

All are important problems!

11

Design Example 7: (similar to

problem 4-21)

• Problem: A combinational circuit is defined by the

following three Boolean functions:

• F1 = (X+Y)’ + XYZ’

• F2 = (X+Y)’ + X’YZ

• F3 = XYZ + (X+Y’)

• Solution:

• Solution:

3-to-8 decoder

• You should write m0=X’Y’Z’

each function in m1=X’Y’Z

terms of its Z m2=X’YZ’

0

minterms: m3=X’YZ

Y m4=XY’Z’

• F1 = Σm(0,1,6) 1

m5=XY’Z

• F2 = Σm(0,1,3) X

2

m6=XYZ’

• F3 = Σm(0,1,7) m7=XYZ

F1

+1

Enable

• Use one OR gate

for each function F2

to sum the

required minterms

F3

12

Design Example 8: Problem 4-19 in

textbook

• Problem: Construct a 15-to-1 line multiplexer with

two 8-to-1 line multiplexers. Interconnect the two

multiplexers and label the inputs such that any added

logic required to have selection codes 0000 through

1110 is minimized.

• Solution:

• Solution:

A3 A2 A1 A0 Output

0 0 0 0 D0 8-to-1 mux

0 0 0 1 D1

A(0-2) S(0-2)

0 0 1 0 D2

0 0 1 1 D3 Y

0 1 0 0 D4 D(0-7) I(0-7)

0 1 0 1 D5

0 1 1 0 D6

0 1 1 1 D7

8-to-1 mux

1 0 0 0 D8 A0

S0

1 0 0 1 D9 A3 S0

A1 S1

1 0 1 0 D10 S1 S2 Y

1 0 1 1 D11 A3

D(8-14) I(0-6)

A2

1 1 0 0 D12 S2

1 1 0 1 D13 A3 I7

D15

1 1 1 0 D14

1 1 1 1

12/28/2008 Dr. Ashraf S. Hasan Mahmoud 26

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