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You are on page 1of 13

Logic gates are physically implemented as Integrated Circuits (IC).

Integrated circuits are implemented in several technologies.

Two landmark IC technologies are the TTL and the CMOS technologies.

Major physical properties of a digital IC depend on the implementation technology.

In this lesson, the following major properties of digital IC’s are described:

1. Allowed physical range of voltages for logic 0 and logic 1,

2. Gate propagation delay/ speed,

3. The fanin and fanout of a gate,

4. The use of buffers, and

5. Tri-State drivers

Practically, logic 0 is represented by a certain Voltages

RANGE of Voltages rather than by a single voltage

level.

.In other words, if the voltage level of a signal falls

Invalid Range

in this range, the signal has a logic 0 value.

Likewise, logic 1 is represented by a different Of Voltages

RANGE of valid voltages.

The range of voltages between the highest logic 0 Valid Logic 0

voltage level and the lowest logic 1 voltage level is Voltages

an “Illegal Voltage Range”.

No signal is allowed to assume a voltage value in this range.

Inputs and outputs of IC’s do not have the same allowed range of voltages neither for

logic 0 nor for logic 1.

VIL is the maximum input voltage that considered a Logic 0.

VOL is the maximum output voltage that considered a Logic 0.

VOL must be lower than VIL to guard against noise disturbance.

Why is VIL > VOL ?

Consider the case of connecting the

output of gate A to the input of

another gate B:

• The logic 0 output of A must

be within the range of

acceptable logic 0 voltages of gate B inputs.

• Voltage level at the input of B = Voltage level at the output of A + Noise

Voltage

• If the highest logic 0 output voltage of A (VOL) is equal to the highest logic 0

input voltage of B (VIL), then the noise signal can cause the actual voltage at

the input of B to fall in the invalid range of voltages.

Valid Logic 1

Voltages

Maximum

Tolerable noise

Invalid Range

Of Voltages

VIL

VOL Valid Logic 00

Valid Logic 0 Input Voltages

Output Voltages

Accordingly, VOL is designed to be lower than VIL to allow for some noise margin.

The difference (VIL - VOL) is thus known as the noise margin for logic 0 (NM0).

VIH is the minimum input voltage that considered a Logic 1.

VOH is the minimum output voltage that considered a Logic 1.

VOH must be higher than VIH to guard against noise signals.

Why is VOH > VIH ?

Allowed Noise

Margin of 0.4v

… VIH=2v

….

A ….

VOH=2.4v …. B

Consider the case of connecting the output of gate A to the input of another gate B:

• The logic 1 output of A must accepted as logic 1 by the input of gate B.

• Thus, the logic 1 output of A must be within the range of voltages which are

acceptable as logic 1 input for gate B.

• If the lowest logic 1 output voltage of A (VOH) is equal to the lowest logic 1

input voltage of B (VIH), then noise signals can cause the actual voltage at the

input of B to fall in the invalid range of input voltages.

Valid Logic 1

Output Voltages Valid Logic 1

V OH

Input Voltages

V IH

Maximum

Tolerable noise

Invalid Range

Of Voltages

Valid Logic 00

Input Voltages

Accordingly, VOH is designed to be higher than VIH to allow for some noise margin.

The difference (VOH - VIH) is thus known as the noise margin for logic 1 (NM1).

Definition

Noise margin is the maximum noise voltage that can be added to the input signal of a

digital circuit without causing an undesirable change in the circuit output..

Valid Logic 1

Valid Logic 1 Voltages

Voltages VOH

NM 1

VIH

VIL

NM 0

Valid Logic 0 VOL

Voltages Valid Logic 0

Voltages

Consider the shown inverter with input X and

output Z.

A change in the input (X) from 0 to 1 X Z

causes the inverter output (Z) to change τ

from 1 to 0. Propagation

Delay = τ

The change in the output (Z), however is

not instantaneous. Rather, it occurs slightly after the input change.

This delay between an input signal change and the corresponding output

signal change is what is known as the propagation delay.

In general,

A signal change on the input of some IC takes a finite amount of time to

cause a corresponding change on the output.

This finite delay time is known as Propagation Delay.

Faster circuits are characterized by smaller propagation delays.

Higher performance systems require higher speeds (smaller propagation

delays).

Timing Diagrams

A timing diagram shows the logic values of signals in a circuit versus

time.

A signal shape versus time is typically referred to as Waveform.

Example

The figure shows the timing diagram of a 2-input AND gate. The gate is

assumed to have a propagation delay of τ.

X Propagation Z

Delay =τ

Y

Y, and Z.

Note how the output Z is delayed from changes of the input signals X &

Y by the amount of the gate Propagation Delay τ.

τ τ τ τ

t

Time

Fanin Limitations

The fanin of a gate is the number of inputs of this gate.

Thus, a 4-input AND gate is said to have a fanin of 4.

A physical gate cannot have a large number of inputs (fanin).

•For CMOS technology, the more inputs a gate has the slower it is (larger

propagation delay). For example, a 4-input AND gate is slower than a 2-

input one.

In CMOS technology, no more than 4-input gates are typically built since

more than 4 inputs makes the devices too slow.

TTL gates can have more inputs (e.g, 8 input NAND 7430).

Fanout Limitations

If the output of some gate A is

connected to the input of another gate B,

gate A is said to be driving gate, while

gate B is said to be the load gate.

As the Figure shows, a driver gate

may have more than one load gate.

There is a limit to the number of gate 1

2

The fanout of a gate is the largest Driver Gate

number of gate inputs this gate can

drive. n

CURRENT.

A TTL output can supply a maximum current IOL = 16 mA (milliamps)

A TTL input requires a current of IIL =1.6mA.

Thus, the fanout for TTL is 16mA/1.6 mA = 10 loads.

For CMOS, the limit is based on SPEED/propagation delay.

A CMOS input resembles a capacitive load (≈10 pf - picofarads).

The more inputs tied to a single output, the higher the capacitive load.

The HIGHER the capacitive load, the SLOWER the propagation delay.

Typically, it is advisable to avoid loads much higher than about 8 loads.

Q. What is meant by the DRIVE of a gate?

A. It is the “CURRENT” driving-ability of a gate. In other words, it is the

amount of current the gate can deliver to its load devices.

A gate with high-drive is capable of driving more load gates than

another with low-drive.

Q. How to drive a number of load gates that is larger than the fanout of the

driver gate?

A. In this case, we can use one of two methods:

1. Use high drive buffers

2. Use multiple drivers. Buffer Symbol

Z=x

x

A buffer is a single input, single output

gate where the logic value of the output

equals that of the input.

The logic symbol of the buffer is shown in the Figure.

The buffer provides the necessary drive capability which allows driving

larger loads.

Note that the symbol of the buffer resembles the inverter symbol except

that it does not have the inverting circle that the inverter symbol has.

The figure shows how the buffer is High Drive

Buffer

used to drive the large load.

1

2

Gate

identical drivers driving the load

gates. n

n> fanout (D)

gates is divided among

1

D1

that each of the identical 2

Driver Gate 1

drivers is driving no more

m Load Gates

than the fanout. n> fanout

The multiple driver gates m+1

m+2

Driver Gate 2

type and should be

connected to the same n

input signals

Tri-State Outputs

A. Generally, Nooooooooooo!!! This is only possible if special types of

gates are used.

Q. Why cann’t the outputs of 2 normal gates be directly connected?

A. Because this causes a short Circuit that results in huge current flow with

a subsequent potential for damaging the circuit.

This is obvious since one output may be at logic 1 (High voltage),

while the other output may be at logic 0 (Low voltage).

Furthermore, the common voltage level of the shorted outputs will

most likely fall in the invalid range of voltage levels.

1

0

Short Circuit

Huge

Current

1

0

Q. What are the types of IC output pins that can be directly connected?

A. These are pins/gates with special output drivers. The two main types are:

Open-Collector outputs Æ this will not be discussed in this course.

Outputs with Tri-State capability.

These gates can be in one of 2 possible states:

1. An enabled state where the output may assume one of two possible

values:

¾ Logic 0 value (low voltage)

¾ Logic 1 value (high voltage)

2. A disabled state where the gate output is in a the Hi-impedance

(Hi-Z) state. In this case, the gate output is disconnected (open-

circuit) from the wire it is driving.

An enable input (E) is used to control the gate into either the enabled or

disabled state.

The enable input (E) may be either active high or active low.

Any gate or IC output may be provided

with tri-state capability. Power Supply

Output State Illustrations VDD

A generalized output driver can be simply

S1

modeled using 2 switches S1 and S0 as

shown in Figure.

Output

The output state is defined by the state of

the 2 switches (closed -open)

S0

If S1 is closed and S0 is open, the output is

high (logic 1) since it is connected to the

power supply (VDD). GND

Power Supply

If S1 is open and S0 is closed, the output VDD

Output = High = Logic1

S0 Open

GND

If, however, both S1 is and S0 are open,

then the output is neither connected to

Power Supply

ground nor to the power supply. In VDD

S1 Open

state. Output = Low = Logic 0

S0 Closed

Examples

GND

a) Tri-State Inverter with active high

Power Supply

enable VDD

S1 Open

E

Output = Hi-Impedance

(Hi-Z)

Logic

Z S0 Open

x G1

Symbol

with active-high enable

Truth E x Z

Table 1 0 1

1 1 0

0 0 Hi-Z

0 1 Hi-Z

E =1

Enabled

Z = x

State x G1 G2

Tri-State Inverter

with active-high enable

E =0 Floating Line

Open Circuit Disconnected

(Hi-Impedance) from G1

Z

x G1 G2

with active-high enable

abled

E =0 Floating Line

State Disconnected

from G1

x G2

In Hi-Z State G1 is

Open Circuit

(Disconnected from

Output line)

E

Logic Z

x G1

Symbol

Tri-State Inverter

with active-low enable

E x Z

Truth 0 0 1

Table 0 1 0

1 0 Hi-Z

1 1 Hi-Z

E=0

Enabled Z = x

x G1 G2

State

Tri-State Inverter

with active-low enable

E =1 Floating Line

Disconnected

Open Circuit from G1

(Hi-Impedance)

Z

x G1 G2

with active-low enable

abled

E =1 Floating Line

State Disconnected

from G1

x G2

In Hi-Z State G1 is

Open Circuit

(Disconnected from

Output line)

Condition for Connecting Outputs of Tri-State Gates

¾ Two or more tri-state outputs may be connected provided that at most one

of these outputs is enabled while all others are in the Hi-Z state.

¾ This avoids conflict situations where one gate output is high while

another is low.

Circuit Examples

inverters with active high enable

inputs.

¾ The outputs of these 2 inverters

are shorted together as a

common output signal Z

¾ The 2 gates are NEVER enabled

at the same time.

¾ G1 is enabled when E=1, while

G2 is enabled when E=0

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